added trb_net_term to trb_net_active_api, Jan

diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd
index 329d26f6df3f80e59f36403e206ed828ef150b05..c3a23e6c8e9278893d9635e4bdb6a571086efbbe 100644 (file)
--- a/trb_net_active_api.vhd
+++ b/trb_net_active_api.vhd
@@ -69,10 +69,11 @@ entity trb_net_active_api is
 
     INT_REPLY_DATAREADY_IN:  in  STD_LOGIC;
     INT_REPLY_DATA_IN:       in  STD_LOGIC_VECTOR (50 downto 0); -- Data word
-    INT_REPLY_READ_OUT:      out STD_LOGIC
+    INT_REPLY_READ_OUT:      out STD_LOGIC;
 
     -- Status and control port
-
+    STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+    STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
     -- not needed now, but later
 
     );
@@ -80,6 +81,7 @@ END trb_net_active_api;
 
 architecture trb_net_active_api_arch of trb_net_active_api is
 
+
 component trb_net_fifo is
   generic (WIDTH : integer := 8;       -- FIFO word width
            DEPTH : integer := 4);     -- Depth of the FIFO, 2^(n+1)
@@ -141,6 +143,50 @@ component trb_net_dummy_fifo is
     );
   END component;
 
+
+
+component trb_net_term is
+
+  generic (FIFO_TERM_BUFFER_DEPTH  : integer := 0);  -- fifo for auto-answering of
+                                               -- the master path, if set to 0
+                                               -- no buffer is used at all 
+  port(
+    --  Misc
+    CLK    : in std_logic;             
+    RESET  : in std_logic;     
+    CLK_EN : in std_logic;
+    
+    -- Internal direction port
+    -- This is just a clone from trb_net_iobuf 
+        
+    INT_DATAREADY_OUT: out STD_LOGIC;
+    INT_DATA_OUT:      out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+    INT_READ_IN:       in  STD_LOGIC; 
+
+    INT_DATAREADY_IN:  in  STD_LOGIC;
+    INT_DATA_IN:       in  STD_LOGIC_VECTOR (50 downto 0); -- Data word
+    INT_READ_OUT:      out STD_LOGIC;
+
+    -- "mini" APL, just to see the triggers coming in
+    APL_DTYPE_OUT:         out STD_LOGIC_VECTOR (3 downto 0);  -- see NewTriggerBusNetworkDescr
+    APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+    APL_SEQNR_OUT:         out STD_LOGIC_VECTOR (7 downto 0);
+    APL_GOT_TRM:           out STD_LOGIC;
+
+    APL_HOLD_TRM:          in STD_LOGIC;
+    APL_DTYPE_IN:          in STD_LOGIC_VECTOR (3 downto 0);  -- see NewTriggerBusNetworkDescr
+    APL_ERROR_PATTERN_IN:  in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+
+        APL_MY_ADDRESS_IN: in  STD_LOGIC_VECTOR (15 downto 0)  -- My own address (temporary solution!!!)
+    -- Status and control port
+
+    -- not needed now, but later
+
+    );
+END component trb_net_term;
+
+
+
 -- signals for the APL to INT fifo:
 signal fifo_to_int_data_in : std_logic_vector(47 downto 0);
 signal fifo_to_int_write : std_logic;
@@ -192,6 +238,27 @@ signal out_select:OUTPUT_SELECT;
 
 begin
 
+TrbNetTerm: trb_net_term
+
+  generic map(FIFO_TERM_BUFFER_DEPTH => 0)
+  port map(
+    CLK       => CLK,
+    RESET     => RESET,
+    CLK_EN    => CLK_EN,
+    INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
+    INT_DATA_OUT      => INT_REPLY_DATA_OUT,
+    INT_READ_IN       => INT_REPLY_READ_IN, 
+    INT_DATAREADY_IN  => INT_INIT_DATAREADY_IN,
+    INT_DATA_IN       => INT_INIT_DATA_IN,
+    INT_READ_OUT      => INT_INIT_READ_OUT,
+    APL_HOLD_TRM      => '0',
+    APL_DTYPE_IN      => (others => '0'),
+    APL_ERROR_PATTERN_IN => (others => '0'),
+       APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN
+    );
+
+
+
   CHECK_BUFFER3:   if FIFO_TO_INT_DEPTH >0 generate
   FIFO_TO_INT: trb_net_fifo
     generic map (
@@ -208,7 +275,19 @@ begin
       FULL_OUT  => fifo_to_int_full,
       EMPTY_OUT => fifo_to_int_empty
       );
+
+  STAT_FIFO_TO_INT(2 downto 0)  <= fifo_to_int_data_in(2 downto 0);
+  STAT_FIFO_TO_INT(3)           <= fifo_to_int_write;
+  STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0);
+  STAT_FIFO_TO_INT(11)           <= fifo_to_int_read;
+  STAT_FIFO_TO_INT(14)           <= fifo_to_int_full;
+  STAT_FIFO_TO_INT(15)           <= fifo_to_int_empty;
+  STAT_FIFO_TO_INT(7 downto 4)  <= (others => '0');
+  STAT_FIFO_TO_INT(13 downto 12)  <= (others => '0');
+  STAT_FIFO_TO_INT(31 downto 16) <= (others => '0');
   end generate CHECK_BUFFER3;
+
+
   CHECK_BUFFER4:   if FIFO_TO_INT_DEPTH =0 generate
       FIFO_TO_INT: trb_net_dummy_fifo
     generic map (
@@ -257,6 +336,16 @@ begin
       FULL_OUT  => fifo_to_apl_full,
       EMPTY_OUT => fifo_to_apl_empty
       );
+
+      STAT_FIFO_TO_APL(2 downto 0)  <= fifo_to_apl_data_in(2 downto 0);
+      STAT_FIFO_TO_APL(3)           <= fifo_to_apl_write;
+      STAT_FIFO_TO_APL(10 downto 8) <= fifo_to_apl_data_out(2 downto 0);
+      STAT_FIFO_TO_APL(11)           <= fifo_to_apl_read;
+      STAT_FIFO_TO_APL(14)           <= fifo_to_apl_full;
+      STAT_FIFO_TO_APL(15)           <= fifo_to_apl_empty;
+      STAT_FIFO_TO_APL(7 downto 4)  <= (others => '0');
+      STAT_FIFO_TO_APL(13 downto 12)  <= (others => '0');
+      STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
       end generate CHECK_BUFFER6;
 
    

diff --git a/trb_net_io_multiplexer.vhd b/trb_net_io_multiplexer.vhd
index 1e5b56d8512d9fcc9eaec44aff516db6ca3475d6..08263bddbdf0cf9f88d442f5bacd739eb4f3850e 100644 (file)
--- a/trb_net_io_multiplexer.vhd
+++ b/trb_net_io_multiplexer.vhd
@@ -128,7 +128,7 @@ architecture trb_net_io_multiplexer_arch of trb_net_io_multiplexer is
 
     G1: for i in  0 to 2**MULT_WIDTH-1 generate
       DEMUX_SBUF: trb_net_sbuf
-        generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH)
+        generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 1)
         port map (
           CLK   => CLK,
           RESET  => RESET,
@@ -215,7 +215,7 @@ INT_READ_OUT <=  tmp_INT_READ_OUT;
 
   
   MUX_SBUF: trb_net_sbuf
-    generic map (DATA_WIDTH => BUS_WIDTH)
+    generic map (DATA_WIDTH => BUS_WIDTH, VERSION => 1)
     port map (
       CLK   => CLK,
       RESET  => RESET,
@@ -241,7 +241,7 @@ process (tmp_INT_READ_OUT, INT_DATA_IN)
     end loop;
   end process;
   
-  mux_enable <= (MED_READ_IN or mux_next_READ);
+  mux_enable <= (mux_next_READ); -- or MED_READ_IN
   mux_read <= or_all(tmp_INT_READ_OUT and INT_DATAREADY_IN);
   
 end trb_net_io_multiplexer_arch;

diff --git a/trb_net_obuf.vhd b/trb_net_obuf.vhd
index e5042b7c0885e310fff98f49740688571f9d211a..2bf3945d47f52b11cacec2a5ebb734871de11ace 100644 (file)
--- a/trb_net_obuf.vhd
+++ b/trb_net_obuf.vhd
@@ -38,7 +38,8 @@ architecture trb_net_obuf_arch of trb_net_obuf is
 
   component trb_net_sbuf is
 
-  generic (DATA_WIDTH : integer := 56);
+  generic (DATA_WIDTH : integer := 56;
+            VERSION : integer := 1);
 
   port(
     --  Misc
@@ -88,7 +89,7 @@ architecture trb_net_obuf_arch of trb_net_obuf is
   begin
 
     SBUF: trb_net_sbuf
-        generic map (DATA_WIDTH => 51)
+        generic map (DATA_WIDTH => 51, VERSION => 1)
         port map (
           CLK   => CLK,
           RESET  => RESET,

diff --git a/trb_net_term_ibuf.vhd b/trb_net_term_ibuf.vhd
index 7ebc53e8fcbf714a5515941e81b56e4184368a8e..a39b19b2800687536bed1211229633c26286e5a8 100644 (file)
--- a/trb_net_term_ibuf.vhd
+++ b/trb_net_term_ibuf.vhd
@@ -43,7 +43,8 @@ architecture trb_net_term_ibuf_arch of trb_net_term_ibuf is
 
   component trb_net_sbuf is
 
-  generic (DATA_WIDTH : integer := 56);
+  generic (DATA_WIDTH : integer := 56;
+            VERSION : integer := 1);
 
   port(
     --  Misc
@@ -145,7 +146,7 @@ reg_buffer: process(CLK)
 
 
   SBUF: trb_net_sbuf
-    generic map (DATA_WIDTH => 51)
+    generic map (DATA_WIDTH => 51, VERSION => 0)
     port map (
       CLK   => CLK,
       RESET  => RESET,