--- /dev/null
+--checks the data stream generated by pseudo_random_stream_generator
+--width of compared bits is configurable via generics
+
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity pseudo_random_stream_checker is
+ generic(
+ WIDTH : integer := 16
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ D_IN : in std_logic_vector(15 downto 0);
+ D_EN : in std_logic;
+ D_RST : in std_logic;
+ FAIL : out std_logic
+ );
+end entity;
+
+
+
+architecture arch of pseudo_random_stream_checker is
+
+ component trb_net_CRC is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ CRC_OUT : out std_logic_vector(15 downto 0);
+ CRC_match : out std_logic
+ );
+ end component;
+
+ signal test_counter : unsigned(20 downto 0);
+ signal CRC_reset : std_logic;
+ signal last_D_EN : std_logic;
+ signal last_D_RST : std_logic;
+ signal last_D_IN : std_logic_vector(15 downto 0);
+ signal CRC_out : std_logic_vector(15 downto 0);
+
+begin
+
+ THE_CRC : trb_net_CRC
+ port map(
+ CLK => CLK,
+ RESET => CRC_reset,
+ CLK_EN => D_EN,
+ DATA_IN => std_logic_vector(test_counter)(15 downto 0),
+ CRC_OUT => CRC_out,
+ CRC_match => open
+ );
+
+ CRC_reset <= RESET or D_RST;
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_D_RST <= D_RST;
+ last_D_EN <= D_EN;
+ last_D_IN <= D_IN;
+
+ if last_D_EN = '1' and last_D_RST = '0' then
+ if CRC_out(WIDTH-1 downto 0) = std_logic_vector(last_D_IN(WIDTH-1 downto 0)) then
+ FAIL <= '0';
+ else
+ FAIL <= '1';
+ end if;
+ end if;
+
+ if last_D_RST = '1' then
+ test_counter <= (others => '0');
+ else
+ test_counter <= test_counter + 1;
+ end if;
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+--produces a stream of 16bit wide pseudo-pseudo-random words
+--(produced by a crc-generator fed with a counter)
+--roughly every fourth word (randomly chosen by a second crc), the output is halted for a clock cycle (shown by D_EN low)
+--every 2^20 words, the D_RST is high for some clock cycles to mark a restart of the sequence.
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity pseudo_random_stream_generator is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ D_OUT : out std_logic_vector(15 downto 0);
+ D_EN : out std_logic;
+ D_RST : out std_logic
+ );
+end entity;
+
+
+
+architecture arch of pseudo_random_stream_generator is
+
+ component trb_net_CRC is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ CRC_OUT : out std_logic_vector(15 downto 0);
+ CRC_match : out std_logic
+ );
+ end component;
+
+
+ signal test_counter : unsigned(20 downto 0);
+ signal CRC_reset : std_logic;
+ signal CRC_enable : std_logic;
+ signal last_CRC_enable : std_logic;
+ signal CRC_out : std_logic_vector(15 downto 0);
+ signal CRC2_out : std_logic_vector(15 downto 0);
+ signal next_D_EN : std_logic;
+ signal next_D_RST : std_logic;
+ signal next_D_OUT : std_logic_vector(15 downto 0);
+
+
+begin
+
+--CRC used as Data stream
+ THE_CRC : trb_net_CRC
+ port map(
+ CLK => CLK,
+ RESET => CRC_reset,
+ CLK_EN => CRC_enable,
+ DATA_IN => std_logic_vector(test_counter(15 downto 0)),
+ CRC_OUT => CRC_out,
+ CRC_match => open
+ );
+
+--CRC generating enable
+ THE_CRC_2 : trb_net_CRC
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+ DATA_IN => std_logic_vector(test_counter(15 downto 0)),
+ CRC_OUT => CRC2_out,
+ CRC_match => open
+ );
+
+ next_D_OUT <= CRC_OUT;
+ next_D_EN <= last_CRC_enable;
+ next_D_RST <= CRC_reset;
+
+ CRC_reset <= and_all(std_logic_vector(test_counter(20 downto 15)));
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ test_counter <= (others => '0');
+ CRC_enable <= '0';
+ D_EN <= '0';
+ D_RST <= '1';
+ else
+ test_counter <= test_counter + 1;
+ D_OUT <= next_D_OUT;
+ D_EN <= next_D_EN;
+ D_RST <= next_D_RST;
+ CRC_enable <= ((CRC2_out(5) or CRC2_out(14)));
+ last_CRC_enable <= CRC_enable;
+ end if;
+ end if;
+ end process;
+end architecture;
\ No newline at end of file
vhdl work "../trb_net16_api_base.vhd"
vhdl work "../trb_net16_iobuf.vhd"
vhdl work "../trb_net16_io_multiplexer.vhd"
-vhdl work "../testbench/trb_net16_dummy_apl.vhd"
+vhdl work "../testbenches/trb_net16_dummy_apl.vhd"
vhdl work "../trb_net16_ipudata.vhd"
vhdl work "../trb_net16_trigger.vhd"
vhdl work "../trb_net16_endpoint_hades_full.vhd"
APL_READ_IN => APL_READ_OUT(0),
APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(0),
APL_DTYPE_OUT => APL_DTYPE_IN(3 downto 0),
- APL_SEND_OUT => APL_SEND_IN(0),
+ APL_SEND_OUT => open,--APL_SEND_IN(0),
APL_DATA_IN => APL_DATA_OUT(15 downto 0),
APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(2 downto 0),
APL_TYP_IN => APL_TYP_OUT(2 downto 0),
APL_READ_IN => APL_READ_OUT(1),
APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(1),
APL_DTYPE_OUT => APL_DTYPE_IN(7 downto 4),
- APL_SEND_OUT => APL_SEND_IN(1),
+ APL_SEND_OUT => open,--APL_SEND_IN(1),
APL_DATA_IN => APL_DATA_OUT(31 downto 16),
APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(5 downto 3),
APL_TYP_IN => APL_TYP_OUT(5 downto 3),
generic map(
TARGET_ADDRESS => x"FFFF",
PREFILL_LENGTH => 3,
- TRANSFER_LENGTH => 10
+ TRANSFER_LENGTH => 1
)
port map(
CLK => CLK,
-- address <= x"0008";
-- reghigh <= x"DEAD";
-- reglow <= x"AFFE";
- reg_F0 <= x"8023"; --x"0001";
+ reg_F0 <= x"5e1d"; --x"0001";
- reg_F1 <= x"8000";
+ reg_F1 <= x"0000";
reg_F2 <= x"0000";--xor_all(APL_DATA_IN) & "000000000000011";
reg_F3 <= x"0000";
- APL_DTYPE_OUT <= x"9";
+ APL_DTYPE_OUT <= x"F";
APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
process(current_state)
jspc29 / trbnet.git / commitdiff