update CTS code with more input options

diff --git a/cts/config_32TDC.vhd b/cts/config_32TDC.vhd
index de7a4b2c0952cf20ffcc98cc801571180befa297..4d642c04c78c3572f58c88b57602dd323e799e93 100644 (file)
--- a/cts/config_32TDC.vhd
+++ b/cts/config_32TDC.vhd
@@ -40,9 +40,9 @@ package config is
     constant INCLUDE_TDC            : integer  := c_YES;
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;
     constant INCLUDE_STATISTICS     : integer  := c_YES;
-    constant TRIG_GEN_INPUT_NUM     : integer  := 32;
+    constant TRIG_GEN_INPUT_NUM     : integer  := 36 - USE_RJADAPT*12;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 2;
-    constant MONITOR_INPUT_NUM      : integer  := 32;    
+    constant MONITOR_INPUT_NUM      : integer  := 36 - USE_RJADAPT*12;    
 
     
     constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5

diff --git a/cts/config_8SFP_KEL.vhd b/cts/config_8SFP_KEL.vhd
index 3cc8b49fded84a565acde65f5b397c0d75548e92..8a1294cd4c35f7d1f381572f7a6b6a8fd0ea3eb2 100644 (file)
--- a/cts/config_8SFP_KEL.vhd
+++ b/cts/config_8SFP_KEL.vhd
@@ -40,9 +40,9 @@ package config is
     constant INCLUDE_TDC            : integer  := c_NO;
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;
     constant INCLUDE_STATISTICS     : integer  := c_YES;
-    constant TRIG_GEN_INPUT_NUM     : integer  := 32;
+    constant TRIG_GEN_INPUT_NUM     : integer  := 36 - USE_RJADAPT*12;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 2;
-    constant MONITOR_INPUT_NUM      : integer  := 32;    
+    constant MONITOR_INPUT_NUM      : integer  := 36 - USE_RJADAPT*12;    
 
     
     constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5

diff --git a/cts/config_8SFP_RJAdapter.vhd b/cts/config_8SFP_RJAdapter.vhd
index 7a2826a78827993ef4baf612cda87433b3462c34..8c4b9bb0ce5e42249f6fa9c500d0b323ecc3e6d8 100644 (file)
--- a/cts/config_8SFP_RJAdapter.vhd
+++ b/cts/config_8SFP_RJAdapter.vhd
@@ -40,9 +40,9 @@ package config is
     constant INCLUDE_TDC            : integer  := c_NO;
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;
     constant INCLUDE_STATISTICS     : integer  := c_YES;
-    constant TRIG_GEN_INPUT_NUM     : integer  := 20;
+    constant TRIG_GEN_INPUT_NUM     : integer  := 36 - USE_RJADAPT*12;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 2;
-    constant MONITOR_INPUT_NUM      : integer  := 20;    
+    constant MONITOR_INPUT_NUM      : integer  := 36 - USE_RJADAPT*12;    
 
     
     constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5

diff --git a/cts/config_compile_frankfurt.pl b/cts/config_compile_frankfurt.pl
index 6d05f8c3795cf344217c5da3c59ac141b76a6b5b..f2124c601263fdeeb8d8f5d1a321d65b8445de99 100644 (file)
--- a/cts/config_compile_frankfurt.pl
+++ b/cts/config_compile_frankfurt.pl
@@ -1,20 +1,20 @@
 TOPNAME                      => "trb3sc_cts",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/O-2018.09-SP1',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.11_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/P-2019.09-SP1',
 #synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodes_cts_frankfurt.txt',
 
 
-pinout_file                  => 'trb3sc_hub_ctsrj',     #with RJ adapter for I/O
-# pinout_file                  => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors
+#pinout_file                  => 'trb3sc_hub_ctsrj',     #with RJ adapter for I/O
+pinout_file                  => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors
 
 
 #Include only necessary lpf files
-include_TDC                  => 0,
+include_TDC                  => 1,
 include_GBE                  => 1,
 
 #Report settings

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 2165cd9426ff715f5bbbf2674cca1b8afea28ae0..9c49e5d8372fcebf04eaeb871619fee0d4866508 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -716,8 +716,8 @@ end generate;
         EXTERNAL_TRIGGER_ID => ETM_ID,  -- fill in trigger logic enumeration id of external trigger logic
         PLATTFORM => 1+USE_RJADAPT, --TRB3sc+KEL+RJ45
         OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,
-        ADDON_GROUPS      => 3,
-        ADDON_GROUP_UPPER => (2,32-USE_RJADAPT*12,2, others => 0)
+        ADDON_GROUPS      => 1,
+        ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3, others => 0)
         )
       port map (
         CLK   => clk_sys,
@@ -931,7 +931,7 @@ end generate;
       DEBUG_OUT  => open
       );      
 
-monitor_inputs_i <= INP;
+monitor_inputs_i <= cts_addon_triggers_in; --INP;
       
 gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate
   do_reboot_i <= common_ctrl_reg(15);
@@ -1010,37 +1010,37 @@ end generate;
 --                         not  (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9))    when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
 --                              '1';
 
--- -------------------------------------------------------------------------------
--- -- TDC
--- -------------------------------------------------------------------------------
---   THE_TDC : entity work.TDC_record
---     generic map (
---       CHANNEL_NUMBER => NUM_TDC_CHANNELS,  -- Number of TDC channels per module
---       STATUS_REG_NR  => 21,             -- Number of status regs
---       DEBUG          => c_YES,
---       SIMULATION     => c_NO)
---     port map (
---       RESET              => reset_i,
---       CLK_TDC            => clk_full_osc,
---       CLK_READOUT        => clk_sys,    -- Clock for the readout
---       REFERENCE_TIME     => cts_trigger_out,  -- Reference time input
---       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
---       HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
---       -- Trigger signals from handler
---       BUSRDO_RX          => cts_rdo_rx,
---       BUSRDO_TX          => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
---       -- Slow control bus
---       BUS_RX             => bustdc_rx,
---       BUS_TX             => bustdc_tx,
---       -- Dubug signals
---       INFO_IN            => timer,
---       LOGIC_ANALYSER_OUT => open
---       );
--- 
---   -- For single edge measurements
---   gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
---     hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-1 downto 1);
---   end generate;
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : entity work.TDC_record
+   generic map (
+     CHANNEL_NUMBER => NUM_TDC_CHANNELS,  -- Number of TDC channels per module
+     STATUS_REG_NR  => 21,             -- Number of status regs
+     DEBUG          => c_YES,
+     SIMULATION     => c_NO)
+   port map (
+     RESET              => reset_i,
+     CLK_TDC            => clk_full_osc,
+     CLK_READOUT        => clk_sys,    -- Clock for the readout
+     REFERENCE_TIME     => cts_trigger_out,  -- Reference time input
+     HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
+     HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
+     -- Trigger signals from handler
+     BUSRDO_RX          => cts_rdo_rx,
+     BUSRDO_TX          => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
+     -- Slow control bus
+     BUS_RX             => bustdc_rx,
+     BUS_TX             => bustdc_tx,
+     -- Dubug signals
+     INFO_IN            => timer,
+     LOGIC_ANALYSER_OUT => open
+     );
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+   hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
+ end generate;
   
 end architecture;
 

diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl
index 8c14c41bb09c6d6befc03173d11ac2c7d482db7d..a12dc1dd3d20bf75c0fac2e86c8cda1531012941 100644 (file)
--- a/tdctemplate/config_compile_frankfurt.pl
+++ b/tdctemplate/config_compile_frankfurt.pl
@@ -4,7 +4,8 @@ lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
 nodelist_file                => '../tdctemplate/nodes_tdctemplate.txt',
-#Include only necessary lpf files
+
+#Include only necessary lpf file
 #pinout_file                  => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME
 #pinout_file                  => 'trb3sc_padiwa', #name of pin-out file, if not equal TOPNAME
 pinout_file                  => 'trb3sc_ada', #name of pin-out file, if not equal TOPNAME