update to trb3sc_pulser, ADC connection

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 981e11dd4d5c683aebe771e602e5fd7320d3b529..277584d88e6360b9af29d41e47bf8f500da71416 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -134,7 +134,7 @@ begin
   busadc_tx.ack     <= '0';
   busadc_tx.data    <= (others => '0');
 
-
+  
 
 ---------------------------------------------------------------------------
 -- SPI
@@ -161,7 +161,13 @@ begin
     SPI_CS_OUT   <= spi_cs;
     SPI_CLK_OUT  <= (others => spi_sck);
     SPI_MOSI_OUT <= (others => spi_sdo);
-    spi_sdi      <= or_all(SPI_MISO_IN and not spi_cs);
+    spi_sdi      <= (ADC_MISO and not spi_cs(7)) or or_all(SPI_MISO_IN and not spi_cs and x"ff7f");
+    
+    ADC_CLK <= not spi_sck;
+    ADC_CS  <= spi_cs(7);
+    ADC_MOSI <= spi_sdo;
+    
+    
   end generate;
   busspi_tx.unknown <= '0';
 

diff --git a/pulser/trb3sc_pulser.lpf b/pulser/trb3sc_pulser.lpf
index 351506731d79a143c11f8682fcb99050747c9f66..73650b3e4e41a741e1a6c9208e663501c759a3e3 100644 (file)
--- a/pulser/trb3sc_pulser.lpf
+++ b/pulser/trb3sc_pulser.lpf
@@ -1,8 +1,8 @@
 
 # PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
 # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
-PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
 
 MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_right 20 ns;
 MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_left  20 ns;

diff --git a/pulser/trb3sc_pulser.prj b/pulser/trb3sc_pulser.prj
index b88f67e9f61b5d4e28a840c8d3f1895711bcefb5..a165503e0a9bd493f9a173038287d906f0a0c5ed 100644 (file)
--- a/pulser/trb3sc_pulser.prj
+++ b/pulser/trb3sc_pulser.prj
@@ -98,7 +98,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
-
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd"
 
 #Flash & Reload, Tools
 add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"

diff --git a/pulser/trb3sc_pulser.vhd b/pulser/trb3sc_pulser.vhd
index 0dbbe0fe9d443ecf6e43b0f1d2e4de888353a9c6..59e54e77cde59cb064f6e423cd4bcfa6d73085e6 100644 (file)
--- a/pulser/trb3sc_pulser.vhd
+++ b/pulser/trb3sc_pulser.vhd
@@ -400,6 +400,7 @@ THE_PULSER : entity work.pulser
   HDR_IO(6)           <= spi_cs(8);
   HDR_IO(10 downto 7) <= (others => '0');
 
+
   RJ_IO               <= "0000";
 
   
@@ -434,7 +435,7 @@ THE_PULSER : entity work.pulser
   led(1) <= time_counter(20);
   
   
---   TEST_LINE <= med_stat_debug(15 downto 0);
+TEST_LINE <= med_stat_debug(15 downto 0);
   
 end architecture;