corrected clock name for timing constraints

diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf
index 2006ebdba4a24feaed63d0b6a6c6e39b01bc63f6..e02c3446d1f83baed3919425974da1b02f93b700 100644 (file)
--- a/base/trb3_periph_ada.lpf
+++ b/base/trb3_periph_ada.lpf
@@ -94,8 +94,8 @@ BLOCK RD_DURING_WR_PATHS ;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
   FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
-MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ;
 
 LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;