slightly changed hardware information register

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index f4f99b520d172dd113e7566b4232ef7a2c5cd3a3..e24d3d889d74858fa7a40a551cb80544cd26a5df 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -90,11 +90,13 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
   \item[6XXX]  use with Nxyter
   \item[7XXX]  use with 32PinAddOn
   \item[8XXX]  uses RX clock as main internal clock
-  \item[X0nX]  contains $2^n$ TDC channels, single edge
-  \item[X1nX]  contains $2^n$ TDC channels, double edge
+  \item[X0nX]  contains $2^n$ TDC channels, single edge, n<8
+  \item[X1nX]  contains $2^n$ TDC channels, double edge, n<8
   \item[X2XX]  contains a network hub
   \item[X4XX]  SPI interface on AddOn connector
   \item[X8XX]  Double edge TDC realized with two single edge channels
+  \item[XX8X]  Non-TDC (because of bad choice of encoding)
+  \item[XX9X]  for MVD converter board 2013
 \end{description*}
 \end{description*}