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\abstract{The RICH detectors of the existing HADES spectrometer and the CBM experiment (to be built at FAIR) will use 64 channel Multi-Anode PMTs.
We designed a complete set of digitizing electronics, consisting of analog and digital frontend modules, power supply and data concentrator cards plugged into a backplane carrying 3x2 MAPMTs on the front side, and all readout modules on the backside.
-These contain all necessary supply electronics, preamplifiers and FPGA-based TDC as well as the digital data and trigger handling logic and an optical transceiver. We are going to present the electronics along with performance test results.}
+These contain all necessary supply electronics, preamplifiers and FPGA-based TDC as well as the digital data and trigger handling logic and an optical transceiver. We present the electronics along with performance test results.}
\flushbottom
\section{Introduction}
-The two heavy ion spectrometers (HADES and CBM) at the GSI Helmholtz Center for Heavy Ion Research (Darmstadt, Germany) and the FAIR accelerator contain a Ring Imaging Cherenkov (RICH)
-detector for particle identification. The existing RICH at the HADES experiment is in operation since the year 2000. Originally, it was built using a CsI photo cathode plane for photon detection. At the moment it is being upgraded with a new MAPMT readout plane consisting of 428 64-channel PMTs (Hamamatsu H12700). Here, the sensitive area of about $1.3~\rm{m}^2$ will be covered with 28,000 inidividual PMT cells.
+The two heavy ion spectrometers (HADES\cite{hades-web} and CBM\cite{cbm-web}) at the GSI Helmholtz Center for Heavy Ion Research (Darmstadt, Germany) and the FAIR accelerator contain a Ring Imaging Cherenkov (RICH)
+detector for particle identification. The existing RICH at the HADES experiment is in operation since the year 2000. Originally, it was built using a CsI photo cathode plane for photon detection. At the moment it is being upgraded with a new MA-PMT readout plane consisting of 428 64-channel PMTs (Hamamatsu H12700). Here, the sensitive area of about $1.3~\rm{m}^2$ will be covered with 28,000 individual PMT cells.
The RICH detector for the CBM experiment will follow the same design, albeit with a larger read-out plane of about twice the size and an even larger sensitive volume. This detector is going to use identical electronics to the HADES setup, with modifications to the read-out system.
-As a third project, the PANDA experiment, to be built at FAIR during the next years, comprises a DIRC as one of its central parts that is planned to use very similar electronics as well.
+As a third project, the PANDA experiment, to be built at FAIR during the next years, comprises a DIRC as one of its central parts that is planned to use identical electronics as well. The only component to change is the backplane to cope with the different detector geometry.
\section{The Components}
\begin{figure}[htbp]
The central part of the system is formed by an FPGA. The FPGA does not only do time-to-digital conversion (described below), but also contains the signal discriminator, threshold generation and the complete DAQ network stack.
-Discrimination of input signals is realized in the devices LVDS receivers: One input is connected to the amplified signal, the other is supplied with an adjustable threshold voltage. The thresholds are generated by the FPGA using a 16 Bit delta-sigma DAC for each channel. Time measurement is accomplished by a tapped delay line TDC, capable of an accuracy of down to 10~ps (see below).
+Discrimination of input signals is realized in the devices LVDS receivers: One input is connected to the amplified signal, the other is supplied with an adjustable threshold voltage. The thresholds are generated by the FPGA using a 16 Bit delta-sigma DAC for each channel. Time measurement is accomplished by a tapped delay line TDC, capable of an precision of down to 10~ps (see below).
In the triggered read-out architecture of HADES, data is stored in internal buffers until a read-out request is received. A trigger window can be applied to recorded data before it is sent out over a 2 GBit/s link over the backplane. For data communication, the TrbNet\cite{trbnet} protocol is employed. This protocol has been developed for the full data acquisition system of the HADES experiment and is able to transport trigger information, read-out data and slow-control simultaneously over the same serial link.
\subsubsection{Analog Stage}
- \begin{figure}[htbp]
+ \begin{figure}
\centering % \begin{center}/\end{center} takes some additional vertical space
\includegraphics[width=.7\textwidth]{figures/analog.png}
\caption{\label{fig:analog} The schematics of one channel of the analog stage of the DiRich board.}
\end{figure}
- \begin{figure}[htbp]
+ \begin{figure}
\centering % \begin{center}/\end{center} takes some additional vertical space
\includegraphics[width=.5\textwidth]{figures/pulses.png}
\caption{\label{fig:pulses} Examples of input (top) and output (bottom) signals.}
\end{figure}
-The typical input signals from the PMTs has a length of about 2~ns and an amplitude between 5 and 40~mV. Before this signal can be fed into a fast discriminator, it has to be amplified by a factor of 20. The discrete amplification stage is built around a wideband transistor (BFU760F) as a common emitter amplifier. The typical resistor at the collector has been replaced by an inductor in this circuit for various reasons. First, it allows to use a low operating voltage of only 1.1~V while keeping the static current in the transistor low. Additionally it helps in shaping the output signal as a high-pass filter. The rise time is preserved, but an undershoot is added at the end of the signal to help in returning to the baseline. In the current configuration, the amplifier takes only 50~ns to return to the baseline, avoiding pile-up and wrong time-over-threshold measurements for close signals. Lastly, the undershoots generates a fast crossing of the threshold resulting in a better timing measurement. The amplification stage has been measured to consume 12mW per channel.
+The typical input signals from the PMTs has a length of about 2~ns and an amplitude between 5 and 40~mV. Before this signal can be fed into a fast discriminator, it has to be amplified by a factor of 20. Figure \ref{fig:pulses} shows two different input signals (upper pane) and the corresponding output signals (lower pane).
+
+The discrete amplification stage is built around a wide-band transistor (BFU760F) as a common emitter amplifier. The typical resistor at the collector has been replaced by an inductor (L77 in figure \ref{fig:analog}) in this circuit for various reasons. First, it allows to use a low operating voltage of only 1.1~V while keeping the static current in the transistor low. Additionally it helps in shaping the output signal as a high-pass filter. The rise time is preserved, but an undershoot is added at the end of the signal to help in returning to the baseline. In the current configuration, the amplifier takes only 50~ns to return to the baseline, avoiding pile-up and wrong time measurements for close signals. Lastly, the undershoot generates a fast crossing of the threshold resulting in a better time-over-threshold measurement. Each channel is galvanically isolated by a small transformer to decouple grounds of the PMT and the amplifier.
+
+The amplification stage has been measured to consume 12~mW per channel. The typical amplification varies between 24 for small signals to 15 for the largest signals of about 40~mV amplitude. This is expected as the total charge the inductor can deliver for each pulse is limited. As the amplitude of the resulting pulse is not measured, there is no negative influence on the accuracy of acquired data.
-The amplified signal with a very fast rise time is then fed into an input of an LVDS-receiver of the FPGA (LFE5UM-85F-8BG381C). The individual threshold
-voltage for the discriminator is produced by a delta-sigma DAC output of the FPGA with a simple, two-stage low pass filter connected to the output pin. This DAC reaches a resolution of 38uV and shows no measureable ripple. The switiching of the 32 channels is timed such that no two channels switch at the same time and the switiching of each channel is limited to few MHz to keep the generated noise level as low as possible.
+The amplified signal with a fast rise time of less than 1~ns is then fed into an input of an LVDS-receiver of the FPGA (LFE5UM-85F-8BG381C). The individual threshold voltage for the discriminator is produced by a delta-sigma DAC output of the FPGA with a simple, two-stage low pass filter connected to the output pin. This DAC reaches a resolution of 38~$\upmu \rm{V}$ and shows no measurable ripple. The switching of the 32 channels is timed such that no two channels switch at the same time and the switching of each channel is limited to few MHz to keep the generated noise level as low as possible.
\subsubsection{Time Measurement}
\includegraphics[width=.4\textwidth]{../figures/dirich/dirich_concentrator.jpg}
\caption{\label{fig:aux} The two auxillary boards: Power supplies (left) and data concentrator (right)}
\end{figure}
-The front-end module is complemented by two auxillary boards. The power board houses switiching and linear voltage regulators to provide all necessary supply voltages. Additionally, trigger (reference time) and clock signals are distributed to all front-ends from this board. Two ADC allow for detailed monitoring of all voltages and currents. The board currently forsees two possible powering schemes: A 24~V input and DC-DC converters provide the most simple external supply. A second option is the direct input of externally regulated low voltages (1.1~V - 3.3~V). In this case, only linear regulators are active and the electromagnetic noise in the system is reduced. Which of the two options will be used in the final system is currently under investigation.
+The front-end module is complemented by two auxillary boards. The power board houses switiching and linear voltage regulators to provide all necessary supply voltages. Additionally, trigger (reference time) and clock signals are distributed to all front-ends from this board. Two ADC allow for detailed monitoring of all voltages and currents. The board currently forsees two possible powering schemes: A 24~V (8 -- 36~V) input and DC-DC converters provide the most simple external supply. A second option is the direct input of externally regulated low voltages (1.1~V -- 3.3~V). In this case, only linear regulators are active and the electromagnetic noise in the system is reduced. Which of the two options will be used in the final system is currently under investigation.
-The second board is the data concentrator. Built around a Lattice ECP3 FPGA, it serves as hub to connect all front-end modules to the central DAQ system. In the HADES configuration, this board runs a total of 13 links at 2 GBit/s using the TrbNet protocol. The reference time for all TDC is supplied by an additional LVDS signal generated by the central trigger system (CTS). In the CBM experiment, data acquisition will not be triggered, but free-streaming. This can be achieved by altering the data processing scheme inside the network and endpoints while keeping the underlying network protocol the same. In this setup, also the clock distribution and fixed-latency synchronization messages will be embedded into the optical data stream to reduce the number of electrical connections inside the detector.
+The second board is the data concentrator. Built around a Lattice ECP3 FPGA, it serves as hub to connect all front-end modules to the central DAQ system. In the HADES configuration, this board runs a total of 13 links at 2 GBit/s using the TrbNet protocol. The reference time for all TDC is supplied by an additional LVDS signal generated by the central trigger system (CTS). A trigger request can be generated by the board as well: Every front-end can generate a signal based on a configurable combination of input signals or multiplicities and forward this via the concentrator board to the CTS, which in turn triggers the read-out of the full detector.
+
+In the CBM experiment, data acquisition will not be triggered, but free-streaming. This can be achieved by altering the data processing scheme inside the network and endpoints while keeping the underlying network protocol the same. In this setup, also the clock distribution and fixed-latency synchronization messages will be embedded into the optical data stream to reduce the number of electrical connections inside the detector.
The 2 GBit/s link of the concentrator board is able to transport the data of up to 40 Mhits/s from each module. As the CBM and PANDA detectors expect hit rates of up to 200 kHz per channel and 60 MHits/s per module in the central parts of the detector, this bandwidth is not sufficient. Here, an upgraded version of the concentrator, using a 4.8 GBit/s optical link will be employed.
\section{Summary}
-
+A complete set of data acquisition electronics for single-photon detectors has been developed. Tests in the lab have been completed successfully, full system tests are on-going.
\acknowledgments
% \bibitem{c}
% Author, \emph{Title},
% Publisher (year).
+\bibitem{hades-web}
+The HADES website,
+\href{https://www-hades.gsi.de/}{https://www-hades.gsi.de/}
+
+\bibitem{cbm-web}
+The CBM website,
+\href{http://www.fair-center.eu/for-users/experiments/cbm.html}{http://www.fair-center.eu/for-users/experiments/cbm.html}
\bibitem{cbmrich}
C. H\"ohne (Ed) et al.,
\emph{Technical Design Report for the CBM Ring Imaging Cherenkov (RICH) Detector},
-GSI-2014-00528, http://repository.gsi.de/record/65526
+\href{http://repository.gsi.de/record/65526}{GSI-2014-00528}
\bibitem{trb-web}
-The TRB3 website, \href{http://trb.gsi.de}{http://trb.gsi.de}.
-
-\bibitem{cbm-web}
-The CBM website,
-\href{http://www.fair-center.eu/for-users/experiments/cbm.html}{http://www.fair-center.eu/for-users/experiments/cbm.html}.
+The TRB3 website, \href{http://trb.gsi.de}{http://trb.gsi.de}
\bibitem{trbnet}
J. Michel et al.,
\emph{The HADES DAQ system: Trigger and readout board network}, IEEE Trans.Nucl.Sci. 58 (2011) 1745-1750
+\bibitem{tdc}
+C. U\u{g}ur et al.,
+\emph{264 Channel TDC Platform Applying 65 Channel High Precision (7.2 ps RMS) FPGA Based TDC},
+\href{http://dx.doi.org/10.1109/NoMeTDC.2013.6658234}{10.1109/NoMeTDC.2013.6658234}
+
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