trb3sc details

diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex
index 622a143a44b7ee023cb32e0a0f17762c0918f15f..e1566ba7f6be0bd1b1880b0f9ebd76476f439bf8 100644 (file)
--- a/trb3/Trb3scBasics.tex
+++ b/trb3/Trb3scBasics.tex
@@ -34,7 +34,7 @@ The native frequency of the board are 240 MHz, logic running at 120 MHz. Neverth
 \end{itemize*}
 
 \subsubsection{Other I/O}
-JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By default, SPI and UART are available:
+HDR\_IO is available for any general purpose I/O. All lines are LVCMOS25. By default, SPI and UART are available:
 \begin{center}
   \begin{tabular}{|l|l|}
   \hline  
@@ -49,15 +49,16 @@ JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By defau
   7 & \\
   8 & \\
   9 & \\
-  10 & 3.3V\\
+  10 & \\
   11 & 3.3V\\
-  12 & GND\\
+  12 & 3.3V\\
   13 & GND\\
+  14 & GND\\
   \hline  
   \end{tabular}
 \end{center}
 
-SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 6 is reserved for JGPIO.
+SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 8 is reserved for HDR\_IO.
 
 
 \subsubsection{Serial Links}