FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ;
REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;
LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
-LOCATE UGROUP "tsmac" REGION "MED0" ;
\ No newline at end of file
+LOCATE UGROUP "tsmac" REGION "MED0" ;
+BLOCK JTAGPATHS ;
+UGROUP "sd_tx_to_pcs"
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
+UGROUP "sd_rx_to_pcs"
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
+ BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
+UGROUP "pcs_tx_to_mac"
+ BLKNAME gen_ethernet_hub_GBE/pcs_tx_en_q
+ BLKNAME gen_ethernet_hub_GBE/pcs_tx_en_qq
+ BLKNAME gen_ethernet_hub_GBE/pcs_tx_er_q
+ BLKNAME gen_ethernet_hub_GBE/pcs_tx_er_qq
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_0
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_1
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_2
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_3
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_4
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_5
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_6
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_7
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_0
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_1
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_2
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_3
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_4
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_5
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_6
+ BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_7;
+UGROUP "pcs_rx_to_mac"
+ BLKNAME gen_ethernet_hub_GBE/pcs_rx_en_q
+ BLKNAME gen_ethernet_hub_GBE/pcs_rx_en_qq
+ BLKNAME gen_ethernet_hub_GBE/pcs_rx_er_q
+ BLKNAME gen_ethernet_hub_GBE/pcs_rx_er_qq
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_0
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_1
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_2
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_3
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_4
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_5
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_6
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_7
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_0
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_1
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_2
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_3
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_4
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_5
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_6
+ BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_7;
+USE PRIMARY NET "CLK_GPLL_RIGHT_c" ;
+FREQUENCY NET "gen_ethernet_hub_GBE/serdes_rx_clk_c" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ;\r
+FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ;\r
+FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ;\r
+FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ;\r
+\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rx_en_q" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rx_er_q" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_1" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_2" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_3" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_4" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_5" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_6" 1.5 ns;\r
+MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_7" 1.5 ns;\r
+\r
+DEFINE PORT GROUP "RX_GRP" "gen_ethernet_hub_GBE/pcs_rx_en_q"\r
+ "gen_ethernet_hub_GBE/pcs_rx_er_q"\r
+ "gen_ethernet_hub_GBE/pcs_rxd_q_*";\r
+INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "gen_ethernet_hub_GBE/serdes_rx_clk_c" ; \r
+\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rx_en_q" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rx_er_q" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_1" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_2" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_3" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_4" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_5" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_6" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_7" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 100;\r
+PRIORITIZE NET "gen_ethernet_hub_GBE/serdes_rx_clk_c" 80;\r
+\r
+BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;
+BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;\r
+
+MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ;
+MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ;
+MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ;
+MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;
+MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;
+MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;
+MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
+
+BLOCK INTERCLOCKDOMAIN PATHS ;
\ No newline at end of file