ring buffer size register address is changed

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index 0ce0c4968c091aca32457d42157c2167012c4727..e5a555a55d253ae8d8409c1b3a55c09a687f40e0 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -50,12 +50,14 @@ the control registers are given in Table \ref{tab:tdcControlReg}.
       0xc803   & Channel enable 2      & 31-0  & Enable signals for the channels 33-64.\\
       
       \hline
-      0xc804   & Data transfer limit   & 7-0   & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout. \textbf{ATTENTION! This conrol is implemented only for debug readons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\
+      0xc804   & Data transfer limit   & 7-0   & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout.\\
+               & Removed after version 2.1.1   &       & \textbf{ATTENTION! This conrol is implemented only for debug readons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\
                &                       & 31-8  & reserved.\\
       
       \hline
-      0xc805   & TDC channel           & 6-0   & Defines the size of the channel buffer size (from tdc\_v2.1).\\
-               & buffer limit          &       & Possible values 0-126\\
+      0xc804   & TDC channel           & 6-0   & Defines the size of the channel buffer size (from tdc\_v2.1).\\
+               & buffer limit          &       & Replaced with the ``Data limit'' register after tdc\_v2.1.1\\
+               &                       &       & Possible values 0-126\\
                &                       & 31-7  & reserved.\\
       \hline