signal rx_error : std_logic;
signal rst_n : std_logic;
+signal rst : std_logic;
signal rx_serdes_rst : std_logic;
signal tx_serdes_rst : std_logic;
signal tx_pcs_rst : std_logic;
signal rx_pcs_rst : std_logic;
signal rst_qd : std_logic;
signal serdes_rst_qd : std_logic;
+signal sd_los_i : std_logic;
signal rx_los_low : std_logic;
signal lsm_status : std_logic;
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-rst_n <= not CLEAR;
+rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
);
+ tx_serdes_rst <= '0'; --no function
+ serdes_rst_qd <= '0'; --included in rst_qd
+
-------------------------------------------------
-- Reset FSM & Link states
-------------------------------------------------
port map(
CLK_200 => clk_200_i,
CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
+ RESET_IN => rst,
TX_DATA_IN => MED_DATA_IN,
TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
port map(
CLK_200 => clk_200_i,
CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
+ RESET_IN => rst,
RX_DATA_OUT => MED_DATA_OUT,
RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
-- Generate LED signals
-------------------------------------------------
led_ok <= rx_allow and tx_allow when rising_edge(SYSCLK);
-led_rx <= (MED_DATAREADY_OUT or led_rx or last_led_rx) and not timer(20) when rising_edge(SYSCLK);
-led_tx <= (MED_DATAREADY_IN or led_tx or last_led_tx) and not timer(20) when rising_edge(SYSCLK);
-led_dlm <= (led_dlm or rx_dlm_i or last_led_dlm) and not timer(20) when rising_edge(clk_200_i);
+led_rx <= (MED_DATAREADY_OUT or led_rx) and not timer(20) when rising_edge(SYSCLK);
+led_tx <= (MED_DATAREADY_IN or led_tx or sd_los_i) and not timer(20) when rising_edge(SYSCLK);
+led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(SYSCLK);
ROC_TIMER : process begin
wait until rising_edge(SYSCLK);
timer <= timer + 1 ;
if timer(20) = '1' then
timer <= (others => '0');
- last_led_rx <= led_rx;
+ last_led_rx <= led_rx ;
last_led_tx <= led_tx;
last_led_dlm <= led_dlm;
end if;
-- Debug Registers
-------------------------------------------------
debug_reg(3 downto 0) <= rx_fsm_state;
-debug_reg(4) <= rx_k;
-debug_reg(5) <= rx_error;
+debug_reg(4) <= CLEAR;
+debug_reg(5) <= tx_allow_q;
debug_reg(6) <= rx_los_low;
debug_reg(7) <= rx_cdr_lol;
-debug_reg(8) <= tx_k;
+debug_reg(8) <= RESET;
debug_reg(9) <= tx_pll_lol;
-debug_reg(10) <= lsm_status;
-debug_reg(11) <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
+debug_reg(10) <= rx_allow_q;
+debug_reg(11) <= CTRL_OP(15);
+debug_reg(12) <= make_link_reset_i;
+debug_reg(13) <= send_link_reset_i;
+debug_reg(14) <= rst_qd;
+debug_reg(15) <= rx_pcs_rst;
-- debug_reg(31 downto 24) <= tx_data;
debug_reg(16) <= '0';
STAT_DEBUG <= debug_reg;
internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
-
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);
STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
-STAT_OP(14) <= '0';
+STAT_OP(14) <= '0' when rising_edge(SYSCLK); --sd_los_i
STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12) <= led_dlm;
-STAT_OP(11) <= led_tx;
-STAT_OP(10) <= led_rx;
+STAT_OP(12) <= led_dlm or last_led_dlm;
+STAT_OP(11) <= led_tx or last_led_tx;
+STAT_OP(10) <= led_rx or last_led_rx;
STAT_OP(9) <= led_ok;
STAT_OP(8 downto 4) <= (others => '0');
STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
+--STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else ("01" & tx_pll_lol & rx_cdr_lol);
end architecture;
signal ns: statetype; -- next state of lsm
signal tx_pll_lol_qd_s_int : std_logic;
-signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
+signal tx_pcs_rst_ch_c_int : std_logic;
signal RST_QD_C_int : std_logic;
signal reset_timer1: std_logic;
else if rising_edge(TX_REFCLK) then
cs <= ns;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
+ tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int;
RST_QD_C <= RST_QD_C_int;
end if;
end if;
-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-process (TX_REFCLK, reset_timer1)
+process (TX_REFCLK)
begin
if rising_edge(TX_REFCLK) then
if reset_timer1 = '1' then
when QUAD_RESET =>
STATE_OUT <= x"1";
- tx_pcs_rst_ch_c_int <= "1111";
+ tx_pcs_rst_ch_c_int <= '1';
RST_QD_C_int <= '1';
reset_timer1 <= '1';
ns <= WAIT_FOR_TIMER1;
when WAIT_FOR_TIMER1 =>
STATE_OUT <= x"2";
- tx_pcs_rst_ch_c_int <= "1111";
+ tx_pcs_rst_ch_c_int <= '1';
RST_QD_C_int <= '1';
if TIMER1 = '1' then
ns <= CHECK_PLOL;
when CHECK_PLOL =>
STATE_OUT <= x"3";
- tx_pcs_rst_ch_c_int <= "1111";
+ tx_pcs_rst_ch_c_int <= '1';
RST_QD_C_int <= '0';
reset_timer2 <= '1';
ns <= WAIT_FOR_TIMER2;
when WAIT_FOR_TIMER2 =>
STATE_OUT <= x"4";
- tx_pcs_rst_ch_c_int <= "1111";
+ tx_pcs_rst_ch_c_int <= '1';
RST_QD_C_int <= '0';
if TIMER2 = '1' then
if tx_pll_lol_qd_s_int = '1' then
when NORMAL =>
STATE_OUT <= x"5";
- tx_pcs_rst_ch_c_int <= "0000";
+ tx_pcs_rst_ch_c_int <= '0';
RST_QD_C_int <= '0';
if tx_pll_lol_qd_s_int = '1' then
ns <= QUAD_RESET;
jspc29 / trbnet.git / commitdiff