]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
*** empty log message ***
authorhadaq <hadaq>
Wed, 4 Jul 2012 09:31:33 +0000 (09:31 +0000)
committerhadaq <hadaq>
Wed, 4 Jul 2012 09:31:33 +0000 (09:31 +0000)
12 files changed:
base/cbmrich.lpf
base/trb3_periph_mainz.lpf
cbmrich/cbmrich.prj
cbmrich/cbmrich.vhd
cbmrich/cbmrich_constraints.lpf
tdc_releases/tdc_v0.2/source/trb3_periph.vhd
tdc_releases/tdc_v0.3/Channel.vhd
tdc_releases/tdc_v0.3/Reference_channel.vhd
tdc_releases/tdc_v0.3/TDC.vhd
tdc_releases/tdc_v0.3/tdc_constraints.lpf [deleted file]
tdc_releases/tdc_v0.3/trb3_periph.vhd [deleted file]
tdc_test/trb3_periph.vhd

index 983455477730bc12afa4eb017f102133f8c112e0..5ccbffe2a86ad02456b5c985b9daafd27d31ba38 100644 (file)
@@ -184,7 +184,11 @@ IOBUF GROUP "SPARE_LINE_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
 LOCATE COMP  "LVDS_1"   SITE "J23";
 LOCATE COMP  "LVDS_2"   SITE "G26";
 DEFINE PORT GROUP "LVDS_group" "LVDS*" ;
+<<<<<<< cbmrich.lpf
+IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
+=======
 IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25;
+>>>>>>> 1.2
 
 LOCATE COMP  "TEMPSENS"    SITE "K23";
 IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
index 07fb2ec153b13426aaf733a891ab06f30d38ee80..7da33936e9c8ddfc9f15fb31b6db6698a2bbc39a 100644 (file)
@@ -7,10 +7,10 @@ BLOCK RD_DURING_WR_PATHS ;
 # Basic Settings
 #################################################################
 
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
 #################################################################
 # Clock I/O
@@ -230,13 +230,13 @@ IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
 
 LOCATE COMP  "DAC_SDI"   SITE "G6";   #"DQUL_7"   DQSUL0_C  #88   #IN_L_SDIb
 LOCATE COMP  "DAC_SCK"   SITE "E4";   #"DQUL_3"   DQUL0_3   #80   #OUT_L_SDOb
-LOCATE COMP  "DAC_CS_1"  SITE "C3";   #"DQUL_4"   DQUL0_4   #82   #OUT_L_SCK
-LOCATE COMP  "DAC_CS_2"  SITE "D3";   #"DQUL_5"   DQUL0_5   #84   #OUT_L_SCKb
-LOCATE COMP  "DAC_CS_3"  SITE "H6";   #"DQUL_10"  DQUL0_8   #94   #OUT_L_CS
-LOCATE COMP  "DAC_CS_4"  SITE "J6";   #"DQUL_11"  DQUL0_9   #96   #OUT_L_CSb
+LOCATE COMP  "DAC_CS_0"  SITE "C3";   #"DQUL_4"   DQUL0_4   #82   #OUT_L_SCK
+LOCATE COMP  "DAC_CS_1"  SITE "D3";   #"DQUL_5"   DQUL0_5   #84   #OUT_L_SCKb
+LOCATE COMP  "DAC_CS_2"  SITE "H6";   #"DQUL_10"  DQUL0_8   #94   #OUT_L_CS
+LOCATE COMP  "DAC_CS_3"  SITE "J6";   #"DQUL_11"  DQUL0_9   #96   #OUT_L_CSb
 
 DEFINE PORT GROUP "DAC_group" "DAC*" ;
-IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
 
 
 #################################################################
index d4686f92858315f02545cb896352d4717082d0d1..31f2bced64c27d6b20f683f44e24d56e4a42eeb6 100644 (file)
@@ -144,7 +144,6 @@ add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Adder_304.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/bit_sync.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Channel.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/FIFO_32x512_OutReg.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/FIFO_32x32_OutReg.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Reference_channel.vhd"
 add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_encoder_3.vhd"
index bb07d70ff5e5cf28f10e2d2c795cda6bab8a7179..393106be3e4015ee72a80ef729fc551dcb6f1083 100644 (file)
@@ -216,12 +216,12 @@ architecture cbmrich_arch of cbmrich is
   signal time_counter : unsigned(31 downto 0);
 
   --TDC
-  signal hit_in_i : std_logic_vector(63 downto 1);
+  signal hit_in_i : std_logic_vector(64 downto 1);
 
   --TDC component
   component TDC
     generic (
-      CHANNEL_NUMBER : integer range 0 to 64;
+      CHANNEL_NUMBER : integer range 1 to 65;
       STATUS_REG_NR  : integer range 0 to 6;
       CONTROL_REG_NR : integer range 0 to 6);
     port (
@@ -632,7 +632,7 @@ timing_trg_received_i <= SPARE_LINE(0);
 -------------------------------------------------------------------------------
     THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER => 32,             -- Number of TDC channels
+      CHANNEL_NUMBER => 65,             -- Number of TDC channels
       STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
       CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
     port map (
@@ -640,7 +640,7 @@ timing_trg_received_i <= SPARE_LINE(0);
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
-      HIT_IN                => hit_in_i(31 downto 1),  -- Channel start signals
+      HIT_IN                => hit_in_i(64 downto 1),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --
@@ -671,7 +671,7 @@ timing_trg_received_i <= SPARE_LINE(0);
       CONTROL_REG_IN        => ctrl_reg);
 
 
-  hit_in_i(63 downto 1)   <= INPUT(63 downto 1);
+  hit_in_i  <= INPUT;
   
   -- to detect rising & falling edges
   --hit_in_i(1) <= not timing_trg_received_i;
index 6da98d001154f6b94aac1e6d5a9332ce4d306721..5a6b38359856279d26b55a13fcb6737e1f38989c 100644 (file)
@@ -702,13 +702,16 @@ UGROUP "E&F_31" # BBOX 4 5
 LOCATE UGROUP "E&F_31" REGION "Region_E&F_12" ;
 
 ##############################################################################
-
+##                         Unimportant Data Lines                           ##
+##############################################################################
 #MULTICYCLE TO PORT "TEST_LINE_*" 2.000000 X ;
-
 MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/lost_hit_cntr_*" 3.000000 X ;
+MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/hit_detect_cntr_*" 3.000000 X ;
+MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/encoder_start_cntr_*" 3.000000 X ;
+MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/fifo_wr_cntr_*" 3.000000 X ;
+
 MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 3.000000 X ;
 
 
 MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.700000 nS DATAPATH_ONLY ;
 MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-
index 9967e2becd72721bed8e1d9d55a7ef6ca158916a..bb6a3dee387971f1626e797989c7330d4f670b9d 100644 (file)
@@ -589,7 +589,7 @@ begin
       RESET                 => reset_i,
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
-      REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
+      REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
       HIT_IN                => hit_in_i(31 downto 1),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
@@ -622,7 +622,7 @@ begin
 
 
   hit_in_i(1) <= not timing_trg_received_i;
-  
+
   Gen_Hit_In_Signals : for i in 1 to 15 generate
     hit_in_i(i*2)   <= INP(i-1);
     hit_in_i(i*2+1) <= not INP(i-1);
index adf833d26806dfe0c1959bec9a3421ce3532c485..4de1a17af2b190e373d9a6b9b4dad7ffb931e99e 100644 (file)
@@ -197,7 +197,7 @@ begin
       DataB  => data_b_i,
       ClkEn  => '1', --ff_array_en_i,
       Result => result_i);
-  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
+  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000F" & x"7FFFFFF";
   data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
 
   --FF_Array_Enable : process (hit_detect_i, release_delay_line_i)
@@ -337,8 +337,8 @@ begin
   --    Empty   => fifo_empty_i,
   --    Full    => fifo_full_i);
   fifo_data_in_i(31)           <= '1';  -- data marker
-  fifo_data_in_i(30 downto 28) <= "000";           -- reserved bits
-  fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6);  -- channel number
+  fifo_data_in_i(30 downto 29) <= "00";           -- reserved bits
+  fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7);  -- channel number
   fifo_data_in_i(21 downto 12) <= fine_counter_i;  -- fine time from the encoder
   fifo_data_in_i(11)           <= '1';  --edge_type_i;  -- rising '1' or falling '0' edge
   fifo_data_in_i(10 downto 0)  <= hit_time_stamp_i;  -- hit time stamp
index 346ca4e65535484c8e068c7153adeed6fab0e1f2..13cddbabfc54cfb356671f7814887fd558027886 100644 (file)
@@ -185,7 +185,7 @@ begin
       DataB  => data_b_i,
       ClkEn  => '1',                    --ff_array_en_i,
       Result => result_i);
-  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
+  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000FF" & x"7FFFFFF";
   data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
 
   --FF_Array_Enable : process (hit_detect_i, release_delay_line_i)
index cb3c6e8eb70da2970756bc3a892731e7e8388bcb..c4c267c8e2f831750e17217b0e17ba759480f622 100644 (file)
@@ -13,7 +13,7 @@ use IEEE.STD_LOGIC_TEXTIO.all;
 
 entity TDC is
   generic (
-    CHANNEL_NUMBER : integer range 0 to 64;
+    CHANNEL_NUMBER : integer range 1 to 65;
     STATUS_REG_NR  : integer range 0 to 6;
     CONTROL_REG_NR : integer range 0 to 6);
   port (
@@ -83,7 +83,7 @@ architecture TDC of TDC is
 --
   component Channel
     generic (
-      CHANNEL_ID : integer range 1 to 64);
+      CHANNEL_ID : integer range 1 to 65);
     port (
       RESET_WR             : in  std_logic;
       RESET_RD             : in  std_logic;
@@ -202,7 +202,7 @@ architecture TDC of TDC is
 -- Other Signals
   signal fifo_full_i           : std_logic;
   signal fifo_almost_full_i    : std_logic;
-  signal mask_i                : std_logic_vector(CHANNEL_NUMBER downto 0);
+  signal mask_i                : std_logic_vector(71 downto 0);
   signal fifo_nr               : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER;
   signal fifo_nr_next          : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER;
   signal TW_pre                : std_logic_vector(10 downto 0);
@@ -210,7 +210,7 @@ architecture TDC of TDC is
   signal channel_hit_time      : std_logic_vector(10 downto 0);
   signal trg_win_l             : std_logic;
   signal trg_win_r             : std_logic;
-  type   Std_Logic_8_array is array (0 to (CHANNEL_NUMBER/8-1)) of std_logic_vector(3 downto 0);
+  type   Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0);
   signal fifo_nr_hex           : Std_Logic_8_array;
   signal coarse_cnt            : std_logic_vector(10 downto 0);
   signal reset_coarse_cnt      : std_logic;
@@ -316,7 +316,7 @@ begin
 
   -- Channel enable signals
   GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate
-    hit_in_i(i) <= HIT_IN(i) and ch_en_i(i);
+    hit_in_i(i) <= HIT_IN(i) and ch_en_i(i-1);
   end generate GEN_Channel_Enable;
 
   -- Channels
@@ -510,7 +510,7 @@ begin
     end if;
   end process CREAT_MASK;
 
-  GEN : for i in 0 to (CHANNEL_NUMBER/8-1) generate
+  GEN : for i in 0 to 8 generate
     ROM : ROM_FIFO
       port map (
         Address    => mask_i(8*(i+1)-1 downto 8*i),
@@ -528,20 +528,22 @@ begin
         fifo_nr_next <= CHANNEL_NUMBER;
       elsif fifo_nr_hex(0)(3) /= '1' then
         fifo_nr_next <= conv_integer("00000" & fifo_nr_hex(0)(2 downto 0));
-      --elsif fifo_nr_hex(1)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0));
-      --elsif fifo_nr_hex(2)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0));
-      --elsif fifo_nr_hex(3)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0));
-      --elsif fifo_nr_hex(4)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0));
-      --elsif fifo_nr_hex(5)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0));
-      --elsif fifo_nr_hex(6)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0));
-      --elsif fifo_nr_hex(7)(3) /= '1' then
-      --  fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0));
+      elsif fifo_nr_hex(1)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0));
+      elsif fifo_nr_hex(2)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0));
+      elsif fifo_nr_hex(3)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0));
+      elsif fifo_nr_hex(4)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0));
+      elsif fifo_nr_hex(5)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0));
+      elsif fifo_nr_hex(6)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0));
+      elsif fifo_nr_hex(7)(3) /= '1' then
+        fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0));
+      elsif fifo_nr_hex(8)(3) /= '1' then
+        fifo_nr_next <= conv_integer("01000" & fifo_nr_hex(8)(2 downto 0));
       else
         fifo_nr_next <= CHANNEL_NUMBER;
       end if;
@@ -594,7 +596,7 @@ begin
           end if;
           stop_status_i <= '0';
         elsif wr_ch_data_reg = '1' and trigger_win_en = '0' then
-          data_out_reg  <= "1000" & channel_data_reg(fifo_nr)(27 downto 0);
+          data_out_reg  <= channel_data_reg(fifo_nr);
           data_wr_reg   <= '1';
           stop_status_i <= '0';
         elsif wr_status_i = '1' then
@@ -877,23 +879,23 @@ begin
   -- Information bits sent after a status trigger
   -- <= lost_hits_nr_i;                 -- total number of lost hits.
 
-  fifo_full_i <= channel_full_i(31) or channel_full_i(30) or channel_full_i(29) or channel_full_i(28) or
-                 channel_full_i(27) or channel_full_i(26) or channel_full_i(25) or channel_full_i(24) or
-                 channel_full_i(23) or channel_full_i(22) or channel_full_i(21) or channel_full_i(20) or
-                 channel_full_i(19) or channel_full_i(18) or channel_full_i(17) or channel_full_i(16) or
-                 channel_full_i(15) or channel_full_i(14) or channel_full_i(13) or channel_full_i(12) or
-                 channel_full_i(11) or channel_full_i(10) or channel_full_i(9) or channel_full_i(8) or
-                 channel_full_i(7) or channel_full_i(6) or channel_full_i(5) or channel_full_i(4) or
-                 channel_full_i(3) or channel_full_i(2) or channel_full_i(1) or channel_full_i(0);
-
-  fifo_almost_full_i <= channel_almost_full_i(31) or channel_almost_full_i(30) or channel_almost_full_i(29) or channel_almost_full_i(28) or
-                        channel_almost_full_i(27) or channel_almost_full_i(26) or channel_almost_full_i(25) or channel_almost_full_i(24) or
-                        channel_almost_full_i(23) or channel_almost_full_i(22) or channel_almost_full_i(21) or channel_almost_full_i(20) or
-                        channel_almost_full_i(19) or channel_almost_full_i(18) or channel_almost_full_i(17) or channel_almost_full_i(16) or
-                        channel_almost_full_i(15) or channel_almost_full_i(14) or channel_almost_full_i(13) or channel_almost_full_i(12) or
-                        channel_almost_full_i(11) or channel_almost_full_i(10) or channel_almost_full_i(9) or channel_almost_full_i(8) or
-                        channel_almost_full_i(7) or channel_almost_full_i(6) or channel_almost_full_i(5) or channel_almost_full_i(4) or
-                        channel_almost_full_i(3) or channel_almost_full_i(2) or channel_almost_full_i(1) or channel_almost_full_i(0);
+  --fifo_full_i <= channel_full_i(31) or channel_full_i(30) or channel_full_i(29) or channel_full_i(28) or
+  --               channel_full_i(27) or channel_full_i(26) or channel_full_i(25) or channel_full_i(24) or
+  --               channel_full_i(23) or channel_full_i(22) or channel_full_i(21) or channel_full_i(20) or
+  --               channel_full_i(19) or channel_full_i(18) or channel_full_i(17) or channel_full_i(16) or
+  --               channel_full_i(15) or channel_full_i(14) or channel_full_i(13) or channel_full_i(12) or
+  --               channel_full_i(11) or channel_full_i(10) or channel_full_i(9) or channel_full_i(8) or
+  --               channel_full_i(7) or channel_full_i(6) or channel_full_i(5) or channel_full_i(4) or
+  --               channel_full_i(3) or channel_full_i(2) or channel_full_i(1) or channel_full_i(0);
+
+  --fifo_almost_full_i <= channel_almost_full_i(31) or channel_almost_full_i(30) or channel_almost_full_i(29) or channel_almost_full_i(28) or
+  --                      channel_almost_full_i(27) or channel_almost_full_i(26) or channel_almost_full_i(25) or channel_almost_full_i(24) or
+  --                      channel_almost_full_i(23) or channel_almost_full_i(22) or channel_almost_full_i(21) or channel_almost_full_i(20) or
+  --                      channel_almost_full_i(19) or channel_almost_full_i(18) or channel_almost_full_i(17) or channel_almost_full_i(16) or
+  --                      channel_almost_full_i(15) or channel_almost_full_i(14) or channel_almost_full_i(13) or channel_almost_full_i(12) or
+  --                      channel_almost_full_i(11) or channel_almost_full_i(10) or channel_almost_full_i(9) or channel_almost_full_i(8) or
+  --                      channel_almost_full_i(7) or channel_almost_full_i(6) or channel_almost_full_i(5) or channel_almost_full_i(4) or
+  --                      channel_almost_full_i(3) or channel_almost_full_i(2) or channel_almost_full_i(1) or channel_almost_full_i(0);
 
 -------------------------------------------------------------------------------
 -- Debug and statistics words
@@ -1135,14 +1137,9 @@ begin
 --
 --  TDC_DEBUG(31 downto 28)          <= 
 
--- Register 0x81
-  --TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 0);
-
--- Register 0x82
-  --Empty_Channels : if CHANNEL_NUMBER >= 33 generate
-  --  TDC_DEBUG(2*32+CHANNEL_NUMBER-33 downto 2*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 32);
-  --end generate Empty_Channels;
-
+  -- Register 0x81 & 0x82
+  TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 0);
+  
 -- Register 0x83
   TDC_DEBUG(3*32+31 downto 3*32+0) <= "00000" & TRG_WIN_POST & "00000" & TRG_WIN_PRE;
 
diff --git a/tdc_releases/tdc_v0.3/tdc_constraints.lpf b/tdc_releases/tdc_v0.3/tdc_constraints.lpf
deleted file mode 100644 (file)
index 0405bc9..0000000
+++ /dev/null
@@ -1,437 +0,0 @@
-
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# TDC Constraints
-#################################################################
-##############################################################################
-##                          REGION DECLERATION                             ##
-##############################################################################
-REGION "Region_E&F_1" "R11C50D" 10 60 DEVSIZE;
-REGION "Region_E&F_2" "R24C50D" 5 60 DEVSIZE;
-REGION "Region_E&F_3" "R38C50D" 10 60 DEVSIZE;
-REGION "Region_E&F_4" "R56C50D" 10 60 DEVSIZE;
-REGION "Region_E&F_5" "R74C50D" 10 60 DEVSIZE;
-REGION "Region_E&F_6" "R92C50D" 10 60 DEVSIZE;
-
-REGION "Region_E&F_7" "R11C120D" 10 44 DEVSIZE;
-REGION "Region_E&F_8" "R24C120D" 5 60 DEVSIZE;
-REGION "Region_E&F_9" "R38C120D" 10 60 DEVSIZE;
-REGION "Region_E&F_10" "R56C120D" 10 60 DEVSIZE;
-REGION "Region_E&F_11" "R74C120D" 10 60 DEVSIZE;
-REGION "Region_E&F_12" "R92C120D" 10 60 DEVSIZE;
-
-##############################################################################
-##                     REFERENCE CHANNEL PLACEMENT                         ##
-##############################################################################
-UGROUP "Ref_Ch" BBOX 1 51 
-       BLKNAME THE_TDC/The_Reference_Time/FC;
-LOCATE UGROUP "Ref_Ch" SITE "R8C66D" ;
-UGROUP "hit_ref_ch" 
-       BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO;
-LOCATE UGROUP "hit_ref_ch" SITE "R9C68D" ;
-
-##############################################################################
-##                 DELAY LINE and HIT BUFFER PLACEMENTS                    ##
-##############################################################################
-#
-UGROUP "FC_1" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_1_Channels/FC;
-LOCATE UGROUP "FC_1" SITE "R10C66D" ;
-UGROUP "hit_1" 
-       BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_1" SITE "R11C68D" ;
-#
-UGROUP "FC_2" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_2_Channels/FC;
-LOCATE UGROUP "FC_2" SITE "R21C66D" ;
-UGROUP "hit_2" 
-       BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_2" SITE "R22C68D" ;
-#
-UGROUP "FC_3" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_3_Channels/FC;
-LOCATE UGROUP "FC_3" SITE "R23C66D" ;
-UGROUP "hit_3" 
-       BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_3" SITE "R24C68D" ;
-#
-UGROUP "FC_4" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_4_Channels/FC;
-LOCATE UGROUP "FC_4" SITE "R30C66D" ;
-UGROUP "hit_4" 
-       BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_4" SITE "R31C68D" ;
-#
-UGROUP "FC_5" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_5_Channels/FC;
-LOCATE UGROUP "FC_5" SITE "R32C66D" ;
-UGROUP "hit_5" 
-       BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_5" SITE "R33C68D" ;
-#
-UGROUP "FC_6" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_6_Channels/FC;
-LOCATE UGROUP "FC_6" SITE "R35C66D" ;
-UGROUP "hit_6" 
-       BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_6" SITE "R36C68D" ;
-#
-UGROUP "FC_7" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_7_Channels/FC;
-LOCATE UGROUP "FC_7" SITE "R37C66D" ;
-UGROUP "hit_7" 
-       BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_7" SITE "R38C68D" ;
-#
-UGROUP "FC_8" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_8_Channels/FC;
-LOCATE UGROUP "FC_8" SITE "R48C66D" ;
-UGROUP "hit_8" 
-       BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_8" SITE "R49C68D" ;
-#
-UGROUP "FC_9" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_9_Channels/FC;
-LOCATE UGROUP "FC_9" SITE "R50C66D" ;
-UGROUP "hit_9" 
-       BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_9" SITE "R51C68D" ;
-#
-UGROUP "FC_10" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_10_Channels/FC;
-LOCATE UGROUP "FC_10" SITE "R53C66D" ;
-UGROUP "hit_10" 
-       BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_10" SITE "R54C68D" ;
-#
-UGROUP "FC_11" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_11_Channels/FC;
-LOCATE UGROUP "FC_11" SITE "R55C66D" ;
-UGROUP "hit_11" 
-       BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_11" SITE "R56C68D" ;
-#
-UGROUP "FC_12" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_12_Channels/FC;
-LOCATE UGROUP "FC_12" SITE "R66C66D" ;
-UGROUP "hit_12" 
-       BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_12" SITE "R67C68D" ;
-#
-UGROUP "FC_13" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_13_Channels/FC;
-LOCATE UGROUP "FC_13" SITE "R68C66D" ;
-UGROUP "hit_13" 
-       BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_13" SITE "R69C68D" ;
-#
-UGROUP "FC_14" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_14_Channels/FC;
-LOCATE UGROUP "FC_14" SITE "R71C66D" ;
-UGROUP "hit_14" 
-       BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_14" SITE "R72C68D" ;
-#
-UGROUP "FC_15" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_15_Channels/FC;
-LOCATE UGROUP "FC_15" SITE "R73C66D" ;
-UGROUP "hit_15" 
-       BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_15" SITE "R74C68D" ;
-
-
-
-
-
-UGROUP "FC_16" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_16_Channels/FC;
-LOCATE UGROUP "FC_16" SITE "R8C125D" ;
-UGROUP "hit_16" 
-       BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_16" SITE "R9C127D" ;
-#
-UGROUP "FC_17" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_17_Channels/FC;
-LOCATE UGROUP "FC_17" SITE "R10C125D" ;
-UGROUP "hit_17" 
-       BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_17" SITE "R11C127D" ;
-#
-UGROUP "FC_18" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_18_Channels/FC;
-LOCATE UGROUP "FC_18" SITE "R21C125D" ;
-UGROUP "hit_18" 
-       BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_18" SITE "R22C127D" ;
-#
-UGROUP "FC_19" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_19_Channels/FC;
-LOCATE UGROUP "FC_19" SITE "R23C125D" ;
-UGROUP "hit_19" 
-       BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_19" SITE "R24C127D" ;
-#
-UGROUP "FC_20" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_20_Channels/FC;
-LOCATE UGROUP "FC_20" SITE "R30C125D" ;
-UGROUP "hit_20" 
-       BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_20" SITE "R31C127D" ;
-#
-UGROUP "FC_21" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_21_Channels/FC;
-LOCATE UGROUP "FC_21" SITE "R32C125D" ;
-UGROUP "hit_21" 
-       BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_21" SITE "R33C127D" ;
-#
-UGROUP "FC_22" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_22_Channels/FC;
-LOCATE UGROUP "FC_22" SITE "R35C125D" ;
-UGROUP "hit_22" 
-       BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_22" SITE "R36C127D" ;
-#
-UGROUP "FC_23" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_23_Channels/FC;
-LOCATE UGROUP "FC_23" SITE "R37C125D" ;
-UGROUP "hit_23" 
-       BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_23" SITE "R38C127D" ;
-#
-UGROUP "FC_24" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_24_Channels/FC;
-LOCATE UGROUP "FC_24" SITE "R48C125D" ;
-UGROUP "hit_24" 
-       BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_24" SITE "R49C127D" ;
-#
-UGROUP "FC_25" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_25_Channels/FC;
-LOCATE UGROUP "FC_25" SITE "R50C125D" ;
-UGROUP "hit_25" 
-       BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_25" SITE "R51C127D" ;
-#
-UGROUP "FC_26" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_26_Channels/FC;
-LOCATE UGROUP "FC_26" SITE "R53C125D" ;
-UGROUP "hit_26" 
-       BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_26" SITE "R54C127D" ;
-#
-UGROUP "FC_27" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_27_Channels/FC;
-LOCATE UGROUP "FC_27" SITE "R55C125D" ;
-UGROUP "hit_27" 
-       BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_27" SITE "R56C127D" ;
-#
-UGROUP "FC_28" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_28_Channels/FC;
-LOCATE UGROUP "FC_28" SITE "R66C125D" ;
-UGROUP "hit_28" 
-       BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_28" SITE "R67C127D" ;
-#
-UGROUP "FC_29" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_29_Channels/FC;
-LOCATE UGROUP "FC_29" SITE "R68C125D" ;
-UGROUP "hit_29" 
-       BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_29" SITE "R69C127D" ;
-#
-UGROUP "FC_30" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_30_Channels/FC;
-LOCATE UGROUP "FC_30" SITE "R71C125D" ;
-UGROUP "hit_30" 
-       BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_30" SITE "R72C127D" ;
-#
-UGROUP "FC_31" BBOX 1 51 
-       BLKNAME THE_TDC/GEN_Channels_31_Channels/FC;
-LOCATE UGROUP "FC_31" SITE "R73C125D" ;
-UGROUP "hit_31" 
-       BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_31" SITE "R74C127D" ;
-
-##############################################################################
-##                          CHANNEL PLACEMENTS                             ##
-##############################################################################
-UGROUP "E&F_ref" # BBOX 4 5
-        BLKNAME THE_TDC/The_Reference_Time/hit_detect_i
-        BLKNAME THE_TDC/The_Reference_Time/hit_detect_reg
-       BLKNAME THE_TDC/The_Reference_Time/result_2_reg;
-LOCATE UGROUP "E&F_ref" REGION "Region_E&F_1" ;
-UGROUP "E&F_1" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_1_Channels/result_2_reg;
-LOCATE UGROUP "E&F_1" REGION "Region_E&F_1" ;
-UGROUP "E&F_2" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_2_Channels/result_2_reg;
-LOCATE UGROUP "E&F_2" REGION "Region_E&F_1" ;
-UGROUP "E&F_3" # BBOX 4 5
-        BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_3_Channels/result_2_reg;
-LOCATE UGROUP "E&F_3" REGION "Region_E&F_1" ;
-UGROUP "E&F_4" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_4_Channels/result_2_reg;
-LOCATE UGROUP "E&F_4" REGION "Region_E&F_2" ;
-UGROUP "E&F_5" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_5_Channels/result_2_reg;
-LOCATE UGROUP "E&F_5" REGION "Region_E&F_2" ;
-UGROUP "E&F_6" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_6_Channels/result_2_reg;
-LOCATE UGROUP "E&F_6" REGION "Region_E&F_3" ;
-UGROUP "E&F_7" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_7_Channels/result_2_reg;
-LOCATE UGROUP "E&F_7" REGION "Region_E&F_3" ;
-UGROUP "E&F_8" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_8_Channels/result_2_reg;
-LOCATE UGROUP "E&F_8" REGION "Region_E&F_3" ;
-UGROUP "E&F_9" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_9_Channels/result_2_reg;
-LOCATE UGROUP "E&F_9" REGION "Region_E&F_3" ;
-UGROUP "E&F_10" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_10_Channels/result_2_reg;
-LOCATE UGROUP "E&F_10" REGION "Region_E&F_4" ;
-UGROUP "E&F_11" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_11_Channels/result_2_reg;
-LOCATE UGROUP "E&F_11" REGION "Region_E&F_4" ;
-UGROUP "E&F_12" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_12_Channels/result_2_reg;
-LOCATE UGROUP "E&F_12" REGION "Region_E&F_4" ;
-UGROUP "E&F_13" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_13_Channels/result_2_reg;
-LOCATE UGROUP "E&F_13" REGION "Region_E&F_4" ;
-UGROUP "E&F_14" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_14_Channels/result_2_reg;
-LOCATE UGROUP "E&F_14" REGION "Region_E&F_5" ;
-UGROUP "E&F_15" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_15_Channels/result_2_reg;
-LOCATE UGROUP "E&F_15" REGION "Region_E&F_5" ;
-
-
-UGROUP "E&F_16" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_16_Channels/result_2_reg;
-LOCATE UGROUP "E&F_16" REGION "Region_E&F_7" ;
-UGROUP "E&F_17" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_17_Channels/result_2_reg;
-LOCATE UGROUP "E&F_17" REGION "Region_E&F_7" ;
-UGROUP "E&F_18" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_18_Channels/result_2_reg;
-LOCATE UGROUP "E&F_18" REGION "Region_E&F_7" ;
-UGROUP "E&F_19" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_19_Channels/result_2_reg;
-LOCATE UGROUP "E&F_19" REGION "Region_E&F_7" ;
-UGROUP "E&F_20" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_20_Channels/result_2_reg;
-LOCATE UGROUP "E&F_20" REGION "Region_E&F_8" ;
-UGROUP "E&F_21" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_21_Channels/result_2_reg;
-LOCATE UGROUP "E&F_21" REGION "Region_E&F_8" ;
-UGROUP "E&F_22" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_22_Channels/result_2_reg;
-LOCATE UGROUP "E&F_22" REGION "Region_E&F_9" ;
-UGROUP "E&F_23" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_23_Channels/result_2_reg;
-LOCATE UGROUP "E&F_23" REGION "Region_E&F_9" ;
-UGROUP "E&F_24" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_24_Channels/result_2_reg;
-LOCATE UGROUP "E&F_24" REGION "Region_E&F_9" ;
-UGROUP "E&F_25" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_25_Channels/result_2_reg;
-LOCATE UGROUP "E&F_25" REGION "Region_E&F_9" ;
-UGROUP "E&F_26" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_26_Channels/result_2_reg;
-LOCATE UGROUP "E&F_26" REGION "Region_E&F_10" ;
-UGROUP "E&F_27" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_27_Channels/result_2_reg;
-LOCATE UGROUP "E&F_27" REGION "Region_E&F_10" ;
-UGROUP "E&F_28" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_28_Channels/result_2_reg;
-LOCATE UGROUP "E&F_28" REGION "Region_E&F_10" ;
-UGROUP "E&F_29" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_29_Channels/result_2_reg;
-LOCATE UGROUP "E&F_29" REGION "Region_E&F_10" ;
-UGROUP "E&F_30" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_30_Channels/result_2_reg;
-LOCATE UGROUP "E&F_30" REGION "Region_E&F_11" ;
-UGROUP "E&F_31" # BBOX 4 5
-       BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_detect_i
-       BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_detect_reg
-       BLKNAME THE_TDC/GEN_Channels_31_Channels/result_2_reg;
-LOCATE UGROUP "E&F_31" REGION "Region_E&F_11" ;
-
-##############################################################################
-
-#MULTICYCLE TO PORT "TEST_LINE_*" 2.000000 X ;
-
-MULTICYCLE TO CELL "THE_TDC/GEN_Channels_*_Channels/lost_hit_cntr_*" 3.000000 X ;
-MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 3.000000 X ;
-
-
-MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_*_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-
diff --git a/tdc_releases/tdc_v0.3/trb3_periph.vhd b/tdc_releases/tdc_v0.3/trb3_periph.vhd
deleted file mode 100644 (file)
index 9967e2b..0000000
+++ /dev/null
@@ -1,631 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-
-
-entity trb3_periph is
-  port(
-    --Clocks
-    CLK_GPLL_LEFT        : in    std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT       : in    std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT        : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT       : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    --Trigger
-    TRIGGER_LEFT         : in    std_logic;  --left side trigger input from fan-out
-    TRIGGER_RIGHT        : in    std_logic;  --right side trigger input from fan-out
-    --Serdes
-    CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
-    CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
-    SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
-    SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
-    SERDES_ADDON_TX      : out   std_logic_vector(11 downto 0);
-    SERDES_ADDON_RX      : in    std_logic_vector(11 downto 0);
-    --Inter-FPGA Communication
-    FPGA5_COMM           : inout std_logic_vector(11 downto 0);
-                                        --Bit 0/1 input, serial link RX active
-                                        --Bit 2/3 output, serial link TX active
-    --Connection to ADA AddOn
-    SPARE_LINE           : inout std_logic_vector(3 downto 0);  --inputs only
-    INP                  : in    std_logic_vector(63 downto 0);
-    OUT_L_SCK            : out   std_logic;
-    OUT_L_SDO            : out   std_logic;
-    OUT_L_CS             : out   std_logic;
-    IN_L_SDI             : out   std_logic;
-    OUT_H_SCK            : out   std_logic;
-    OUT_H_SDO            : out   std_logic;
-    OUT_H_CS             : out   std_logic;
-    IN_H_SDI             : out   std_logic;
-    --Flash ROM & Reboot
-    FLASH_CLK            : out   std_logic;
-    FLASH_CS             : out   std_logic;
-    FLASH_DIN            : out   std_logic;
-    FLASH_DOUT           : in    std_logic;
-    PROGRAMN             : out   std_logic;  --reboot FPGA
-    --Misc
-    TEMPSENS             : inout std_logic;  --Temperature Sensor
-    CODE_LINE            : in    std_logic_vector(1 downto 0);
-    LED_GREEN            : out   std_logic;
-    LED_ORANGE           : out   std_logic;
-    LED_RED              : out   std_logic;
-    LED_YELLOW           : out   std_logic;
-    SUPPL                : in    std_logic;  --terminated diff pair, PCLK, Pads
-    --Test Connectors
-    TEST_LINE            : out   std_logic_vector(15 downto 0)
-    );
-  attribute syn_useioff                  : boolean;
-  --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of LED_GREEN     : signal is false;
-  attribute syn_useioff of LED_ORANGE    : signal is false;
-  attribute syn_useioff of LED_RED       : signal is false;
-  attribute syn_useioff of LED_YELLOW    : signal is false;
-  attribute syn_useioff of TEMPSENS      : signal is false;
-  attribute syn_useioff of PROGRAMN      : signal is false;
-  attribute syn_useioff of CODE_LINE     : signal is false;
-  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
-  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
-  --important signals
-  attribute syn_useioff of FLASH_CLK     : signal is true;
-  attribute syn_useioff of FLASH_CS      : signal is true;
-  attribute syn_useioff of FLASH_DIN     : signal is true;
-  attribute syn_useioff of FLASH_DOUT    : signal is true;
-  attribute syn_useioff of FPGA5_COMM    : signal is true;
-  attribute syn_useioff of TEST_LINE     : signal is true;
-  attribute syn_useioff of INP           : signal is false;
-  attribute syn_useioff of SPARE_LINE    : signal is true;
-  attribute syn_useioff of OUT_L_SCK     : signal is true;
-  attribute syn_useioff of OUT_L_SDO     : signal is true;
-  attribute syn_useioff of OUT_L_CS      : signal is true;
-  attribute syn_useioff of IN_L_SDI      : signal is true;
-  attribute syn_useioff of OUT_H_SCK     : signal is true;
-  attribute syn_useioff of OUT_H_SDO     : signal is true;
-  attribute syn_useioff of OUT_H_CS      : signal is true;
-  attribute syn_useioff of IN_H_SDI      : signal is true;
-end entity;
-
-
-architecture trb3_periph_arch of trb3_periph is
-  --Constants
-  constant REGIO_NUM_STAT_REGS : integer := 5;
-  constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-  attribute syn_keep     : boolean;
-  attribute syn_preserve : boolean;
-
-  --Clock / Reset
-  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-  signal clear_i                  : std_logic;
-  signal reset_i                  : std_logic;
-  signal GSR_N                    : std_logic;
-  attribute syn_keep of GSR_N     : signal is true;
-  attribute syn_preserve of GSR_N : signal is true;
-
-  --Media Interface
-  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
-  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
-  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
-  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
-  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
-  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
-  signal med_dataready_out  : std_logic;
-  signal med_read_out       : std_logic;
-  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
-  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
-  signal med_dataready_in   : std_logic;
-  signal med_read_in        : std_logic;
-
-  --LVL1 channel
-  signal timing_trg_received_i  : std_logic;
-  signal trg_data_valid_i       : std_logic;
-  signal trg_timing_valid_i     : std_logic;
-  signal trg_notiming_valid_i   : std_logic;
-  signal trg_invalid_i          : std_logic;
-  signal trg_type_i             : std_logic_vector(3 downto 0);
-  signal trg_number_i           : std_logic_vector(15 downto 0);
-  signal trg_code_i             : std_logic_vector(7 downto 0);
-  signal trg_information_i      : std_logic_vector(23 downto 0);
-  signal trg_int_number_i       : std_logic_vector(15 downto 0);
-  signal trg_multiple_trg_i     : std_logic;
-  signal trg_timeout_detected_i : std_logic;
-  signal trg_spurious_trg_i     : std_logic;
-  signal trg_missing_tmg_trg_i  : std_logic;
-  signal trg_spike_detected_i   : std_logic;
-
-  --Data channel
-  signal fee_trg_release_i    : std_logic;
-  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
-  signal fee_data_i           : std_logic_vector(31 downto 0);
-  signal fee_data_write_i     : std_logic;
-  signal fee_data_finished_i  : std_logic;
-  signal fee_almost_full_i    : std_logic;
-
-  --Slow Control channel
-  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-  --RegIO
-  signal my_address             : std_logic_vector (15 downto 0);
-  signal regio_addr_out         : std_logic_vector (15 downto 0);
-  signal regio_read_enable_out  : std_logic;
-  signal regio_write_enable_out : std_logic;
-  signal regio_data_out         : std_logic_vector (31 downto 0);
-  signal regio_data_in          : std_logic_vector (31 downto 0);
-  signal regio_dataready_in     : std_logic;
-  signal regio_no_more_data_in  : std_logic;
-  signal regio_write_ack_in     : std_logic;
-  signal regio_unknown_addr_in  : std_logic;
-  signal regio_timeout_out      : std_logic;
-
-  --Timer
-  signal global_time         : std_logic_vector(31 downto 0);
-  signal local_time          : std_logic_vector(7 downto 0);
-  signal time_since_last_trg : std_logic_vector(31 downto 0);
-  signal timer_ticks         : std_logic_vector(1 downto 0);
-
-  --Flash
-  signal spictrl_read_en  : std_logic;
-  signal spictrl_write_en : std_logic;
-  signal spictrl_data_in  : std_logic_vector(31 downto 0);
-  signal spictrl_addr     : std_logic;
-  signal spictrl_data_out : std_logic_vector(31 downto 0);
-  signal spictrl_ack      : std_logic;
-  signal spictrl_busy     : std_logic;
-  signal spimem_read_en   : std_logic;
-  signal spimem_write_en  : std_logic;
-  signal spimem_data_in   : std_logic_vector(31 downto 0);
-  signal spimem_addr      : std_logic_vector(5 downto 0);
-  signal spimem_data_out  : std_logic_vector(31 downto 0);
-  signal spimem_ack       : std_logic;
-
-  signal spi_bram_addr : std_logic_vector(7 downto 0);
-  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
-  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
-  signal spi_bram_we   : std_logic;
-
-  --FPGA Test
-  signal time_counter : unsigned(31 downto 0);
-
-  --TDC
-  signal hit_in_i : std_logic_vector(31 downto 1);
-
-  --TDC component
-  component TDC
-    generic (
-      CHANNEL_NUMBER : integer range 0 to 64;
-      STATUS_REG_NR  : integer range 0 to 6;
-      CONTROL_REG_NR : integer range 0 to 6);
-    port (
-      RESET                 : in  std_logic;
-      CLK_TDC               : in  std_logic;
-      CLK_READOUT           : in  std_logic;
-      REFERENCE_TIME        : in  std_logic;
-      HIT_IN                : in  std_logic_vector(CHANNEL_NUMBER-1 downto 1);
-      TRG_WIN_PRE           : in  std_logic_vector(10 downto 0);
-      TRG_WIN_POST          : in  std_logic_vector(10 downto 0);
-      TRG_DATA_VALID_IN     : in  std_logic;
-      VALID_TIMING_TRG_IN   : in  std_logic;
-      VALID_NOTIMING_TRG_IN : in  std_logic;
-      INVALID_TRG_IN        : in  std_logic;
-      TMGTRG_TIMEOUT_IN     : in  std_logic;
-      SPIKE_DETECTED_IN     : in  std_logic;
-      MULTI_TMG_TRG_IN      : in  std_logic;
-      SPURIOUS_TRG_IN       : in  std_logic;
-      TRG_NUMBER_IN         : in  std_logic_vector(15 downto 0);
-      TRG_CODE_IN           : in  std_logic_vector(7 downto 0);
-      TRG_INFORMATION_IN    : in  std_logic_vector(23 downto 0);
-      TRG_TYPE_IN           : in  std_logic_vector(3 downto 0);
-      TRG_RELEASE_OUT       : out std_logic;
-      TRG_STATUSBIT_OUT     : out std_logic_vector(31 downto 0);
-      DATA_OUT              : out std_logic_vector(31 downto 0);
-      DATA_WRITE_OUT        : out std_logic;
-      DATA_FINISHED_OUT     : out std_logic;
-      TDC_DEBUG             : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0);
-      LOGIC_ANALYSER_OUT    : out std_logic_vector(15 downto 0);
-      CONTROL_REG_IN        : in  std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0));
-  end component;
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-  GSR_N <= pll_lock;
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-      RESET_IN      => '0',              -- general reset signal (SYSCLK)
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-  THE_MAIN_PLL : pll_in200_out100
-    port map(
-      CLK   => CLK_GPLL_RIGHT,
-      CLKOP => clk_100_i,
-      CLKOK => clk_200_i,
-      LOCK  => pll_lock
-      );
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
-    generic map(
-      SERDES_NUM  => 1,                 --number of serdes in quad
-      EXT_CLOCK   => c_NO,              --use internal clock
-      USE_200_MHZ => c_YES              --run on 200 MHz clock
-      )
-    port map(
-      CLK                => clk_200_i,
-      SYSCLK             => clk_100_i,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
-      --Internal Connection
-      MED_DATA_IN        => med_data_out,
-      MED_PACKET_NUM_IN  => med_packet_num_out,
-      MED_DATAREADY_IN   => med_dataready_out,
-      MED_READ_OUT       => med_read_in,
-      MED_DATA_OUT       => med_data_in,
-      MED_PACKET_NUM_OUT => med_packet_num_in,
-      MED_DATAREADY_OUT  => med_dataready_in,
-      MED_READ_IN        => med_read_out,
-      REFCLK2CORE_OUT    => open,
-      --SFP Connection
-      SD_RXD_P_IN        => SERDES_INT_RX(2),
-      SD_RXD_N_IN        => SERDES_INT_RX(3),
-      SD_TXD_P_OUT       => SERDES_INT_TX(2),
-      SD_TXD_N_OUT       => SERDES_INT_TX(3),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
-      SD_PRSNT_N_IN      => FPGA5_COMM(0),
-      SD_LOS_IN          => FPGA5_COMM(0),
-      SD_TXDIS_OUT       => FPGA5_COMM(2),
-      -- Status and control port
-      STAT_OP            => med_stat_op,
-      CTRL_OP            => med_ctrl_op,
-      STAT_DEBUG         => med_stat_debug,
-      CTRL_DEBUG         => (others => '0')
-      );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
-  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-    generic map(
-      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,  --16 stat reg
-      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,  --8 cotrol reg
-      ADDRESS_MASK              => x"FFFF",
-      BROADCAST_BITMASK         => x"FF",
-      BROADCAST_SPECIAL_ADDR    => x"45",
-      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-      REGIO_HARDWARE_VERSION    => x"91000001",
-      REGIO_INIT_ADDRESS        => x"f300",
-      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-      CLOCK_FREQUENCY           => 125,
-      TIMING_TRIGGER_RAW        => c_YES,
-      --Configure data handler
-      DATA_INTERFACE_NUMBER     => 1,
-      DATA_BUFFER_DEPTH         => 13,         --13
-      DATA_BUFFER_WIDTH         => 32,
-      DATA_BUFFER_FULL_THRESH   => 2**13-800,  --2**13-1024
-      TRG_RELEASE_AFTER_DATA    => c_YES,
-      HEADER_BUFFER_DEPTH       => 9,
-      HEADER_BUFFER_FULL_THRESH => 2**9-16
-      )
-    port map(
-      CLK                => clk_100_i,
-      RESET              => reset_i,
-      CLK_EN             => '1',
-      MED_DATAREADY_OUT  => med_dataready_out,  -- open,  --
-      MED_DATA_OUT       => med_data_out,  -- open,  --
-      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open,  --
-      MED_READ_IN        => med_read_in,
-      MED_DATAREADY_IN   => med_dataready_in,
-      MED_DATA_IN        => med_data_in,
-      MED_PACKET_NUM_IN  => med_packet_num_in,
-      MED_READ_OUT       => med_read_out,  -- open,  --
-      MED_STAT_OP_IN     => med_stat_op,
-      MED_CTRL_OP_OUT    => med_ctrl_op,
-
-      --Timing trigger in
-      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
-      --LVL1 trigger to FEE
-      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
-      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
-      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
-      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
-
-      LVL1_TRG_TYPE_OUT        => trg_type_i,
-      LVL1_TRG_NUMBER_OUT      => trg_number_i,
-      LVL1_TRG_CODE_OUT        => trg_code_i,
-      LVL1_TRG_INFORMATION_OUT => trg_information_i,
-      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
-
-      --Information about trigger handler errors
-      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
-      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
-      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
-      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
-      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
-
-      --Response from FEE
-      FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
-      FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
-      FEE_DATA_IN                 => fee_data_i,
-      FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
-      FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
-      FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
-
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
-      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-      REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-      REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-      REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-      REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-      BUS_ADDR_OUT         => regio_addr_out,
-      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-      BUS_DATA_OUT         => regio_data_out,
-      BUS_DATA_IN          => regio_data_in,
-      BUS_DATAREADY_IN     => regio_dataready_in,
-      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-      BUS_WRITE_ACK_IN     => regio_write_ack_in,
-      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-      BUS_TIMEOUT_OUT      => regio_timeout_out,
-      ONEWIRE_INOUT        => TEMPSENS,
-      ONEWIRE_MONITOR_OUT  => open,
-
-      TIME_GLOBAL_OUT         => global_time,
-      TIME_LOCAL_OUT          => local_time,
-      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-      TIME_TICKS_OUT          => timer_ticks,
-
-      STAT_DEBUG_IPU              => open,
-      STAT_DEBUG_1                => open,
-      STAT_DEBUG_2                => open,
-      STAT_DEBUG_DATA_HANDLER_OUT => open,
-      STAT_DEBUG_IPU_HANDLER_OUT  => open,
-      STAT_TRIGGER_OUT            => open,
-      CTRL_MPLEX                  => (others => '0'),
-      IOBUF_CTRL_GEN              => (others => '0'),
-      STAT_ONEWIRE                => open,
-      STAT_ADDR_DEBUG             => open,
-      DEBUG_LVL1_HANDLER_OUT      => open
-      );
-
-  timing_trg_received_i <= TRIGGER_LEFT;
-
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
-  OUT_L_SCK <= '0';
-  OUT_L_SDO <= '0';
-  OUT_L_CS  <= '0';
-  OUT_H_SCK <= '0';
-  OUT_H_SDO <= '0';
-  OUT_H_CS  <= '0';
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 2,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
-      )
-    port map(
-      CLK   => clk_100_i,
-      RESET => reset_i,
-
-      DAT_ADDR_IN          => regio_addr_out,
-      DAT_DATA_IN          => regio_data_out,
-      DAT_DATA_OUT         => regio_data_in,
-      DAT_READ_ENABLE_IN   => regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
-      DAT_TIMEOUT_IN       => regio_timeout_out,
-      DAT_DATAREADY_OUT    => regio_dataready_in,
-      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
-      --Bus Handler (SPI CTRL)
-      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
-      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
-      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
-      BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
-      BUS_DATAREADY_IN(0)                 => spictrl_ack,
-      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
-      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
-      BUS_UNKNOWN_ADDR_IN(0)              => '0',
-      --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
-      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
-      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(1)                 => spimem_ack,
-      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
-      BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
-
-      STAT_DEBUG => open
-      );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-  THE_SPI_MASTER : spi_master
-    port map(
-      CLK_IN         => clk_100_i,
-      RESET_IN       => reset_i,
-      -- Slave bus
-      BUS_READ_IN    => spictrl_read_en,
-      BUS_WRITE_IN   => spictrl_write_en,
-      BUS_BUSY_OUT   => spictrl_busy,
-      BUS_ACK_OUT    => spictrl_ack,
-      BUS_ADDR_IN(0) => spictrl_addr,
-      BUS_DATA_IN    => spictrl_data_in,
-      BUS_DATA_OUT   => spictrl_data_out,
-      -- SPI connections
-      SPI_CS_OUT     => FLASH_CS,
-      SPI_SDI_IN     => FLASH_DOUT,
-      SPI_SDO_OUT    => FLASH_DIN,
-      SPI_SCK_OUT    => FLASH_CLK,
-      -- BRAM for read/write data
-      BRAM_A_OUT     => spi_bram_addr,
-      BRAM_WR_D_IN   => spi_bram_wr_d,
-      BRAM_RD_D_OUT  => spi_bram_rd_d,
-      BRAM_WE_OUT    => spi_bram_we,
-      -- Status lines
-      STAT           => open
-      );
-
--- data memory for SPI accesses
-  THE_SPI_MEMORY : spi_databus_memory
-    port map(
-      CLK_IN        => clk_100_i,
-      RESET_IN      => reset_i,
-      -- Slave bus
-      BUS_ADDR_IN   => spimem_addr,
-      BUS_READ_IN   => spimem_read_en,
-      BUS_WRITE_IN  => spimem_write_en,
-      BUS_ACK_OUT   => spimem_ack,
-      BUS_DATA_IN   => spimem_data_in,
-      BUS_DATA_OUT  => spimem_data_out,
-      -- state machine connections
-      BRAM_ADDR_IN  => spi_bram_addr,
-      BRAM_WR_D_OUT => spi_bram_wr_d,
-      BRAM_RD_D_IN  => spi_bram_rd_d,
-      BRAM_WE_IN    => spi_bram_we,
-      -- Status lines
-      STAT          => open
-      );
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
-  THE_FPGA_REBOOT : fpga_reboot
-    port map(
-      CLK       => clk_100_i,
-      RESET     => reset_i,
-      DO_REBOOT => common_ctrl_reg(15),
-      PROGRAMN  => PROGRAMN
-      );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-  LED_GREEN  <= not med_stat_op(9);
-  LED_ORANGE <= not med_stat_op(10);
-  LED_RED    <= not INP(0);
-  LED_YELLOW <= not med_stat_op(11);
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
-
---    TEST_LINE(15 downto 0) <= time_counter(15 downto 0);
-  ---------------------------------------------------------------------------
-  -- Test Circuits
-  ---------------------------------------------------------------------------
-  --process
-  --begin
-  --  wait until rising_edge(clk_100_i);
-  --  time_counter <= time_counter + 1;
-  --end process;
-
-  -------------------------------------------------------------------------------
-  -- TDC
-  -------------------------------------------------------------------------------
-
-  THE_TDC : TDC
-    generic map (
-      CHANNEL_NUMBER => 32,             -- Number of TDC channels
-      STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
-      CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
-    port map (
-      RESET                 => reset_i,
-      CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
-      CLK_READOUT           => clk_100_i,   -- Clock for the readout
-      REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
-      HIT_IN                => hit_in_i(31 downto 1),  -- Channel start signals
-      TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
-      TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
-      --
-      -- Trigger signals from handler
-      TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet
-      VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger signal from trbnet
-      VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,  -- valid notiming signal from trbnet
-      INVALID_TRG_IN        => trg_invalid_i,  -- invalid trigger signal from trbnet
-      TMGTRG_TIMEOUT_IN     => trg_timeout_detected_i,  -- timing trigger timeout signal from trbnet
-      SPIKE_DETECTED_IN     => trg_spike_detected_i,
-      MULTI_TMG_TRG_IN      => trg_multiple_trg_i,
-      SPURIOUS_TRG_IN       => trg_spurious_trg_i,
-      --
-      TRG_NUMBER_IN         => trg_number_i,  -- LVL1 trigger information package
-      TRG_CODE_IN           => trg_code_i,  --
-      TRG_INFORMATION_IN    => trg_information_i,   --
-      TRG_TYPE_IN           => trg_type_i,  -- LVL1 trigger information package
-      --
-      --Response to handler
-      TRG_RELEASE_OUT       => fee_trg_release_i,   -- trigger release signal
-      TRG_STATUSBIT_OUT     => fee_trg_statusbits_i,  -- status information of the tdc
-      DATA_OUT              => fee_data_i,  -- tdc data
-      DATA_WRITE_OUT        => fee_data_write_i,  -- data valid signal
-      DATA_FINISHED_OUT     => fee_data_finished_i,  -- readout finished signal
-      --
-      TDC_DEBUG             => stat_reg,
-      LOGIC_ANALYSER_OUT    => TEST_LINE,
-      CONTROL_REG_IN        => ctrl_reg);
-
-
-  hit_in_i(1) <= not timing_trg_received_i;
-  
-  Gen_Hit_In_Signals : for i in 1 to 15 generate
-    hit_in_i(i*2)   <= INP(i-1);
-    hit_in_i(i*2+1) <= not INP(i-1);
-  end generate Gen_Hit_In_Signals;
-
-end architecture;
index f9f15e40c29e52e3ae6e96869136951dcfeffde7..0de395a21c3103a9c4bb125cfea176fd5ab67124 100644 (file)
@@ -33,7 +33,7 @@ entity trb3_periph is
     --Connection to ADA AddOn
     SPARE_LINE           : inout std_logic_vector(3 downto 0);  --inputs only
     INP                  : in    std_logic_vector(63 downto 0);
-    DAC_SDO              : in    std_logic;
+--    DAC_SDO              : in    std_logic;
     DAC_SDI              : out   std_logic;
     DAC_SCK              : out   std_logic;
     DAC_CS               : out   std_logic_vector(3 downto 0);
@@ -616,7 +616,7 @@ begin
 
   THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER => 8,             -- Number of TDC channels
+      CHANNEL_NUMBER => 64,             -- Number of TDC channels
       STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
       CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
     port map (
@@ -624,7 +624,7 @@ begin
       CLK_TDC        => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT    => clk_100_i,      -- Clock for the readout
       REFERENCE_TIME => timing_trg_received_i,   -- Reference time input
-      HIT_IN         => hit_in_i(7 downto 1),   -- Channel start signals
+      HIT_IN         => hit_in_i(64 downto 1),   -- Channel start signals
       TRG_WIN_PRE    => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST   => ctrl_reg(58 downto 48),  -- Post-Trigger window width
 
@@ -655,8 +655,8 @@ begin
       CONTROL_REG_IN     => ctrl_reg);
 
 
---  -- For single edge measurements
-----  hit_in_i(64 downto 1) <= INP(63 downto 0);
+  -- For single edge measurements
+  hit_in_i(64 downto 1) <= INP(63 downto 0);
 
 --  -- For ToT Measurements
 --  hit_in_i(1) <= not timing_trg_received_i;