-- \r
SERDES_ACTIVE_IN : in std_logic; -- SerDes Tx / Rx channels operational\r
AN_COMPLETE_IN : in std_logic; -- Link AN completed\r
- MAC_READY_CONF_IN : in std_logic; -- MAC configuration completed\r
+ MAC_CONF_DONE_IN : in std_logic; -- MAC configuration completed\r
--\r
AN_RESTART_OUT : out std_logic;\r
- MAC_RECONF_OUT : out std_logic;\r
+ MAC_CONF_START_OUT : out std_logic;\r
+ MAC_CONF_STOP_OUT : out std_logic;\r
LINK_ACTIVE_OUT : out std_logic;\r
LINK_START_OUT : out std_logic;\r
LINK_STOP_OUT : out std_logic;\r
-- Components\r
\r
-- state machine signals\r
- type state_t is (INACTIVE,AN_WAIT,AN_RESTART,ENABLE_MAC,ACTIVATED);\r
+ type state_t is (INACTIVE,AN_WAIT,AN_RESTART,ENABLE_MAC,ACTIVATED,SHUTDOWN);\r
signal STATE, NEXT_STATE : state_t;\r
\r
-- Signals\r
signal dly_ctr_done : std_logic;\r
signal dly_ctr_rst_x : std_logic;\r
signal dly_ctr_rst : std_logic;\r
- signal reconf_mac_x : std_logic;\r
- signal reconf_mac : std_logic;\r
+ signal start_mac_x : std_logic;\r
+ signal start_mac : std_logic;\r
+ signal stop_mac_x : std_logic;\r
+ signal stop_mac : std_logic;\r
signal restart_an_x : std_logic;\r
signal restart_an : std_logic;\r
signal link_start_x : std_logic;\r
if ( RESET = '1' ) then\r
STATE <= INACTIVE;\r
restart_an <= '0';\r
- reconf_mac <= '0';\r
+ start_mac <= '0';\r
+ stop_mac <= '0';\r
dly_ctr_rst <= '1';\r
link_start <= '0';\r
link_stop <= '0';\r
elsif( rising_edge(CLK) ) then\r
STATE <= NEXT_STATE;\r
restart_an <= restart_an_x;\r
- reconf_mac <= reconf_mac_x;\r
+ start_mac <= start_mac_x;\r
+ stop_mac <= stop_mac_x;\r
dly_ctr_rst <= dly_ctr_rst_x;\r
link_start <= link_start_x;\r
link_stop <= link_stop_x;\r
end if;\r
end process THE_FSM;\r
\r
- THE_STATE_TRANSITIONS: process( STATE, SERDES_ACTIVE_IN, AN_COMPLETE_IN, MAC_READY_CONF_IN, dly_ctr_done )\r
+ THE_STATE_TRANSITIONS: process( STATE, SERDES_ACTIVE_IN, AN_COMPLETE_IN, MAC_CONF_DONE_IN, dly_ctr_done )\r
begin\r
restart_an_x <= '0';\r
- reconf_mac_x <= '0';\r
+ start_mac_x <= '0';\r
+ stop_mac_x <= '0';\r
dly_ctr_rst_x <= '1';\r
link_start_x <= '0';\r
link_stop_x <= '0';\r
if( AN_COMPLETE_IN = '1' ) then\r
-- AN completed\r
NEXT_STATE <= ENABLE_MAC;\r
- reconf_mac_x <= '1';\r
+ start_mac_x <= '1';\r
elsif( dly_ctr_done = '1' ) then\r
-- no AN within delay\r
NEXT_STATE <= AN_RESTART;\r
-- SerDes broken\r
NEXT_STATE <= INACTIVE;\r
else\r
- if( MAC_READY_CONF_IN = '1' ) then\r
+ if( MAC_CONF_DONE_IN = '1' ) then\r
NEXT_STATE <= ACTIVATED;\r
link_start_x <= '1';\r
else \r
NEXT_STATE <= ENABLE_MAC;\r
- reconf_mac_x <= '1';\r
+ start_mac_x <= '1';\r
end if;\r
end if;\r
\r
when ACTIVATED =>\r
if ( (SERDES_ACTIVE_IN = '0') or (AN_COMPLETE_IN = '0') ) then\r
-- SerDes broken\r
- NEXT_STATE <= INACTIVE;\r
+ NEXT_STATE <= SHUTDOWN;\r
link_stop_x <= '1';\r
+ stop_mac_x <= '1';\r
else\r
NEXT_STATE <= ACTIVATED;\r
end if;\r
\r
+ when SHUTDOWN =>\r
+ if( MAC_CONF_DONE_IN = '1' ) then\r
+ NEXT_STATE <= INACTIVE;\r
+ else \r
+ NEXT_STATE <= SHUTDOWN;\r
+ stop_mac_x <= '1';\r
+ end if;\r
+ \r
when others =>\r
NEXT_STATE <= INACTIVE;\r
end case;\r
end process THE_STATE_TRANSITIONS;\r
\r
- AN_RESTART_OUT <= restart_an;\r
- MAC_RECONF_OUT <= reconf_mac;\r
- LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0';\r
- LINK_START_OUT <= link_start;\r
- LINK_STOP_OUT <= link_stop;\r
+ AN_RESTART_OUT <= restart_an;\r
+ MAC_CONF_START_OUT <= start_mac;\r
+ MAC_CONF_STOP_OUT <= stop_mac;\r
+ LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0';\r
+ LINK_START_OUT <= link_start;\r
+ LINK_STOP_OUT <= link_stop;\r
\r
end architecture;\r
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
+--use work.trb_net16_hub_func.all;
+
+entity gbe_mac_control is
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+ -- signals to/from main controller
+ MC_READY_OUT : out std_logic;
+ MC_START_IN : in std_logic;
+ MC_STOP_IN : in std_logic;
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
+ TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
+ TSM_HCS_N_OUT : out std_logic;
+ TSM_HWRITE_N_OUT : out std_logic;
+ TSM_HREAD_N_OUT : out std_logic;
+ TSM_HREADY_N_IN : in std_logic;
+ TSM_HDATA_EN_N_IN : in std_logic;
+ -- Debug
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
+end entity gbe_mac_control;
+
+architecture gbe_mac_control_arch of gbe_mac_control is
+
+-- state machine signals
+ type state_t is (IDLE,WR_DIS,WR_DIS_W,WR_CTLL,WR_CTLL_W,WR_CTLH,WR_CTLH_W,WR_ENA,WR_ENA_W,DONE_W);
+ signal STATE : state_t;
+
+ signal reg_mode : std_logic_vector(7 downto 0);
+ signal reg_tx_rx_ctrl : std_logic_vector(15 downto 0);
+
+ signal haddr : std_logic_vector(7 downto 0);
+ signal hcsn : std_logic;
+ signal hwriten : std_logic;
+ signal hdata : std_logic_vector(7 downto 0);
+
+ signal tsm_ready : std_logic;
+
+begin
+
+ -- MAC main control register\r
+ -- address 0x00/0x01
+ reg_mode(7 downto 4) <= (others => '0');
+ reg_mode(3) <= '1'; -- tx_en
+ reg_mode(2) <= '1'; -- rx_en
+ reg_mode(1) <= '0'; -- flow_control en
+ reg_mode(0) <= '1'; -- gbe en
+\r
+ -- MAC setup register
+ -- address 0x02/0x03
+ reg_tx_rx_ctrl(15 downto 9) <= (others => '0'); -- reserved
+ reg_tx_rx_ctrl(8) <= '0'; -- receive short
+ reg_tx_rx_ctrl(7) <= '1'; -- receive broadcast
+ reg_tx_rx_ctrl(6) <= '1'; -- drop control
+ reg_tx_rx_ctrl(5) <= '0'; -- half_duplex en
+ reg_tx_rx_ctrl(4) <= '1'; -- receive multicast
+ reg_tx_rx_ctrl(3) <= '0'; -- receive pause
+ reg_tx_rx_ctrl(2) <= '0'; -- transmit disable FCS
+ reg_tx_rx_ctrl(1) <= '1'; -- receive discard FCS and padding
+ reg_tx_rx_ctrl(0) <= '1'; -- promiscuous mode
+
+ -----------------------------------------------------------
+ -- statemachine: clocked process
+ -----------------------------------------------------------
+ THE_FSM: process( CLK, RESET )
+ begin
+ if ( RESET = '1' ) then
+ STATE <= IDLE;
+ haddr <= x"00";
+ hdata <= x"00";
+ hcsn <= '1';
+ hwriten <= '1';\r
+ tsm_ready <= '0';
+ elsif( rising_edge(CLK) ) then\r
+\r
+ case STATE is\r
+\r
+ when IDLE =>\r
+ if( (MC_START_IN = '1') or (MC_STOP_IN = '1') ) then\r
+ STATE <= WR_DIS;\r
+ haddr <= x"00";\r
+ hdata <= x"00";\r
+ hcsn <= '0';\r
+ hwriten <= '0';\r
+ end if;\r
+\r
+ when WR_DIS =>\r
+ if( TSM_HREADY_N_IN = '0' ) then\r
+ STATE <= WR_DIS_W;\r
+ hcsn <= '1';
+ hwriten <= '1';
+ end if;\r
+\r
+ when WR_DIS_W =>
+ STATE <= WR_CTLL;
+ haddr <= x"02";
+ hdata <= reg_tx_rx_ctrl(7 downto 0);
+ hcsn <= '0';
+ hwriten <= '0';
+\r
+ when WR_CTLL =>
+ if( TSM_HREADY_N_IN = '0' ) then
+ STATE <= WR_CTLL_W;
+ hcsn <= '1';
+ hwriten <= '1';
+ end if;
+\r
+ when WR_CTLL_W =>
+ STATE <= WR_CTLH;
+ haddr <= x"03";
+ hdata <= reg_tx_rx_ctrl(15 downto 8);
+ hcsn <= '0';
+ hwriten <= '0';
+
+ when WR_CTLH =>
+ if( TSM_HREADY_N_IN = '0' ) then\r
+ STATE <= WR_CTLH_W;\r
+ hcsn <= '1';
+ hwriten <= '1';
+ end if;
+\r
+ when WR_CTLH_W =>
+ if( MC_START_IN = '1' ) then
+ STATE <= WR_ENA;
+ haddr <= x"00";
+ hdata <= reg_mode;
+ hcsn <= '0';
+ hwriten <= '0';
+ else
+ STATE <= DONE_W;
+ haddr <= x"00";
+ hdata <= x"00";
+ hcsn <= '1';
+ hwriten <= '1';\r
+ tsm_ready <= '1';
+ end if;
+\r
+ when WR_ENA =>
+ if( TSM_HREADY_N_IN = '0' ) then
+ STATE <= WR_ENA_W;\r
+ haddr <= x"00";\r
+ hdata <= x"00";
+ hcsn <= '1';
+ hwriten <= '1';
+ end if;
+\r
+ when WR_ENA_W =>
+ STATE <= DONE_W;\r
+ tsm_ready <= '1';
+\r
+ when DONE_W =>\r
+ if( (MC_START_IN = '0') and (MC_STOP_IN = '0') ) then\r
+ STATE <= IDLE;\r
+ tsm_ready <= '0';\r
+ end if;\r
+\r
+ when others =>\r
+ STATE <= IDLE;\r
+ haddr <= x"00";\r
+ hdata <= x"00";\r
+ hcsn <= '1';\r
+ hwriten <= '1';\r
+\r
+ end case;\r
+
+ end if;
+ end process THE_FSM;
+\r
+ TSM_HADDR_OUT <= haddr;
+ TSM_HDATA_OUT <= hdata;
+ TSM_HCS_N_OUT <= hcsn;
+ TSM_HWRITE_N_OUT <= hwriten;
+ TSM_HREAD_N_OUT <= '1';\r
+ MC_READY_OUT <= tsm_ready;\r
+
+end gbe_mac_control_arch;
+
+
-- FrameActive: we must not change to "receive" in the middle of a frame\r
-- when "buffer full" condition is deasserted.\r
-- Needs to be extra process, not inside the state machine!\r
- THE_FRAME_ACTIVE_PROC: process( CLK )\r
+ THE_FRAME_ACTIVE_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
+ if ( RESET = '1' ) then\r
frame_active <= '0';\r
- elsif( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then\r
frame_active <= '1';\r
elsif( (MAC_RX_EOF_IN = '1') and (frame_active = '1') ) then\r
frame_active <= '0';\r
end process THE_FRAME_ACTIVE_PROC;\r
\r
-- Read pointer for ring buffer\r
- THE_RD_PTR_PROC: process( CLK )\r
+ THE_RD_PTR_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- rd_ptr <= (others => '0');\r
- elsif( ce_rd_ptr_x = '1' ) then\r
+ if ( RESET = '1' ) then\r
+ rd_ptr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( ce_rd_ptr_x = '1' ) then\r
rd_ptr <= rd_ptr + 1;\r
end if;\r
end if;\r
end process THE_RD_PTR_PROC;\r
\r
-- Write pointer for ring buffer\r
- THE_WR_PTR_PROC: process( CLK )\r
+ THE_WR_PTR_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- wr_ptr <= (others => '0');\r
- elsif( ld_wr_ptr_x = '1' ) then\r
+ if ( RESET = '1' ) then\r
+ wr_ptr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( ld_wr_ptr_x = '1' ) then\r
wr_ptr <= unsigned(last_wr_ptr);\r
elsif( ce_wr_ptr_x = '1' ) then\r
wr_ptr <= wr_ptr + 1;\r
end process THE_WR_PTR_PROC;\r
\r
-- last write pointer: used to drop a broken frame, in case\r
- THE_LAST_WR_PTR_PROC: process( CLK )\r
+ THE_LAST_WR_PTR_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- last_wr_ptr <= (others => '0');\r
- elsif( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then\r
+ if ( RESET = '1' ) then\r
+ last_wr_ptr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then\r
last_wr_ptr <= std_logic_vector(wr_ptr);\r
end if;\r
end if;\r
else '0';\r
\r
-- FrameError: catches problem with FIFOFULL during a frame write.\r
- THE_FRAME_ERROR_PROC: process( CLK )\r
+ THE_FRAME_ERROR_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- frame_error <= '0';\r
- elsif( (frame_active = '1') and (rb_full_x = '1') and (MAC_RX_WR_IN = '1') ) then\r
+ if ( RESET = '1' ) then\r
+ frame_error <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( (frame_active = '1') and (rb_full_x = '1') and (MAC_RX_WR_IN = '1') ) then\r
frame_error <= '1';\r
elsif( (frame_active = '0') ) then -- could be better!\r
frame_error <= '0';\r
end process THE_FRAME_ERROR_PROC;\r
\r
-- FrameReq signal, one pulse only\r
- THE_FRAME_REQ_PROC: process( CLK )\r
+ THE_FRAME_REQ_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- frame_requested <= '0';\r
- elsif( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then\r
+ if ( RESET = '1' ) then\r
+ frame_requested <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then\r
frame_requested <= '1';\r
elsif( ((ram_q(8) = '1') and (frame_requested = '1')) or (empty_read_ack = '1') ) then\r
frame_requested <= '0';\r
rd_ram_x <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0';\r
ce_rd_ptr_x <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0';\r
\r
--- THE_SYNC_PROC: process( CLK )\r
--- begin\r
- empty_read_ack <= FRAME_REQ_IN and rb_empty_x when rising_edge(CLK);\r
+ empty_read_ack <= FRAME_REQ_IN and rb_empty_x when rising_edge(CLK);\r
sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK); \r
- FRAME_START_OUT <= sof_int when rising_edge(CLK);\r
- fifo_wr_int <= rd_ram_x when rising_edge(CLK);\r
- FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK);\r
- FRAME_ACK_OUT <= normal_read_ack_x or empty_read_ack when rising_edge(CLK); \r
- FIFO_Q_OUT <= ram_q when rising_edge(CLK);\r
--- end process THE_SYNC_PROC;\r
+ FRAME_START_OUT <= sof_int when rising_edge(CLK);\r
+ fifo_wr_int <= rd_ram_x when rising_edge(CLK);\r
+ FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK);\r
+ FRAME_ACK_OUT <= normal_read_ack_x or empty_read_ack when rising_edge(CLK); \r
+ FIFO_Q_OUT <= ram_q when rising_edge(CLK);\r
\r
-- FramesAvailable counter\r
- THE_FRAMES_AVAIL_PROC: process( CLK )\r
+ THE_FRAMES_AVAIL_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- frames_avail <= (others => '0');\r
- elsif( (STATE = FRAME_OK) and (normal_read_ack_x = '0') ) then\r
+ if ( RESET = '1' ) then\r
+ frames_avail <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( (STATE = FRAME_OK) and (normal_read_ack_x = '0') ) then\r
-- one frame written successfully\r
frames_avail <= frames_avail + 1;\r
elsif( (STATE /= FRAME_OK) and (normal_read_ack_x = '1') ) then\r
-----------------------------------------------------------\r
-- statemachine: clocked process\r
-----------------------------------------------------------\r
- THE_FSM: process( CLK )\r
+ THE_FSM: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if( RESET = '1' ) then\r
- STATE <= RX_DENY;\r
- else\r
- STATE <= NEXT_STATE;\r
- end if;\r
+ if ( RESET = '1' ) then\r
+ STATE <= RX_DENY;\r
+ elsif( rising_edge(CLK) ) then\r
+ STATE <= NEXT_STATE;\r
end if;\r
end process THE_FSM;\r
\r
\r
-- store the src port status\r
GEN_REGS: for I in 0 to 15 generate\r
- THE_SRC_STORE_PROC: process( CLK )\r
+ THE_SRC_STORE_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- stored_ports(I) <= '0';\r
- elsif( store_ports_x = '1' ) then\r
+ if ( RESET = '1' ) then\r
+ stored_ports(I) <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( store_ports_x = '1' ) then\r
stored_ports(I) <= DL_FRAME_AVAIL_IN(I);\r
elsif( DL_FRAME_ACK_IN(I) = '1' ) then\r
stored_ports(I) <= '0';\r
all_ports_done_x <= '1' when stored_ports = x"0000" else '0';\r
\r
-- select the port data\r
- THE_SELECT_PORT_PROC: process( CLK )\r
+ THE_SELECT_PORT_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if( RESET = '1' ) then\r
- select_ports <= (others => '0');\r
- mux_ports <= (others => '0');\r
- else\r
- select_ports <= next_port_x;\r
- mux_ports <= next_mux_x;\r
- end if;\r
+ if ( RESET = '1' ) then\r
+ select_ports <= (others => '0');\r
+ mux_ports <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ select_ports <= next_port_x;\r
+ mux_ports <= next_mux_x;\r
end if;\r
end process THE_SELECT_PORT_PROC;\r
\r
-----------------------------------------------------------\r
-- statemachine: clocked process\r
-----------------------------------------------------------\r
- THE_FSM: process( CLK )\r
+ THE_FSM: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if( RESET = '1' ) then\r
- STATE <= IDLE;\r
- ul_frame_req <= '0';\r
- local_frame_req <= '0';\r
- else\r
- STATE <= NEXT_STATE;\r
- ul_frame_req <= ul_frame_req_x;\r
- local_frame_req <= local_frame_req_x;\r
- end if;\r
+ if ( RESET = '1' ) then\r
+ STATE <= IDLE;\r
+ ul_frame_req <= '0';\r
+ local_frame_req <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ STATE <= NEXT_STATE;\r
+ ul_frame_req <= ul_frame_req_x;\r
+ local_frame_req <= local_frame_req_x;\r
end if;\r
end process THE_FSM;\r
\r
begin\r
\r
-- FrameActice signal - used to inhibit acceptance of runt frames\r
- THE_FRAME_ACTIVE_PROC: process( CLK )\r
+ THE_FRAME_ACTIVE_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- frame_active <= '0';\r
- elsif( FRAME_START_IN = '1' ) then\r
+ if ( RESET = '1' ) then\r
+ frame_active <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( FRAME_START_IN = '1' ) then\r
frame_active <= LINK_ACTIVE_IN;\r
elsif( frame_written = '1' ) then\r
frame_active <= '0';\r
frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0';\r
\r
-- FramesAvailable counter\r
- THE_FRAMES_AVAIL_PROC: process( CLK )\r
+ THE_FRAMES_AVAIL_PROC: process( CLK, RESET )\r
begin\r
- if( rising_edge(CLK) ) then\r
- if ( RESET = '1' ) then\r
- frames_avail <= (others => '0');\r
- elsif( (frame_written = '1') and (frame_read = '0') ) then\r
+ if ( RESET = '1' ) then\r
+ frames_avail <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( (frame_written = '1') and (frame_read = '0') ) then\r
-- one frame written successfully\r
frames_avail <= frames_avail + 1;\r
elsif( (frame_written = '0') and (frame_read = '1') ) then\r
signal mac_rx_eof : std_logic_vector(3 downto 0);
signal mac_rx_err : std_logic_vector(3 downto 0);
signal mac_rx_fifofull : std_logic_vector(3 downto 0);
- signal mac_ready_conf : std_logic_vector(3 downto 0);
- signal mac_reconf : std_logic_vector(3 downto 0);
+ signal mac_conf_done : std_logic_vector(3 downto 0);
+ signal mac_conf_start : std_logic_vector(3 downto 0);
+ signal mac_conf_stop : std_logic_vector(3 downto 0);
signal link_active : std_logic_vector(3 downto 0);
signal led_timer : unsigned(19 downto 0);
DEBUG_OUT(i * 32 + 25) <= '0'; -- (25)
DEBUG_OUT(i * 32 + 24) <= '0'; -- (24)
DEBUG_OUT(i * 32 + 23) <= '0'; -- (23)
- DEBUG_OUT(i * 32 + 22) <= '0'; -- (22)
- DEBUG_OUT(i * 32 + 21) <= '0'; -- (21)
- DEBUG_OUT(i * 32 + 20) <= '0'; -- (20)
+ DEBUG_OUT(i * 32 + 22) <= tsm_hready_n(i); -- (22)
+ DEBUG_OUT(i * 32 + 21) <= tsm_hwrite_n(i); -- (21)
+ DEBUG_OUT(i * 32 + 20) <= tsm_hcs_n(i); -- (20)
DEBUG_OUT(i * 32 + 19) <= TX_PCS_RST_IN; -- (19)
DEBUG_OUT(i * 32 + 18) <= rx_pcs_rst(i); -- (18)
DEBUG_OUT(i * 32 + 17) <= rx_serdes_rst(i); -- (17)
DEBUG_OUT(i * 32 + 15) <= lsm_status(i); -- (15)
DEBUG_OUT(i * 32 + 14) <= sd_rx_cv_error(i); -- (14)
DEBUG_OUT(i * 32 + 13) <= rx_cdr_lol(i); -- (13)
- DEBUG_OUT(i * 32 + 12) <= sci_ch_i(0); -- (12)
- DEBUG_OUT(i * 32 + 11) <= is_wap_zero(i); -- (11)
- DEBUG_OUT(i * 32 + 10) <= sci_read_i; -- (10)
- DEBUG_OUT(i * 32 + 9) <= mac_ready_conf(i); -- (9)
- DEBUG_OUT(i * 32 + 8) <= mac_reconf(i); -- (8)
+ DEBUG_OUT(i * 32 + 12) <= is_wap_zero(i); -- (12)
+ DEBUG_OUT(i * 32 + 11) <= sci_read_i; -- (11)
+ DEBUG_OUT(i * 32 + 10) <= mac_conf_done(i); -- (10)
+ DEBUG_OUT(i * 32 + 9) <= mac_conf_stop(i); -- (9)
+ DEBUG_OUT(i * 32 + 8) <= mac_conf_start(i); -- (8)
DEBUG_OUT(i * 32 + 7) <= an_restart_i(i); -- (7)
DEBUG_OUT(i * 32 + 6) <= an_link_ok_i(i); -- (6)
DEBUG_OUT(i * 32 + 5) <= mr_page_rx_i(i); --(5)
txmac_clk => MASTER_CLK_IN,
rxmac_clk => MASTER_CLK_IN,
reset_n => CLEAR_N, --RESET_N, -- CHECKIFWORKS
- ------------------- Input signals to the GMII ----------------
+ ------------------- Input signals to the Gdhcp_startMII ----------------
rxd => pcs_rxd(i * 8 + 7 downto i * 8),
rx_dv => pcs_rx_en(i),
rx_er => pcs_rx_er(i),
);
-- responsible for loading the TSMAC registers
- -- CAN BE OPTIMIZED
- TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+ THE_GBE_MAC_CONTROL: entity gbe_mac_control
port map(
CLK => MASTER_CLK_IN,
- RESET => CLEAR, --RESET, -- CHECKIFWORKS
- -- signals to/from main controller
- MC_TSMAC_READY_OUT => mac_ready_conf(i),
- MC_RECONF_IN => mac_reconf(i),
- MC_GBE_EN_IN => '1',
--- MC_RX_DISCARD_FCS => '0',
- MC_PROMISC_IN => '1',
--- MC_MAC_ADDR_IN => (others => '0'),
- -- signal to/from Host interface of TriSpeed MAC
+ RESET => CLEAR, --RESET, -- CHECKIFWORKS
+ -- signals to/from main controller
+ MC_READY_OUT => mac_conf_done(i),
+ MC_START_IN => mac_conf_start(i),
+ MC_STOP_IN => mac_conf_stop(i),
+ -- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT => tsm_haddr(i * 8 + 7 downto i * 8),
TSM_HDATA_OUT => tsm_hdata(i * 8 + 7 downto i * 8),
TSM_HCS_N_OUT => tsm_hcs_n(i),
TSM_HREAD_N_OUT => tsm_hread_n(i),
TSM_HREADY_N_IN => tsm_hready_n(i),
TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
- -- Debug
+ -- Debug
DEBUG_OUT => open
);
-
+
-- initializes MAC after AN is complete
THE_FW_GBE_LSM: entity gbe_lsm
port map(
RESET => CLEAR, --RESET, -- CHECKIFWORKS
SERDES_ACTIVE_IN => serdes_active(i),
AN_COMPLETE_IN => an_link_ok_i(i),
- MAC_READY_CONF_IN => mac_ready_conf(i),
+ MAC_CONF_DONE_IN => mac_conf_done(i),
AN_RESTART_OUT => an_restart_i(i),
- MAC_RECONF_OUT => mac_reconf(i),
+ MAC_CONF_START_OUT => mac_conf_start(i),
+ MAC_CONF_STOP_OUT => mac_conf_stop(i),
LINK_ACTIVE_OUT => link_active(i),
DEBUG => open
);
LINK_ACTIVE_IN => link_active(i)
);
+ -- TO BE REMOVED. NOT NEEDED ANYMORE.
PCS_AN_READY_OUT(i) <= an_link_ok_i(i); -- needed for internal SCTRL
+
LINK_ACTIVE_OUT(i) <= link_active(i);
-- LED connections, can be simplified by CE signal, to get rid of local counter instances
led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
end architecture gbe_med_fifo_arch;
-
--- -- Debug signals, MSB to LSB
--- DEBUG_OUT((i + 1) * 32 - 1) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 2) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 3) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 4) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 5) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 6) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 7) <= '0';
--- DEBUG_OUT((i + 1) * 32 - 8) <= an_link_ok_i(i);
--- DEBUG_OUT((i + 1) * 32 - 9) <= is_wap_zero(i);
--- DEBUG_OUT((i + 1) * 32 - 10) <= sci_read_i;
--- DEBUG_OUT((i + 1) * 32 - 11) <= tx_clk_avail_i;
--- DEBUG_OUT((i + 1) * 32 - 12) <= link_active(i);
--- DEBUG_OUT((i + 1) * 32 - 13) <= an_complete(i);
--- DEBUG_OUT((i + 1) * 32 - 14) <= cfg_rx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 15) <= idle_rx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 16) <= unknown_rx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 17) <= cfg_tx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 18) <= idle_tx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 19) <= unknown_tx_int(i);
--- DEBUG_OUT((i + 1) * 32 - 20) <= TX_LINK_READY_IN;
--- DEBUG_OUT((i + 1) * 32 - 21) <= link_rx_ready(i);
--- DEBUG_OUT((i + 1) * 32 - 22) <= rx_serdes_rst(i);
--- DEBUG_OUT((i + 1) * 32 - 23) <= rx_pcs_rst(i);
--- DEBUG_OUT((i + 1) * 32 - 24) <= sd_rx_disp_error(i);
--- DEBUG_OUT((i + 1) * 32 - 25) <= sd_rx_cv_error(i);
--- DEBUG_OUT((i + 1) * 32 - 26) <= lsm_status(i);
--- DEBUG_OUT((i + 1) * 32 - 27) <= rx_los_low(i);
--- DEBUG_OUT((i + 1) * 32 - 28) <= rx_cdr_lol(i);
--- DEBUG_OUT((i + 1) * 32 - 29) <= TX_PCS_RST_IN;
--- DEBUG_OUT((i + 1) * 32 - 30) <= tx_plol_lol;
--- DEBUG_OUT((i + 1) * 32 - 31) <= RESET;
--- DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR;
jspc29 / trbnet.git / commitdiff