NX_FRAME_CLOCK_OUT : out std_logic;\r
NX_FRAME_SYNC_OUT : out std_logic;\r
NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);\r
+ NX_NEW_FRAME_OUT : out std_logic;\r
\r
-- Slave bus \r
SLV_READ_IN : in std_logic;\r
\r
architecture Behavioral of nx_timestamp_fifo_read is\r
\r
+ -----------------------------------------------------------------------------\r
+ -- NX_TIMESTAMP_CLK Domain\r
+ -----------------------------------------------------------------------------\r
+\r
-- FIFO Input Handler\r
signal fifo_full : std_logic;\r
signal fifo_write_enable : std_logic;\r
signal frame_clock_ctr_inc_l : std_logic;\r
signal frame_clock_ctr_inc : std_logic;\r
\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- CLK_IN Domain\r
+ -----------------------------------------------------------------------------\r
+\r
-- FIFO Output Handler\r
+ type STATES is (S_IDLE,\r
+ S_READ_FIFO\r
+ );\r
+\r
+ signal STATE, NEXT_STATE : STATES;\r
+\r
signal fifo_out : std_logic_vector(35 downto 0);\r
signal fifo_empty : std_logic;\r
signal fifo_read_enable_x : std_logic;\r
signal fifo_read_enable : std_logic;\r
signal register_fifo_data_x : std_logic_vector(31 downto 0);\r
signal register_fifo_data : std_logic_vector(31 downto 0);\r
- signal fifo_new_data_x : std_logic;\r
- signal fifo_new_data : std_logic;\r
+ signal fifo_new_frame_x : std_logic;\r
+ signal fifo_new_frame_o : std_logic;\r
\r
- signal frame_clock_ctr_inc_r : std_logic;\r
- signal frame_clock_ctr_inc_s : std_logic;\r
signal frame_clock_ctr_inc_o : std_logic;\r
\r
- -- Sync NX Frame Process\r
-\r
-- RS Sync FlipFlop\r
- signal nx_frame_synced_o : std_logic;\r
- signal rs_sync_set : std_logic;\r
- signal rs_sync_reset : std_logic;\r
- \r
- -- Sync Process\r
- signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
- signal frame_sync_wait_ctr : unsigned (7 downto 0);\r
- \r
- -- Slave Bus\r
- signal slv_data_out_o : std_logic_vector(31 downto 0);\r
- signal slv_no_more_data_o : std_logic;\r
- signal slv_unknown_addr_o : std_logic;\r
- signal slv_ack_o : std_logic;\r
- signal register_fifo_status : std_logic_vector(31 downto 0);\r
-\r
- type STATES is (S_IDLE,\r
- S_READ_FIFO\r
- );\r
- signal STATE, NEXT_STATE : STATES;\r
+ signal nx_frame_synced_o : std_logic;\r
\r
+ -- Frame Sync Process \r
type STATES_SYNC is (S_SYNC_CHECK,\r
S_SYNC_RESYNC,\r
S_SYNC_WAIT\r
);\r
- signal STATE_SYNC : STATES_SYNC;\r
\r
+ signal STATE_SYNC, NEXT_STATE_SYNC: STATES_SYNC;\r
+\r
+ signal rs_sync_set : std_logic;\r
+ signal rs_sync_reset : std_logic;\r
+ signal frame_clock_ctr_inc_s : std_logic;\r
+ signal frame_sync_wait_ctr : unsigned(7 downto 0);\r
+ signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
+ signal frame_sync_wait_done : std_logic;\r
+ \r
+ signal rs_sync_set_x : std_logic;\r
+ signal rs_sync_reset_x : std_logic;\r
+ signal frame_clock_ctr_inc_s_x : std_logic;\r
+ signal frame_sync_wait_ctr_x : unsigned(7 downto 0);\r
+ signal nx_frame_resync_ctr_x : unsigned(7 downto 0);\r
+\r
+ -- Slave Bus \r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ signal register_fifo_status : std_logic_vector(31 downto 0);\r
+ signal frame_clock_ctr_inc_r : std_logic;\r
\r
begin\r
\r
DEBUG_OUT(0) <= CLK_IN;\r
\r
- DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; -- fifo_write_enable;\r
--- DEBUG_OUT(2) <= fifo_full;\r
--- DEBUG_OUT(3) <= fifo_write_enable;\r
--- DEBUG_OUT(4) <= fifo_empty;\r
--- DEBUG_OUT(5) <= fifo_read_enable;\r
- \r
- -- DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT;\r
- -- DEBUG_OUT(3) <= ;\r
- -- DEBUG_OUT(5) <= ;\r
- -- DEBUG_OUT(6) <= ;\r
- -- DEBUG_OUT(7) <= '0';\r
- DEBUG_OUT(6) <= NX_FRAME_CLOCK_OUT;\r
- DEBUG_OUT(7) <= frame_clock_ctr_inc;\r
--- DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_OUT(7 downto 0);\r
- --DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN(7 downto 0);\r
- DEBUG_OUT(9 downto 8) <= frame_clock_ctr;\r
+ DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;\r
+ DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT;\r
+ DEBUG_OUT(3) <= NX_FRAME_SYNC_OUT;\r
+ DEBUG_OUT(4) <= NX_NEW_FRAME_OUT;\r
+ DEBUG_OUT(5) <= frame_clock_ctr_inc_o;\r
+ DEBUG_OUT(7 downto 6) <= (others => '0');\r
+ DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN(7 downto 0);\r
\r
-----------------------------------------------------------------------------\r
- -- Dual Clock FIFO 8bit to 32bit\r
+ -- Dual Clock FIFO 9bit to 36bit\r
-----------------------------------------------------------------------------\r
\r
-- Send data to FIFO\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1') then\r
fifo_read_enable <= '0';\r
- fifo_new_data <= '0';\r
+ fifo_new_frame_o <= '0';\r
register_fifo_data <= (others => '0');\r
STATE <= S_IDLE;\r
register_fifo_data <= (others => '0');\r
else\r
fifo_read_enable <= fifo_read_enable_x;\r
- fifo_new_data <= fifo_new_data_x;\r
+ fifo_new_frame_o <= fifo_new_frame_x;\r
register_fifo_data <= register_fifo_data_x;\r
STATE <= NEXT_STATE;\r
end if;\r
\r
begin\r
fifo_read_enable_x <= '0';\r
- fifo_new_data_x <= '0';\r
+ fifo_new_frame_x <= '0';\r
register_fifo_data_x <= register_fifo_data;\r
\r
frame_tag := fifo_out(35) & fifo_out(26) &\r
end if;\r
\r
when S_READ_FIFO =>\r
- fifo_new_data_x <= '1';\r
+ fifo_new_frame_x <= '1';\r
case frame_tag is\r
when "1000" =>\r
register_fifo_data_x(31 downto 24) <= fifo_out(34 downto 27);\r
register_fifo_data_x(23 downto 16) <= fifo_out(25 downto 18);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(16 downto 9);\r
- register_fifo_data_x(7 downto 0) <= fifo_out(7 downto 0);\r
+ register_fifo_data_x(15 downto 8) <= fifo_out(16 downto 9);\r
+ register_fifo_data_x( 7 downto 0) <= fifo_out( 7 downto 0);\r
when "0100" => \r
register_fifo_data_x(31 downto 24) <= fifo_out( 7 downto 0);\r
register_fifo_data_x(23 downto 16) <= fifo_out(34 downto 27);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(25 downto 18);\r
- register_fifo_data_x(7 downto 0) <= fifo_out(16 downto 9);\r
+ register_fifo_data_x(15 downto 8) <= fifo_out(25 downto 18);\r
+ register_fifo_data_x( 7 downto 0) <= fifo_out(16 downto 9);\r
when "0010" => \r
register_fifo_data_x(31 downto 24) <= fifo_out(16 downto 9);\r
- register_fifo_data_x(23 downto 16) <= fifo_out(7 downto 0);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(34 downto 27);\r
- register_fifo_data_x(7 downto 0) <= fifo_out(25 downto 18);\r
+ register_fifo_data_x(23 downto 16) <= fifo_out( 7 downto 0);\r
+ register_fifo_data_x(15 downto 8) <= fifo_out(34 downto 27);\r
+ register_fifo_data_x( 7 downto 0) <= fifo_out(25 downto 18);\r
when "0001" => \r
- register_fifo_data_x(31 downto 24) <= fifo_out(25 downto 18);\r
- register_fifo_data_x(23 downto 16) <= fifo_out(16 downto 9);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(7 downto 0);\r
- register_fifo_data_x(7 downto 0) <= fifo_out(34 downto 27);\r
+ register_fifo_data_x(31 downto 24) <= fifo_out(25 downto 18);\r
+ register_fifo_data_x(23 downto 16) <= fifo_out(16 downto 9);\r
+ register_fifo_data_x(15 downto 8) <= fifo_out( 7 downto 0);\r
+ register_fifo_data_x( 7 downto 0) <= fifo_out(34 downto 27);\r
\r
when others =>\r
register_fifo_data_x <= (others => '1');\r
- fifo_new_data_x <= '0';\r
+ fifo_new_frame_x <= '0';\r
end case;\r
NEXT_STATE <= S_IDLE;\r
\r
end process PROC_FIFO_READ;\r
\r
\r
+ -----------------------------------------------------------------------------\r
+ -- Sync to NX_DATA FRAME\r
+ -----------------------------------------------------------------------------\r
+ \r
-- RS FlipFlop to hold Sync Status\r
PROC_RS_FRAME_SYNCED: process(CLK_IN)\r
begin\r
end if;\r
end process PROC_RS_FRAME_SYNCED;\r
\r
- -- Sync to NX_DATA FRAME \r
- PROC_SYNC_TO_NO_DATA: process(CLK_IN)\r
+ -- Frame Resync Timer_done Timer\r
+ nx_timer_1: nx_timer\r
+ generic map (\r
+ CTR_WIDTH => 8\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => frame_sync_wait_ctr,\r
+ TIMER_DONE_OUT => frame_sync_wait_done\r
+ );\r
\r
- variable fifo_tag_given : std_logic_vector(3 downto 0);\r
- \r
+ -- Frame Sync process\r
+ PROC_SYNC_TO_NX_FRAME_TRANSFER: process(CLK_IN)\r
begin\r
- fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
- fifo_out(17) & fifo_out(8);\r
+ \r
\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
rs_sync_set <= '0';\r
rs_sync_reset <= '1';\r
+ frame_clock_ctr_inc_s <= '0';\r
nx_frame_resync_ctr <= (others => '0');\r
frame_sync_wait_ctr <= (others => '0');\r
- frame_clock_ctr_inc_s <= '0';\r
STATE_SYNC <= S_SYNC_CHECK;\r
else\r
- rs_sync_set <= '0';\r
- rs_sync_reset <= '0';\r
- frame_clock_ctr_inc_s <= '0';\r
+ rs_sync_set <= rs_sync_set_x;\r
+ rs_sync_reset <= rs_sync_reset_x;\r
+ frame_clock_ctr_inc_s <= frame_clock_ctr_inc_s_x;\r
+ nx_frame_resync_ctr <= nx_frame_resync_ctr_x;\r
+ frame_sync_wait_ctr <= frame_sync_wait_ctr_x;\r
+ STATE_SYNC <= NEXT_STATE_SYNC;\r
+ end if;\r
+ end if;\r
+ end process PROC_SYNC_TO_NX_FRAME_TRANSFER;\r
\r
- DEBUG_OUT(5 downto 2) <= fifo_tag_given;\r
- \r
- case STATE_SYNC is\r
-\r
- when S_SYNC_CHECK =>\r
- case register_fifo_data is\r
- when x"7f7f7f06" =>\r
- rs_sync_set <= '1';\r
- STATE_SYNC <= S_SYNC_CHECK;\r
-\r
- when x"067f7f7f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
-\r
- when x"7f067f7f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when x"7f7f067f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
-\r
- when others =>\r
- STATE_SYNC <= S_SYNC_CHECK;\r
- \r
- end case;\r
-\r
- when S_SYNC_RESYNC =>\r
- rs_sync_reset <= '1';\r
- frame_clock_ctr_inc_s <= '1';\r
- nx_frame_resync_ctr <= nx_frame_resync_ctr + 1;\r
- frame_sync_wait_ctr <= x"ff";\r
- STATE_SYNC <= S_SYNC_WAIT;\r
-\r
- when S_SYNC_WAIT =>\r
- if (frame_sync_wait_ctr > 0) then\r
- frame_sync_wait_ctr <= frame_sync_wait_ctr -1;\r
- STATE_SYNC <= S_SYNC_WAIT;\r
- else\r
- STATE_SYNC <= S_SYNC_CHECK;\r
- end if;\r
+ PROC_SYNC_TO_NX_FRAME: process(STATE_SYNC)\r
+\r
+ variable fifo_tag_given : std_logic_vector(3 downto 0);\r
\r
+ begin\r
+ rs_sync_set_x <= '0';\r
+ rs_sync_reset_x <= '0';\r
+ frame_clock_ctr_inc_s_x <= '0';\r
+ nx_frame_resync_ctr_x <= nx_frame_resync_ctr;\r
+ frame_sync_wait_ctr_x <= (others => '0');\r
+\r
+ fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
+ fifo_out(17) & fifo_out(8);\r
+ \r
+ case STATE_SYNC is\r
+ \r
+ when S_SYNC_CHECK =>\r
+ case register_fifo_data is\r
+ when x"7f7f7f06" =>\r
+ rs_sync_set_x <= '1';\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+\r
+ when x"067f7f7f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when x"7f067f7f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when x"7f7f067f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when others =>\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+ \r
end case;\r
\r
- end if;\r
- end if;\r
- end process PROC_SYNC_TO_NO_DATA;\r
+ when S_SYNC_RESYNC =>\r
+ rs_sync_reset_x <= '1';\r
+ frame_clock_ctr_inc_s_x <= '1';\r
+ nx_frame_resync_ctr_x <= nx_frame_resync_ctr + 1;\r
+ frame_sync_wait_ctr_x <= x"ff";\r
+ NEXT_STATE_SYNC <= S_SYNC_WAIT;\r
+\r
+ when S_SYNC_WAIT =>\r
+ if (frame_sync_wait_done = '0') then\r
+ NEXT_STATE_SYNC <= S_SYNC_WAIT;\r
+ else\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+ end if;\r
+ \r
+ end case;\r
+ end process PROC_SYNC_TO_NX_FRAME;\r
\r
NX_FRAME_SYNC_OUT <= nx_frame_synced_o;\r
\r
--- \r
--- -------------------------------------------------------------------------------\r
--- -- TRBNet Slave Bus\r
--- -------------------------------------------------------------------------------\r
--- \r
--- -- Cross ClockDomain NX_TIMESTAMP_CLK_IN --> CLK_IN, for simplicity just\r
--- -- cross all signals, even the CLK_IN ones\r
--- -- PROC_SYNC_FIFO_SIGNALS: process(CLK_IN)\r
--- -- begin\r
--- -- if( rising_edge(CLK_IN) ) then\r
--- -- if( RESET_IN = '1' ) then\r
--- -- fifo_empty_x <= '0';\r
--- -- fifo_empty <= '0';\r
--- -- \r
--- -- fifo_full_x <= '0';\r
--- -- fifo_full <= '0';\r
--- -- \r
--- -- fifo_write_enable_x <= '0';\r
--- -- fifo_write_enable <= '0';\r
--- -- \r
--- -- fifo_read_enable_x <= '0';\r
--- -- fifo_read_enable <= '0';\r
--- -- \r
--- -- fifo_write_skip_ctr_x <= (others => '0');\r
--- -- fifo_write_skip_ctr_o <= (others => '0');\r
--- -- else\r
--- -- fifo_empty_x <= fifo_empty_i;\r
--- -- fifo_empty <= fifo_empty_x;\r
--- -- \r
--- -- fifo_full_x <= fifo_full_i;\r
--- -- fifo_full <= fifo_full_x;\r
--- -- \r
--- -- fifo_write_enable_x <= fifo_write_enable;\r
--- -- fifo_write_enable <= fifo_write_enable_x;\r
--- -- \r
--- -- fifo_read_enable_x <= fifo_read_enable_o;\r
--- -- fifo_read_enable <= fifo_read_enable_x;\r
--- -- \r
--- -- fifo_write_skip_ctr_x <= fifo_write_skip_ctr;\r
--- -- fifo_write_skip_ctr_o <= fifo_write_skip_ctr_x;\r
--- -- end if;\r
--- -- end if;\r
--- -- end process PROC_SYNC_FIFO_SIGNALS;\r
--- \r
+ \r
+ -----------------------------------------------------------------------------\r
+ -- TRBNet Slave Bus\r
+ -----------------------------------------------------------------------------\r
\r
register_fifo_status(0) <= fifo_write_enable;\r
register_fifo_status(1) <= fifo_full;\r
register_fifo_status(4) <= fifo_read_enable;\r
register_fifo_status(5) <= fifo_empty;\r
register_fifo_status(7 downto 6) <= (others => '0');\r
- register_fifo_status(15 downto 8) <= (others => '0');-- fifo_write_skip_ctr;\r
+ register_fifo_status(15 downto 8) <= (others => '0');\r
register_fifo_status(23 downto 16) <= nx_frame_resync_ctr;\r
register_fifo_status(30 downto 24) <= (others => '0');\r
register_fifo_status(31) <= nx_frame_synced_o;\r
\r
if (SLV_READ_IN = '1') then\r
case SLV_ADDR_IN is\r
- when x"0000" => slv_data_out_o <= register_fifo_data;\r
- when x"0001" => slv_data_out_o <= register_fifo_status;\r
- when others => slv_unknown_addr_o <= '1';\r
- slv_ack_o <= '0'; \r
+ when x"0000" =>\r
+ slv_data_out_o <= register_fifo_data;\r
+\r
+ when x"0001" =>\r
+ slv_data_out_o <= register_fifo_status;\r
+\r
+ when others =>\r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0'; \r
end case;\r
\r
elsif (SLV_WRITE_IN = '1') then\r
case SLV_ADDR_IN is\r
- when x"0001" => frame_clock_ctr_inc_r <= '1';\r
- when others => slv_unknown_addr_o <= '1'; \r
- slv_ack_o <= '0';\r
+ when x"0001" =>\r
+ frame_clock_ctr_inc_r <= '1';\r
+\r
+ when others =>\r
+ slv_unknown_addr_o <= '1'; \r
+ slv_ack_o <= '0';\r
end case; \r
else\r
slv_ack_o <= '0';\r
frame_clock_ctr_inc_o <= frame_clock_ctr_inc_r or frame_clock_ctr_inc_s;\r
\r
-- Output Signals\r
- SLV_DATA_OUT <= slv_data_out_o; \r
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
- SLV_ACK_OUT <= slv_ack_o;\r
-\r
- NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
- NX_TIMESTAMP_OUT <= register_fifo_data;\r
-\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o;\r
+\r
+ NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
+ NX_TIMESTAMP_OUT <= register_fifo_data;\r
+ NX_NEW_FRAME_OUT <= fifo_new_frame_o;\r
+ \r
end Behavioral;\r
jspc29 / trb3.git / commitdiff