--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity InputStage is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ DIN : in std_logic_vector(7 downto 0);
+ DOUT : out std_logic_vector(15 downto 0);
+
+ ACTIVE : out std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of InputStage is
+
+ signal clk_rx : std_logic;
+ signal reset_i : std_logic;
+ signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0');
+
+ signal data_i : std_logic_vector(15 downto 0);
+ signal add_reg : std_logic_vector(31 downto 0);
+
+ type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT);
+ type state_arrt is array (0 to 7) of state_t;
+
+ type unsigned_arr is array(0 to 7) of unsigned(6 downto 0);
+ signal sample_good, sample_bad : unsigned_arr := (others => (others => '0'));
+ signal first_good, first_bad : unsigned_arr := (others => (others => '1'));
+ signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0'));
+ signal active_i : std_logic_vector(7 downto 0);
+
+begin
+
+reset_i <= RESET when rising_edge(CLK);
+
+THE_IN : entity work.mimosis_inp
+ port map (
+ clkin=>CLK,
+ reset=>reset_i,
+ sclk=>clk_rx,
+ data_cflag(7 downto 0)=>s_cflag,
+ data_direction(7 downto 0)=>(others => '0'),
+ data_loadn(7 downto 0)=>s_loadn,
+ data_move(7 downto 0)=>s_move,
+ datain(7 downto 0)=>DIN,
+ q(15 downto 0)=>data_i
+ );
+
+
+DOUT <= data_i;
+ACTIVE <= and(active_i);
+
+gen_finders : for i in 0 to 7 generate
+ signal timer : unsigned(14 downto 0);
+ signal state : state_t;
+ signal count : unsigned(11 downto 0);
+ signal pos : unsigned(6 downto 0);
+ signal lastsample : std_logic;
+ signal train : unsigned(3 downto 0);
+ signal last : std_logic_vector(1 downto 0);
+
+begin
+ PROC_FIND : process begin
+ wait until rising_edge(CLK);
+ s_loadn(i) <= not add_reg(i+16);
+ active_i(i) <= '0';
+
+ case state is
+ when START =>
+ timer <= 0;
+ count <= 0;
+ s_move(i) <= '0';
+ state <= LISTEN;
+
+ when LISTEN =>
+ if timer(timer'left) = '1' then
+ state <= STEP;
+ if count >= 2047 and count <= 2049 then
+ sample_good(i) <= sample_good(i) + 1;
+ lastsample <= '1';
+ if first_good(i) > pos then
+ first_good(i) <= pos;
+ end if;
+ if last_bad(i) < pos and lastsample = '0' then
+ last_bad(i) <= pos;
+ end if;
+
+ else
+ lastsample <= '0';
+ sample_bad(i) <= sample_bad(i) + 1;
+ if first_bad(i) > pos then
+ first_bad(i) <= pos;
+ end if;
+ if last_good(i) < pos and lastsample = '1' then
+ last_good(i) <= pos;
+ end if;
+ end if;
+ else
+ timer <= timer + 1;
+ end if;
+
+ last <= data_i(i*2+1 downto i*2);
+
+ if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and
+ data_i(i*2+1 downto i*2) = last then
+ train <= train + 1;
+ else
+ train <= x"0";
+ end if;
+
+ if train = x"3" then
+ count <= count + 1;
+ end if;
+
+
+ when STEP =>
+ if s_cflag(i) = '0' then
+ s_move(i) <= '1';
+ pos <= pos + 1;
+ state <= START;
+ else
+ state <= CALC;
+ s_loadn(i) <= '0';
+ end if;
+
+ when CALC =>
+ if first_good(i) = "0000000" then
+ pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";
+ else
+ pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1);
+ end if;
+ state <= SET0;
+
+ when SET0 =>
+ posi(i) <= pos;
+ state <= SET1;
+
+ when SET1 =>
+ state <= SET2;
+ s_move(i) <= '1';
+
+ when SET2 =>
+ s_move(i) <= '0';
+ if pos = 0 then
+ state <= ENDWAIT;
+ else
+ state <= SET3;
+ pos <= pos - 1;
+ end if;
+
+ when SET3 =>
+ state <= SET1;
+
+ when ENDWAIT =>
+ active_i(i) <= '1';
+ state <= ENDWAIT;
+
+ end case;
+
+ if reset_i = '1' or add_reg(0) = '1' then
+ state <= START;
+ pos <= 0;
+ s_loadn(i) <= '0';
+ active_i(i) <= '0';
+ sample_good(i) <= 0;
+ sample_bad(i) <= 0;
+ last_good(i) <= 0;
+ last_bad(i) <= 0;
+ first_good(i) <= (others => '1');
+ first_bad(i) <= (others => '1');
+ end if;
+ end process;
+end generate;
+
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(clk_sys);
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.data <= (others => '0');
+ addr := to_integer(unsigned(BUS_RX.addr(2 downto 0)));
+ if BUS_RX.write = '1' then
+ if BUS_RX.addr(15 downto 0) = x"0010" then
+ BUS_TX.ack <= '1';
+ add_reg <= BUS_RX.data;
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(15 downto 0) = x"0010" then
+ BUS_TX.data <= add_reg;
+ elsif BUS_RX.addr(15 downto 4) = x"000" then
+ if BUS_RX.addr(3) = '0' then
+ BUS_TX.data(6 downto 0) <= std_logic_vector(sample_good(addr));
+ BUS_TX.data(14 downto 8) <= std_logic_vector(sample_bad(addr));
+ BUS_TX.data(16) <= s_cflag(addr);
+ BUS_TX.data(20) <= active_i(addr);
+ BUS_TX.data(30 downto 24)<= std_logic_vector(posi(addr));
+ else
+ BUS_TX.data(6 downto 0) <= std_logic_vector(first_good(addr));
+ BUS_TX.data(14 downto 8) <= std_logic_vector(last_good(addr));
+ BUS_TX.data(22 downto 16) <= std_logic_vector(first_bad(addr));
+ BUS_TX.data(30 downto 24) <= std_logic_vector(last_bad(addr));
+ end if;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+
+ end if;
+ end if;
+end process;
+
+
+
+
+end architecture;
--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity MimosisInput is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ INPUT : in std_logic_vector(7 downto 0);
+
+ BUSRDO_RX : in READOUT_RX;
+ BUSRDO_TX : out READOUT_TX;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of MimosisInput is
+ constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
+ constant WORD_LIMIT : integer := 3990;
+
+ signal input_active_i : std_logic;
+ signal data_i : std_logic_vector(15 downto 0);
+ signal inp_i : std_logic_vector(7 downto 0);
+ signal word_i : std_logic_vector(31 downto 0);
+ signal word_valid : std_logic;
+
+ signal businp_rx, busword_rx : CTRLBUS_RX;
+ signal businp_tx, busword_tx : CTRLBUS_TX;
+
+ signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic;
+ signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic;
+ signal ct_fifo_data_out : std_logic_vector(31 downto 0);
+
+ signal buffer_empty, buffer_full : std_logic;
+ signal buffer_write, buffer_read : std_logic;
+ signal buffer_valid, buffer_nextvalid : std_logic;
+ signal buffer_din, buffer_dout : std_logic_vector(31 downto 0);
+ signal buffer_fill : std_logic_vector(13 downto 0);
+
+ type state_t is (IDLE,START_COPY, COPY,FINISH,DONE);
+ signal state : state_t;
+ signal word_count : integer range 0 to 8191;
+
+
+begin
+
+ THE_IN : entity work.InputStage
+ port map (
+ CLK => CLK,
+ CLK_SYS => CLK_SYS,
+ RESET => RESET,
+
+ DIN => INPUT,
+ DOUT => data_i,
+ ACTIVE => input_active_i,
+
+ BUS_RX => businp_rx,
+ BUS_TX => businp_tx
+ );
+
+
+ THE_WORDS: entity work.WordAlign
+ port map(
+ CLK => CLK,
+ CLK_SYS => CLK_SYS,
+ RESET => RESET,
+
+ DIN => data_i,
+ DOUT => word_i,
+ VALID => word_valid,
+
+ ACTIVE => input_active_i,
+
+ BUS_RX => busword_rx,
+ BUS_TX => busword_tx
+ );
+
+
+----------------------------------------------------------------------
+-- Clock Domain Transfer
+----------------------------------------------------------------------
+THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg
+ port map(
+ Data(31 downto 0) => word_i(31 downto 0),
+ Data(35 downto 32) => "0000",
+ WrClock => CLK,
+ RdClock => CLK_SYS,
+ WrEn => word_valid,
+ RdEn => ct_fifo_read,
+ Reset => RESET,
+ RPReset => RESET,
+ Q(31 downto 0) => ct_fifo_data_out(31 downto 0),
+ Empty => ct_fifo_empty,
+ Full => ct_fifo_full,
+ AlmostFull => ct_fifo_afull
+ );
+
+ ct_fifo_read <= '1';
+ ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS);
+ ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS);
+
+----------------------------------------------------------------------
+-- Frame Copy
+----------------------------------------------------------------------
+ buffer_write <= ct_fifo_valid;
+ buffer_din <= ct_fifo_data_out;
+
+----------------------------------------------------------------------
+-- Main Fifo
+----------------------------------------------------------------------
+THE_FIFO : entity work.fifo_36x8k_oreg
+ port map(
+ Data(31 downto 0) => buffer_din,
+ Clock => CLK_SYS,
+ WrEn => buffer_write,
+ RdEn => buffer_read,
+ Reset => RESET,
+ AmFullThresh => "1111111110000",
+ Q(31 downto 0) => buffer_dout,
+ WCNT => buffer_fill,
+ Empty => buffer_empty,
+ Full => open,
+ AlmostFull => buffer_full
+ );
+
+ buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS);
+ buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS);
+
+---------------------------------------------------------------------------
+-- Buffer Handler
+---------------------------------------------------------------------------
+PROC_RDO : process begin
+ wait until rising_edge(CLK_SYS);
+ if state = IDLE and buffer_full = '1' then
+ buffer_read <= '1';
+ else
+ buffer_read <= '0';
+ end if;
+
+
+ BUSRDO_TX.busy_release <= '0';
+ BUSRDO_TX.data_write <= '0';
+ BUSRDO_TX.data_finished <= '0';
+
+ case state is
+ when IDLE =>
+ if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then
+ state <= START_COPY;
+ buffer_read <= '1';
+ word_count <= 0;
+ end if;
+ if BUSRDO_RX.invalid_trg = '1' then
+ state <= FINISH;
+ end if;
+ when START_COPY =>
+ state <= COPY;
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+
+ when COPY =>
+
+ if word_count = WORD_LIMIT or buffer_valid = '0' then
+ state <= FINISH;
+ else
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+ BUSRDO_TX.data <= buffer_dout;
+ BUSRDO_TX.data_write <= '1';
+ end if;
+
+ when FINISH =>
+ BUSRDO_TX.data_finished <= '1';
+ state <= DONE;
+
+ when DONE =>
+ BUSRDO_TX.busy_release <= '1';
+ state <= IDLE;
+ end case;
+
+end process;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 1, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => CLK_SYS,
+ RESET => RESET,
+
+ REGIO_RX => BUS_RX,
+ REGIO_TX => BUS_TX,
+
+ BUS_RX(0) => businp_rx,
+ BUS_RX(1) => busword_rx,
+
+ BUS_TX(0) => businp_tx,
+ BUS_TX(1) => busword_tx,
+ STAT_DEBUG => open
+ );
+
+
+
+end architecture;
--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity WordAlign is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ DIN : in std_logic_vector(15 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ VALID : out std_logic;
+
+ ACTIVE : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of WordAlign is
+ constant IDLE_WORD : std_logic_vector(15 downto 0) := x"FCAA";
+ constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
+
+
+ signal reset_i : std_logic;
+ type word_arr is array(0 to 7) of std_logic_vector(23 downto 0);
+ signal shift_reg, words, data_reg : word_arr;
+
+ signal doubleword : std_logic_vector(31 downto 0);
+ signal doubleword_valid : std_logic;
+
+ signal control_reg : std_logic_vector(31 downto 0);
+ alias CONF_channel_enable : std_logic_vector is control_reg(7 downto 0);
+ alias CONF_fixalign : std_logic is control_reg(8);
+ alias CONF_writeall : std_logic is control_reg(9);
+
+ signal bittime : integer range 0 to 31 := 0;
+
+ signal word_update : std_logic_vector(7 downto 0);
+ signal found_idle : std_logic_vector(7 downto 0) := (others => '0');
+ signal last_word_update, next_last_word_update : std_logic;
+ signal copycnt : integer range 0 to 4;
+
+begin
+
+bittime <= bittime + 1 when rising_edge(CLK);
+
+gen_links: for i in 0 to 7 generate
+ signal bitcnt : integer range 0 to 7 := 0;
+ signal oddeven : std_logic;
+ signal shift_reg : std_logic_vector(16 downto 0);
+begin
+ process begin
+ wait until rising_edge(CLK);
+ bitcnt <= bitcnt + 1;
+ word_update(i) <= '0';
+ shift_reg <= shift_reg(14 downto 0) & DIN(i*2) & DIN(i*2+1);
+
+ if CONF_fixalign = '0' and ACTIVE = '1' then
+ if shift_reg(15 downto 0) = IDLE_WORD then
+ oddeven <= '1';
+ bitcnt <= 1;
+ found_idle(i) <= '1';
+ elsif shift_reg(16 downto 1) = IDLE_WORD then
+ oddeven <= '0';
+ bitcnt <= 1;
+ found_idle(i) <= '1';
+ end if;
+ end if;
+
+ if bitcnt = 0 then
+ word_update(i) <= '1';
+ if oddeven = '1' then
+ words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(15 downto 0);
+ else
+ words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(16 downto 1);
+ end if;
+ end if;
+
+ end process;
+end generate;
+
+next_last_word_update <= word_update(0) when rising_edge(CLK);
+last_word_update <= next_last_word_update when rising_edge(CLK);
+
+PROC_COPY_MUX : process begin
+ wait until rising_edge(CLK);
+ doubleword_valid <= '0';
+ copycnt <= copycnt + 1;
+ if last_word_update = '1' then
+ data_reg <= words;
+ copycnt <= 0;
+ elsif copycnt = 0 then
+ doubleword <= data_reg(0)(15 downto 0) & data_reg(1)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 1 then
+ doubleword <= data_reg(2)(15 downto 0) & data_reg(3)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 2 then
+ doubleword <= data_reg(4)(15 downto 0) & data_reg(5)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 3 then
+ doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 4 then
+ copycnt <= copycnt;
+ end if;
+end process;
+
+PROC_FIFO_WRITE : process begin
+ wait until rising_edge(CLK);
+ DOUT <= doubleword;
+ VALID <= '0';
+ if doubleword_valid = '1' and (doubleword /= IDLE_WORD & IDLE_WORD or CONF_writeall = '1') then
+ VALID <= '1';
+ end if;
+end process;
+
+
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(clk_sys);
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.data <= (others => '0');
+ addr := to_integer(unsigned(BUS_RX.addr(2 downto 0)));
+ if BUS_RX.write = '1' then
+ if BUS_RX.addr(15 downto 0) = x"0000" then
+ BUS_TX.ack <= '1';
+ control_reg <= BUS_RX.data;
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(15 downto 0) = x"0000" then
+ BUS_TX.data <= control_reg;
+ elsif BUS_RX.addr(15 downto 4) = x"001" then
+ if BUS_RX.addr(3) = '0' then
+ BUS_TX.data <= "000" & found_idle(addr) & x"0" & words(addr);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+
+ end if;
+ end if;
+end process;
+
+
+
+end architecture;
--TDC settings
constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
- -- 0: single edge only,
- -- 1: same channel,
- -- 2: alternating channels,
- -- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
- -- mode: 0, 1, 2, 3, 7
- -- size: 32, 64, 96, 128, dyn
- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
- -- 0: Single fine time as the sum of the two transitions
- -- 1: Double fine time, individual transitions
- -- 13: Debug - fine time + (if 0x3ff full chain)
- -- 14: Debug - single fine time and the ROM addresses for the two transitions
- -- 15: Debug - complete carry chain dump
-
- constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+ constant FPGA_SIZE : string := "85KUM";
+-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+-- -- 0: single edge only,
+-- -- 1: same channel,
+-- -- 2: alternating channels,
+-- -- 3: same channel with stretcher
+-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+-- -- mode: 0, 1, 2, 3, 7
+-- -- size: 32, 64, 96, 128, dyn
+-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+-- -- 0: Single fine time as the sum of the two transitions
+-- -- 1: Double fine time, individual transitions
+-- -- 13: Debug - fine time + (if 0x3ff full chain)
+-- -- 14: Debug - single fine time and the ROM addresses for the two transitions
+-- -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 15; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 15000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
- t(15) := '1'; --TDC
- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+-- t(15) := '1'; --TDC
+-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
Q1=>qb0);
udel_dataini7: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini7, LOADN=>data_loadn(7),
MOVE=>data_move(7), DIRECTION=>data_direction(7),
Z=>dataini_t7, CFLAG=>data_cflag(7));
udel_dataini6: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini6, LOADN=>data_loadn(6),
MOVE=>data_move(6), DIRECTION=>data_direction(6),
Z=>dataini_t6, CFLAG=>data_cflag(6));
udel_dataini5: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini5, LOADN=>data_loadn(5),
MOVE=>data_move(5), DIRECTION=>data_direction(5),
Z=>dataini_t5, CFLAG=>data_cflag(5));
udel_dataini4: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini4, LOADN=>data_loadn(4),
MOVE=>data_move(4), DIRECTION=>data_direction(4),
Z=>dataini_t4, CFLAG=>data_cflag(4));
udel_dataini3: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini3, LOADN=>data_loadn(3),
MOVE=>data_move(3), DIRECTION=>data_direction(3),
Z=>dataini_t3, CFLAG=>data_cflag(3));
udel_dataini2: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini2, LOADN=>data_loadn(2),
MOVE=>data_move(2), DIRECTION=>data_direction(2),
Z=>dataini_t2, CFLAG=>data_cflag(2));
udel_dataini1: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini1, LOADN=>data_loadn(1),
MOVE=>data_move(1), DIRECTION=>data_direction(1),
Z=>dataini_t1, CFLAG=>data_cflag(1));
udel_dataini0: DELAYF
- generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
port map (A=>buf_dataini0, LOADN=>data_loadn(0),
MOVE=>data_move(0), DIRECTION=>data_direction(0),
Z=>dataini_t0, CFLAG=>data_cflag(0));
ModuleName=pll_200_160
SourceFormat=vhdl
ParameterFileVersion=1.0
-Date=06/04/2019
-Time=11:21:53
+Date=07/02/2021
+Time=12:07:59
[Parameters]
Verilog=0
CLKOP_DIV=4
CLKOP_ACTUAL_FREQ=160.000000
CLKOP_MUXA=DISABLED
-CLKOS_Enable=DISABLED
-CLKOS_FREQ=100.00
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=320
CLKOS_TOL=0.0
-CLKOS_DIV=1
-CLKOS_ACTUAL_FREQ=
+CLKOS_DIV=2
+CLKOS_ACTUAL_FREQ=320.000000
CLKOS_MUXB=DISABLED
CLKOS2_Enable=DISABLED
CLKOS2_FREQ=100.00
PLL_USE_SMI=DISABLED
[Command]
-cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1
+cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1
<lattice:device>LFE5UM-85F-8BG756C</lattice:device>
<lattice:synthesis>synplify</lattice:synthesis>
<lattice:date>2019-06-04.11:21:55</lattice:date>
- <lattice:modified>2019-06-04.11:21:55</lattice:modified>
- <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:modified>2021-07-02.12:08:04</lattice:modified>
+ <lattice:diamond>3.11.2.446</lattice:diamond>
<lattice:language>VHDL</lattice:language>
<lattice:attributes>
<lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Date</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">06/04/2019</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">07/02/2021</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>ModuleName</lattice:lpckey>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Time</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">11:21:53</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">12:07:59</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>VendorName</lattice:lpckey>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">320.000000</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_Enable</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">320</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
<lattice:lpcsection lattice:name="Command"/>
<lattice:lpcentry>
<lattice:lpckey>cmd_line</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
</lattice:lpcentry>
</lattice:lpc>
<lattice:groups/>
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446
-- Module Version: 5.7
---/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /d/jspc22/trb/git/trb5sc/mimosis/project/pll_200_160/pll_200_160.fdc
+--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/trb5sc/mimosis/cores/pll_200_160/pll_200_160.fdc
--- Tue Jun 4 11:21:55 2019
+-- Fri Jul 2 12:08:04 2021
library IEEE;
use IEEE.std_logic_1164.all;
entity pll_200_160 is
port (
CLKI: in std_logic;
- CLKOP: out std_logic);
+ CLKOP: out std_logic;
+ CLKOS: out std_logic);
end pll_200_160;
architecture Structure of pll_200_160 is
-- internal signal declarations
signal REFCLK: std_logic;
signal LOCK: std_logic;
+ signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
+ attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "12";
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
- CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
+ CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
- OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
- CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
+ CLKOS2_DIV=> 1, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
- ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
+ ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>REFCLK, CLKINTFB=>open);
+ CLKOS <= CLKOS_t;
CLKOP <= CLKOP_t;
end Structure;
-BLOCK NET "bustdc_tx*";
+
+#################################################################
+# Basic Settings
+#################################################################
+
+FREQUENCY PORT CLK_200 200 MHz;
+FREQUENCY PORT CLK_125 125 MHz;
+FREQUENCY PORT CLK_EXT 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
+
+FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
+
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
+BLOCK PATH TO PORT "TEST_LINE*";
+
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+GSR_NET NET "clear_i";
+
+# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+
+
+REGION "MEDIA" "R81C44D" 13 25;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
+
+BLOCK NET "THE_MIMOSIS/THE_IN/reset_i";
+BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i";
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns;
+
+BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*";
+BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*";
set_option -symbolic_fsm_compiler 1
set_option -top_module "trb5sc_mimosis"
set_option -resource_sharing false
+set_option -vhdl2008 true
# map options
set_option -frequency 120
add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
-add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
#Fifos
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
#Flash & Reload, Tools
#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
##########################################
-
-#########################################
-#channel 0, backplane
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
-
-#channel 1, SFP
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
-##########################################
-
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
add_file -vhdl -lib work "./cores/mimosis_inp.vhd"
add_file -vhdl -lib work "./cores/testout.vhd"
+add_file -vhdl -lib work "./code/MimosisInput.vhd"
+add_file -vhdl -lib work "./code/InputStage.vhd"
+add_file -vhdl -lib work "./code/WordAlign.vhd"
add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd"
add_file -vhdl -lib work "./trb5sc_mimosis.vhd"
-- FE_DIFF : inout std_logic_vector(63 downto 0);\r
--INP : inout std_logic_vector(63 downto 0);\r
LED_ADDON : out std_logic_vector(5 downto 0);\r
- LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
- LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
+-- LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
+-- LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
\r
attribute syn_keep : boolean;\r
attribute syn_preserve : boolean;\r
\r
- signal clk_sys, clk_full, clk_full_osc, clk_160 : std_logic;\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320 : std_logic;\r
signal GSR_N : std_logic;\r
signal reset_i : std_logic;\r
signal clear_i : std_logic;\r
signal readout_rx : READOUT_RX;\r
signal readout_tx : readout_tx_array_t(0 to 0);\r
\r
- signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;\r
- signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx : CTRLBUS_RX;\r
\r
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
signal timer : TIMERS;\r
signal add_reg : std_logic_vector(31 downto 0); \r
\r
- \r
- \r
- signal clk_rx : std_logic;\r
- signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0');\r
- signal data_i : std_logic_vector(15 downto 0);\r
- signal inp_i : std_logic_vector(7 downto 0);\r
- \r
- signal out_data : std_logic_vector(15 downto 0);\r
- signal out_i : std_logic_vector( 7 downto 0); \r
- \r
- type state_t is (START, LISTEN, STEP, CALC, SET1, SET2, ENDWAIT);\r
- type state_arrt is array (0 to 7) of state_t;\r
- \r
- type unsigned_arr is array(0 to 7) of unsigned(6 downto 0);\r
- signal sample_good, sample_bad : unsigned_arr := (others => (others => '0'));\r
- signal first_good, first_bad : unsigned_arr := (others => (others => '1'));\r
- signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0'));\r
- \r
+ signal out_data : std_logic_vector(15 downto 0);\r
+ signal out_i : std_logic_vector( 7 downto 0);\r
+ signal inp_i : std_logic_vector( 7 downto 0);\r
+ signal dummy : std_logic_vector( 1 downto 0);\r
\r
begin\r
\r
THE_160_PLL : entity work.pll_200_160\r
port map(\r
CLKI => clk_full_osc,\r
- CLKOP => clk_160\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320\r
);\r
\r
-\r
+H5(3) <= clk_320;\r
\r
---------------------------------------------------------------------------\r
-- TrbNet Uplink\r
\r
THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
generic map(\r
- SERDES_NUM => 0,\r
+ SERDES_NUM => SERDES_NUM,\r
IS_SYNC_SLAVE => c_YES\r
)\r
port map(\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
PORT_NUMBER => 4,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 5 => x"c000", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 12, others => 0),\r
PORT_MASK_ENABLE => 1\r
)\r
port map(\r
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
BUS_RX(1) => bussci_rx, --SCI Serdes\r
BUS_RX(2) => bustc_rx, --Clock switch\r
- BUS_RX(3) => bustdc_rx,\r
+ BUS_RX(3) => busmimosis_rx,\r
+-- BUS_RX(4) => bustdc_rx,\r
BUS_TX(0) => bustools_tx,\r
BUS_TX(1) => bussci_tx,\r
BUS_TX(2) => bustc_tx,\r
- BUS_TX(3) => bustdc_tx,\r
-\r
+ BUS_TX(3) => busmimosis_tx,\r
+-- BUS_TX(4) => bustdc_tx,\r
STAT_DEBUG => open\r
);\r
\r
when 3 => out_data <= x"0000";\r
when 4 => out_data <= x"5555";\r
when 5 => out_data <= x"5555";\r
- when 6 => out_data <= x"5555";\r
- when 7 => out_data <= x"5555";\r
+ when 6 => out_data <= x"5555";--sdummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
+ when 7 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
end case;\r
end process; \r
\r
- \r
----------------------------------------------------------------------------\r
--- Input stage\r
----------------------------------------------------------------------------\r
- \r
- \r
- THE_IN : entity work.mimosis_inp\r
- port map (\r
- clkin=>clk_160, \r
- reset=>reset_i, \r
- sclk=>clk_rx, \r
- data_cflag(7 downto 0)=>s_cflag, \r
- data_direction(7 downto 0)=>(others => '0'), \r
- data_loadn(7 downto 0)=>s_loadn, \r
- data_move(7 downto 0)=>s_move, \r
- datain(7 downto 0)=>inp_i, \r
- q(15 downto 0)=>data_i\r
- );\r
-\r
- HDR_IO <= data_i;\r
-\r
- \r
H3(3 downto 0) <= out_i(3 downto 0);\r
H4(3 downto 0) <= out_i(7 downto 4);\r
\r
- inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
-\r
--- s_move <= add_reg(7 downto 0);\r
-\r
-\r
-gen_finders : for i in 0 to 7 generate \r
- signal timer : unsigned(14 downto 0);\r
- signal state : state_t;\r
- signal count : unsigned(11 downto 0);\r
- signal pos : unsigned(6 downto 0);\r
- signal lastsample : std_logic;\r
- signal train : unsigned(3 downto 0);\r
- signal last : std_logic_vector(1 downto 0);\r
\r
-begin \r
- PROC_FIND : process begin\r
+ process begin\r
wait until rising_edge(clk_160);\r
- s_loadn(i) <= not add_reg(i+16);\r
-\r
- case state is\r
- when START =>\r
- timer <= 0;\r
- count <= 0;\r
- s_move(i) <= '0';\r
- state <= LISTEN;\r
- \r
- when LISTEN =>\r
- if timer(timer'left) = '1' then\r
- state <= STEP;\r
- if count >= 2047 and count <= 2049 then\r
- sample_good(i) <= sample_good(i) + 1;\r
- lastsample <= '1';\r
- if first_good(i) > pos then\r
- first_good(i) <= pos;\r
- end if;\r
- if last_bad(i) < pos and lastsample = '0' then\r
- last_bad(i) <= pos;\r
- end if;\r
- \r
- else\r
- lastsample <= '0';\r
- sample_bad(i) <= sample_bad(i) + 1; \r
- if first_bad(i) > pos then\r
- first_bad(i) <= pos;\r
- end if;\r
- if last_good(i) < pos and lastsample = '1' then\r
- last_good(i) <= pos;\r
- end if; \r
- end if;\r
- else \r
- timer <= timer + 1;\r
- end if;\r
- \r
- last <= data_i(i*2+1 downto i*2);\r
- \r
- if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and \r
- data_i(i*2+1 downto i*2) = last then\r
- train <= train + 1;\r
- else\r
- train <= x"0";\r
- end if;\r
- \r
- if train = x"3" then\r
- count <= count + 1;\r
- end if;\r
+ if add_reg(31) = '0' then\r
+ dummy <= "01";\r
+ else\r
+ dummy <= not dummy;\r
+ end if;\r
+ end process;\r
+ \r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ THE_MIMOSIS : entity work.MimosisInput\r
+ port map(\r
+ CLK => clk_160,\r
+ CLK_SYS => clk_sys,\r
+ RESET => reset_i,\r
\r
- \r
- when STEP =>\r
- if s_cflag(i) = '0' then\r
- s_move(i) <= '1';\r
- pos <= pos + 1;\r
- state <= START;\r
- else\r
- state <= CALC;\r
- s_loadn(i) <= '1'; \r
- end if; \r
- \r
- when CALC =>\r
- pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";\r
- posi(i) <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";\r
- state <= SET1;\r
- \r
- when SET1 =>\r
- state <= SET2;\r
- s_move(i) <= '1';\r
+ INPUT => inp_i,\r
\r
- when SET2 =>\r
- s_move(i) <= '0';\r
- if pos = 0 then\r
- state <= ENDWAIT;\r
- else \r
- state <= SET1;\r
- pos <= pos - 1;\r
- end if; \r
- \r
- when ENDWAIT =>\r
-\r
- state <= ENDWAIT;\r
+ BUSRDO_RX => readout_rx,\r
+ BUSRDO_TX => readout_tx(0),\r
\r
- end case;\r
- \r
- if reset_i = '1' or add_reg(0) = '1' then\r
- state <= START;\r
- pos <= 0;\r
- sample_good(i) <= 0;\r
- sample_bad(i) <= 0;\r
- last_good(i) <= 0;\r
- last_bad(i) <= 0;\r
- first_good(i) <= (others => '1'); \r
- first_bad(i) <= (others => '1'); \r
- end if;\r
- end process;\r
-end generate; \r
+ BUS_RX => busmimosis_rx,\r
+ BUS_TX => busmimosis_tx\r
+ );\r
\r
-PROC_REGS : process \r
- variable addr : integer range 0 to 7;\r
-begin\r
- wait until rising_edge(clk_sys);\r
- bustdc_tx.ack <= '0';\r
- bustdc_tx.unknown <= '0';\r
- bustdc_tx.nack <= '0';\r
- bustdc_tx.data <= (others => '0');\r
- addr := to_integer(unsigned(bustdc_rx.addr(2 downto 0)));\r
- \r
- if bustdc_rx.read = '1' then\r
- bustdc_tx.ack <= '1';\r
- if bustdc_rx.addr(15 downto 4) = x"000" then\r
- if bustdc_rx.addr(3) = '0' then\r
- bustdc_tx.data(6 downto 0) <= std_logic_vector(sample_good(addr));\r
- bustdc_tx.data(14 downto 8) <= std_logic_vector(sample_bad(addr));\r
- bustdc_tx.data(16) <= s_cflag(addr);\r
- bustdc_tx.data(30 downto 24)<= std_logic_vector(posi(addr));\r
- else\r
- bustdc_tx.data(6 downto 0) <= std_logic_vector(first_good(addr));\r
- bustdc_tx.data(14 downto 8) <= std_logic_vector(last_good(addr));\r
- bustdc_tx.data(22 downto 16) <= std_logic_vector(first_bad(addr));\r
- bustdc_tx.data(30 downto 24) <= std_logic_vector(last_bad(addr));\r
- end if;\r
- else\r
- bustdc_tx.ack <= '0';\r
- bustdc_tx.unknown <= '1';\r
- \r
- end if;\r
- end if;\r
-end process;\r
+ inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
\r
-------------------------------------------------------------------------------\r
-- No trigger/data endpoint included\r
-------------------------------------------------------------------------------\r
-readout_tx(0).data_finished <= '1';\r
-readout_tx(0).data_write <= '0';\r
-readout_tx(0).busy_release <= '1'; \r
+-- readout_tx(0).data_finished <= '1';\r
+-- readout_tx(0).data_write <= '0';\r
+-- readout_tx(0).busy_release <= '1'; \r
\r
\r
end architecture;\r
# LOCATE COMP "FE_DIFF[29]" SITE "J29" ; #was "FE_DIFF[29]"
LOCATE COMP "H2[0]" SITE "H27" ; #was "FE_DIFF[30]"
# LOCATE COMP "FE_DIFF[31]" SITE "K27" ; #was "FE_DIFF[31]"
-LOCATE COMP "H3[4]" SITE "D4" ; #was "FE_DIFF[32]"
-LOCATE COMP "H3[3]" SITE "B1" ; #was "FE_DIFF[34]"
+LOCATE COMP "H3[3]" SITE "D4" ; #was "FE_DIFF[32]"
+LOCATE COMP "H3[4]" SITE "B1" ; #was "FE_DIFF[34]"
LOCATE COMP "H3[2]" SITE "F3" ; #was "FE_DIFF[36]"
LOCATE COMP "H3[1]" SITE "F2" ; #was "FE_DIFF[38]"
LOCATE COMP "H3[0]" SITE "H2" ; #was "FE_DIFF[40]"
jspc29 / trb5sc.git / commitdiff