-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
-- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 8 -depth 256 -rdata_width 32 -regout -no_enable -pe 0 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 32 -depth 64 -rdata_width 32 -regout -pe 0 -pf -1 -e
--- Sat Mar 30 18:53:35 2013
+-- Sun Apr 7 20:23:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use ecp3.components.all;
-- synopsys translate_on
-entity fifo_dc_8to32_dyn is
+entity fifo_32to32_dc is
port (
- Data: in std_logic_vector(7 downto 0);
+ Data: in std_logic_vector(31 downto 0);
WrClock: in std_logic;
RdClock: in std_logic;
WrEn: in std_logic;
Empty: out std_logic;
Full: out std_logic;
AlmostEmpty: out std_logic);
-end fifo_dc_8to32_dyn;
+end fifo_32to32_dc;
-architecture Structure of fifo_dc_8to32_dyn is
+architecture Structure of fifo_32to32_dc is
-- internal signal declarations
signal invout_1: std_logic;
signal invout_0: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
signal rcnt_reg_5_inv: std_logic;
signal w_gdata_0: std_logic;
signal w_gdata_1: std_logic;
signal w_gdata_3: std_logic;
signal w_gdata_4: std_logic;
signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
signal wptr_0: std_logic;
signal wptr_1: std_logic;
signal wptr_2: std_logic;
signal wptr_4: std_logic;
signal wptr_5: std_logic;
signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
signal r_gdata_0: std_logic;
signal r_gdata_1: std_logic;
signal r_gdata_2: std_logic;
signal rptr_4: std_logic;
signal rptr_5: std_logic;
signal rptr_6: std_logic;
+ signal ffidata_0: std_logic;
+ signal ffidata_1: std_logic;
+ signal ffidata_2: std_logic;
+ signal ffidata_3: std_logic;
+ signal ffidata_4: std_logic;
+ signal ffidata_5: std_logic;
+ signal ffidata_6: std_logic;
+ signal ffidata_7: std_logic;
+ signal ffidata_8: std_logic;
+ signal ffidata_9: std_logic;
+ signal ffidata_10: std_logic;
+ signal ffidata_11: std_logic;
+ signal ffidata_12: std_logic;
+ signal ffidata_13: std_logic;
+ signal ffidata_14: std_logic;
+ signal ffidata_15: std_logic;
+ signal ffidata_16: std_logic;
+ signal ffidata_17: std_logic;
+ signal ffidata_18: std_logic;
+ signal ffidata_19: std_logic;
+ signal ffidata_20: std_logic;
+ signal ffidata_21: std_logic;
+ signal ffidata_22: std_logic;
+ signal ffidata_23: std_logic;
+ signal ffidata_24: std_logic;
+ signal ffidata_25: std_logic;
+ signal ffidata_26: std_logic;
+ signal ffidata_27: std_logic;
+ signal ffidata_28: std_logic;
+ signal ffidata_29: std_logic;
+ signal ffidata_30: std_logic;
+ signal ffidata_31: std_logic;
signal w_gcount_0: std_logic;
signal w_gcount_1: std_logic;
signal w_gcount_2: std_logic;
signal w_gcount_4: std_logic;
signal w_gcount_5: std_logic;
signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
signal r_gcount_0: std_logic;
signal r_gcount_1: std_logic;
signal r_gcount_2: std_logic;
signal w_gcount_r5: std_logic;
signal w_gcount_r26: std_logic;
signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
signal r_gcount_w20: std_logic;
signal r_gcount_w0: std_logic;
signal r_gcount_w21: std_logic;
signal iwcount_5: std_logic;
signal co1: std_logic;
signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal co4: std_logic;
- signal wcount_8: std_logic;
signal co3: std_logic;
+ signal wcount_6: std_logic;
+ signal co2: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_gctr_ci: std_logic;
signal co3_2d: std_logic;
signal co3_2: std_logic;
signal cmp_ci: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
signal rcount_0: std_logic;
signal rcount_1: std_logic;
signal co0_3: std_logic;
- signal wcount_r4: std_logic;
+ signal wcount_r2: std_logic;
signal w_g2b_xor_cluster_0: std_logic;
signal rcount_2: std_logic;
signal rcount_3: std_logic;
signal co1_3: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
signal rcount_4: std_logic;
signal rcount_5: std_logic;
signal co2_3: std_logic;
signal empty_d_c: std_logic;
signal wren_i: std_logic;
signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
signal wcount_0: std_logic;
signal wcount_1: std_logic;
signal co0_4: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
+ signal rcount_w2: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
signal wcount_2: std_logic;
signal wcount_3: std_logic;
signal co1_4: std_logic;
- signal rcount_w2: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
signal wcount_4: std_logic;
signal wcount_5: std_logic;
signal co2_4: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
signal full_cmp_clr: std_logic;
signal full_cmp_set: std_logic;
signal full_d: std_logic;
component XOR2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
end component;
attribute MEM_LPC_FILE : string;
attribute MEM_INIT_FILE : string;
attribute RESETMODE : string;
attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_dc_8to32_dyn.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_dc_8to32_dyn.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32to32_dc.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
attribute GSR of FF_89 : label is "ENABLED";
attribute GSR of FF_88 : label is "ENABLED";
attribute GSR of FF_87 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t19: AND2
+ AND2_t17: AND2
port map (A=>WrEn, B=>invout_1, Z=>wren_i);
INV_2: INV
port map (A=>full_i, Z=>invout_1);
- AND2_t18: AND2
+ AND2_t16: AND2
port map (A=>RdEn, B=>invout_0, Z=>rden_i);
INV_1: INV
port map (A=>empty_i, Z=>invout_0);
- OR2_t17: OR2
+ OR2_t15: OR2
port map (A=>Reset, B=>RPReset, Z=>rRst);
- XOR2_t16: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t15: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
XOR2_t14: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
XOR2_t13: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
XOR2_t12: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
XOR2_t11: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
XOR2_t10: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
XOR2_t9: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
XOR2_t8: XOR2
port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
XOR2_t3: XOR2
port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r7);
-
LUT4_15: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6);
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_gcount_r26,
+ DO0=>w_g2b_xor_cluster_0);
LUT4_14: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r5);
LUT4_13: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3);
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4);
LUT4_12: ROM16X1A
generic map (initval=> X"6996")
port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2);
+ AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2);
LUT4_11: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1);
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
LUT4_10: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0);
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0);
LUT4_9: ROM16X1A
generic map (initval=> X"6996")
AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0);
XOR2_t2: XOR2
- port map (A=>w_gcount_r28, B=>rcount_6, Z=>rcnt_sub_msb);
+ port map (A=>w_gcount_r26, B=>rcount_6, Z=>rcnt_sub_msb);
LUT4_3: ROM16X1A
generic map (initval=> X"0410")
- port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28,
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26,
AD0=>scuba_vlo, DO0=>empty_cmp_set);
LUT4_2: ROM16X1A
generic map (initval=> X"1004")
- port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28,
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26,
AD0=>scuba_vlo, DO0=>empty_cmp_clr);
LUT4_1: ROM16X1A
generic map (initval=> X"0140")
- port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26,
+ port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26,
AD0=>scuba_vlo, DO0=>full_cmp_set);
LUT4_0: ROM16X1A
generic map (initval=> X"4001")
- port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26,
+ port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26,
AD0=>scuba_vlo, DO0=>full_cmp_clr);
INV_0: INV
AND2_t0: AND2
port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig);
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo,
- ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
- ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
- ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(8), DOB5=>Q(9),
- DOB6=>Q(10), DOB7=>Q(11), DOB8=>open, DOB9=>Q(16),
- DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19), DOB13=>Q(24),
- DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27), DOB17=>open);
-
- pdp_ram_0_1_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo,
- ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
- ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
- ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(12), DOB5=>Q(13),
- DOB6=>Q(14), DOB7=>Q(15), DOB8=>open, DOB9=>Q(20),
- DOB10=>Q(21), DOB11=>Q(22), DOB12=>Q(23), DOB13=>Q(28),
- DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31), DOB17=>open);
-
- FF_89: FD1P3BX
+ pdp_ram_0_0_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
+ ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>scuba_vlo, ADW7=>scuba_vlo,
+ ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi,
+ BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock,
+ CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
+ ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
+ ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo,
+ CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18,
+ DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21,
+ DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24,
+ DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27,
+ DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30,
+ DO13=>ffidata_31, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>ffidata_0, DO19=>ffidata_1,
+ DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4,
+ DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7,
+ DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10,
+ DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13,
+ DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16,
+ DO35=>ffidata_17);
+
+ FF_111: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
Q=>wcount_0);
- FF_88: FD1P3DX
+ FF_110: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_1);
- FF_87: FD1P3DX
+ FF_109: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_2);
- FF_86: FD1P3DX
+ FF_108: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_3);
- FF_85: FD1P3DX
+ FF_107: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_4);
- FF_84: FD1P3DX
+ FF_106: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_5);
- FF_83: FD1P3DX
+ FF_105: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_6);
- FF_82: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_81: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_80: FD1P3DX
+ FF_104: FD1P3DX
port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_0);
- FF_79: FD1P3DX
+ FF_103: FD1P3DX
port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_1);
- FF_78: FD1P3DX
+ FF_102: FD1P3DX
port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_2);
- FF_77: FD1P3DX
+ FF_101: FD1P3DX
port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_3);
- FF_76: FD1P3DX
+ FF_100: FD1P3DX
port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_4);
- FF_75: FD1P3DX
+ FF_99: FD1P3DX
port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_5);
- FF_74: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ FF_98: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_6);
- FF_73: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_72: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_71: FD1P3DX
+ FF_97: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_0);
- FF_70: FD1P3DX
+ FF_96: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_1);
- FF_69: FD1P3DX
+ FF_95: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_2);
- FF_68: FD1P3DX
+ FF_94: FD1P3DX
port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_3);
- FF_67: FD1P3DX
+ FF_93: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_4);
- FF_66: FD1P3DX
+ FF_92: FD1P3DX
port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_5);
- FF_65: FD1P3DX
+ FF_91: FD1P3DX
port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_6);
- FF_64: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_63: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_62: FD1P3BX
+ FF_90: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
Q=>rcount_0);
- FF_61: FD1P3DX
+ FF_89: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_1);
- FF_60: FD1P3DX
+ FF_88: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_2);
- FF_59: FD1P3DX
+ FF_87: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_3);
- FF_58: FD1P3DX
+ FF_86: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_4);
- FF_57: FD1P3DX
+ FF_85: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_5);
- FF_56: FD1P3DX
+ FF_84: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_6);
- FF_55: FD1P3DX
+ FF_83: FD1P3DX
port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_0);
- FF_54: FD1P3DX
+ FF_82: FD1P3DX
port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_1);
- FF_53: FD1P3DX
+ FF_81: FD1P3DX
port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_2);
- FF_52: FD1P3DX
+ FF_80: FD1P3DX
port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_3);
- FF_51: FD1P3DX
+ FF_79: FD1P3DX
port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_4);
- FF_50: FD1P3DX
+ FF_78: FD1P3DX
port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_5);
- FF_49: FD1P3DX
+ FF_77: FD1P3DX
port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_6);
- FF_48: FD1P3DX
+ FF_76: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_0);
- FF_47: FD1P3DX
+ FF_75: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_1);
- FF_46: FD1P3DX
+ FF_74: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_2);
- FF_45: FD1P3DX
+ FF_73: FD1P3DX
port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_3);
- FF_44: FD1P3DX
+ FF_72: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_4);
- FF_43: FD1P3DX
+ FF_71: FD1P3DX
port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_5);
- FF_42: FD1P3DX
+ FF_70: FD1P3DX
port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_6);
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+ FF_69: FD1P3DX
+ port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0));
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+ FF_68: FD1P3DX
+ port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1));
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+ FF_67: FD1P3DX
+ port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2));
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+ FF_66: FD1P3DX
+ port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3));
+
+ FF_65: FD1P3DX
+ port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4));
+
+ FF_64: FD1P3DX
+ port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5));
+
+ FF_63: FD1P3DX
+ port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6));
+
+ FF_62: FD1P3DX
+ port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7));
+
+ FF_61: FD1P3DX
+ port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8));
+
+ FF_60: FD1P3DX
+ port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9));
+
+ FF_59: FD1P3DX
+ port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_58: FD1P3DX
+ port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_57: FD1P3DX
+ port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_56: FD1P3DX
+ port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_55: FD1P3DX
+ port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_54: FD1P3DX
+ port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_53: FD1P3DX
+ port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_52: FD1P3DX
+ port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_51: FD1P3DX
+ port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(18));
+
+ FF_50: FD1P3DX
+ port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(19));
+
+ FF_49: FD1P3DX
+ port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(20));
+
+ FF_48: FD1P3DX
+ port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(21));
+
+ FF_47: FD1P3DX
+ port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(22));
+
+ FF_46: FD1P3DX
+ port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(23));
+
+ FF_45: FD1P3DX
+ port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(24));
+
+ FF_44: FD1P3DX
+ port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(25));
+
+ FF_43: FD1P3DX
+ port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(26));
+
+ FF_42: FD1P3DX
+ port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(27));
+
+ FF_41: FD1P3DX
+ port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(28));
+
+ FF_40: FD1P3DX
+ port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(29));
+
+ FF_39: FD1P3DX
+ port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(30));
+
+ FF_38: FD1P3DX
+ port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst,
+ Q=>Q(31));
FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
FF_32: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
FF_31: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
FF_30: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
FF_29: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
FF_28: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
FF_27: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
FF_26: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
FF_25: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_24: FD1S3DX
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_23: FD1S3DX
port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r20);
- FF_24: FD1S3DX
+ FF_22: FD1S3DX
port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r21);
- FF_23: FD1S3DX
+ FF_21: FD1S3DX
port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r22);
- FF_22: FD1S3DX
+ FF_20: FD1S3DX
port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r23);
- FF_21: FD1S3DX
+ FF_19: FD1S3DX
port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r24);
- FF_20: FD1S3DX
+ FF_18: FD1S3DX
port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r25);
- FF_19: FD1S3DX
+ FF_17: FD1S3DX
port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r26);
- FF_18: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
FF_16: FD1S3DX
port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
NC0=>iwcount_4, NC1=>iwcount_5);
w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4,
- NC0=>iwcount_8, NC1=>open);
+ port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3,
+ NC0=>iwcount_6, NC1=>open);
r_gctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
port map (Z=>scuba_vhi);
rcnt_0: FSUB2B
- port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo,
+ port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo,
B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
S1=>rcnt_sub_0);
rcnt_1: FSUB2B
- port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_1,
+ port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rcount_1,
B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1,
S1=>rcnt_sub_2);
rcnt_2: FSUB2B
- port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r6, B0=>rcount_3,
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r4, B0=>rcount_3,
B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3,
S1=>rcnt_sub_4);
rcnt_3: FSUB2B
- port map (A0=>wcount_r7, A1=>rcnt_sub_msb, B0=>rcount_5,
+ port map (A0=>wcount_r5, A1=>rcnt_sub_msb, B0=>rcount_5,
B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5,
S1=>rcnt_sub_6);
CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
- B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3);
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3);
empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co1_3, GE=>co2_3);
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
empty_cmp_3: AGEB2
port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
- B1=>rcount_w1, CI=>co0_4, GE=>co1_4);
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>r_g2b_xor_cluster_0, CI=>co0_4, GE=>co1_4);
full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
- B1=>r_g2b_xor_cluster_0, CI=>co1_4, GE=>co2_4);
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co2_4, GE=>co3_3);
-
- full_cmp_4: AGEB2
port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c);
+ B1=>scuba_vlo, CI=>co2_4, GE=>full_d_c);
a1: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
-- synopsys translate_off
library ecp3;
-configuration Structure_CON of fifo_dc_8to32_dyn is
+configuration Structure_CON of fifo_32to32_dc is
for Structure
for all:AGEB2 use entity ecp3.AGEB2(V); end for;
for all:AND2 use entity ecp3.AND2(V); end for;
for all:VHI use entity ecp3.VHI(V); end for;
for all:VLO use entity ecp3.VLO(V); end for;
for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
end for;
end Structure_CON;
use ieee.numeric_std.all;\r
\r
library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
use work.nxyter_components.all;\r
\r
entity nx_timestamp_fifo_read is\r
port(\r
CLK_IN : in std_logic;\r
RESET_IN : in std_logic;\r
- \r
+ \r
-- nXyter Timestamp Ports\r
NX_TIMESTAMP_CLK_IN : in std_logic;\r
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);\r
- NX_FRAME_CLOCK_OUT : out std_logic;\r
NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);\r
NX_NEW_TIMESTAMP_OUT : out std_logic;\r
- \r
+\r
-- Slave bus \r
SLV_READ_IN : in std_logic;\r
SLV_WRITE_IN : in std_logic;\r
-----------------------------------------------------------------------------\r
\r
-- FIFO Input Handler\r
+ signal nx_timestamp_reg_t : std_logic_vector(7 downto 0);\r
+ signal nx_timestamp_reg : std_logic_vector(7 downto 0);\r
signal fifo_full : std_logic;\r
- signal fifo_write_enable : std_logic;\r
- signal frame_tag_o : std_logic;\r
signal fifo_reset : std_logic;\r
\r
- -- FRAME_CLOCK_GENERATOR \r
- signal frame_clock_ctr : unsigned(1 downto 0);\r
- signal nx_frame_clock_o : std_logic;\r
+ -- NX_TIMESTAMP_IN Process\r
+ signal frame_byte_ctr : unsigned(1 downto 0);\r
+ signal fifo_32bit_word : std_logic_vector(31 downto 0);\r
+ signal nx_new_frame : std_logic;\r
+\r
+ -- Frame Sync Process \r
+ signal frame_byte_pos : unsigned(1 downto 0);\r
+\r
+ -- RS Sync FlipFlop\r
+ signal nx_frame_synced : std_logic;\r
+ signal rs_sync_set : std_logic;\r
+ signal rs_sync_reset : std_logic;\r
+\r
+ -- Parity Check\r
+ signal parity_error : std_logic;\r
+\r
+ -- Write to FIFO Handler\r
+ signal fifo_data_input : std_logic_vector(31 downto 0);\r
+ signal fifo_write_enable : std_logic;\r
\r
- signal frame_clock_ctr_inc_x : std_logic;\r
- signal frame_clock_ctr_inc_l : std_logic;\r
- signal frame_clock_ctr_inc : std_logic;\r
- \r
-----------------------------------------------------------------------------\r
-- CLK_IN Domain\r
-----------------------------------------------------------------------------\r
\r
+ -- PROC FIFO_READ\r
+ signal nx_new_timestamp_o : std_logic;\r
+ signal register_fifo_data : std_logic_vector(31 downto 0);\r
+\r
+ signal fifo_almost_empty_tt : std_logic;\r
+ signal fifo_almost_empty_t : std_logic;\r
+\r
+ \r
-- FIFO Output Handler\r
- signal fifo_out : std_logic_vector(35 downto 0);\r
+ signal fifo_out : std_logic_vector(31 downto 0);\r
signal fifo_empty : std_logic;\r
signal fifo_almost_empty : std_logic;\r
- signal fifo_almost_empty_prev : std_logic;\r
signal fifo_read_enable : std_logic;\r
- signal fifo_data_valid_x : std_logic;\r
+ signal fifo_data_valid_t : std_logic;\r
signal fifo_data_valid : std_logic;\r
- signal register_fifo_data : std_logic_vector(31 downto 0);\r
- signal fifo_new_frame : std_logic;\r
- \r
- signal frame_clock_ctr_inc_o : std_logic;\r
- \r
- -- RS Sync FlipFlop\r
- signal nx_frame_synced : std_logic;\r
-\r
- -- Frame Sync Process \r
- type STATES_SYNC is (S_SYNC_CHECK,\r
- S_SYNC_RESYNC,\r
- S_SYNC_WAIT\r
- );\r
+ signal read_enable_pause : std_logic;\r
\r
- signal STATE_SYNC : STATES_SYNC;\r
+ -- Resync Counter Process \r
+ signal resync_counter : unsigned(11 downto 0);\r
+ signal resync_ctr_inc : std_logic;\r
+ signal nx_clk_active : std_logic;\r
+ \r
+ -- Parity Error Counter Process \r
+ signal parity_error_counter : unsigned(11 downto 0);\r
+ signal parity_error_ctr_inc : std_logic;\r
\r
- signal rs_sync_set : std_logic;\r
- signal rs_sync_reset : std_logic;\r
- signal frame_clock_ctr_inc_s : std_logic;\r
- signal frame_sync_wait_ctr : unsigned(7 downto 0);\r
- signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
- signal frame_sync_wait_done : std_logic;\r
+ signal reg_nx_frame_synced_t : std_logic;\r
+ signal reg_nx_frame_synced : std_logic;\r
\r
-- Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
signal slv_unknown_addr_o : std_logic;\r
signal slv_ack_o : std_logic;\r
\r
- signal reset_ctr : std_logic;\r
- signal frame_clock_ctr_inc_r : std_logic;\r
+ signal reset_resync_ctr : std_logic;\r
+ signal reset_parity_error_ctr : std_logic;\r
signal fifo_delay_r : std_logic_vector(5 downto 0);\r
signal fifo_reset_r : std_logic;\r
- \r
- signal pll_lock : std_logic;\r
- signal nx_clk_in_delayed : std_logic;\r
- signal nx_timestamp_reg : std_logic_vector(7 downto 0);\r
- \r
+\r
begin\r
\r
- DEBUG_OUT(0) <= '0';\r
- DEBUG_OUT(1) <= '0';\r
- DEBUG_OUT(2) <= fifo_empty;\r
- DEBUG_OUT(3) <= fifo_read_enable;\r
- DEBUG_OUT(4) <= fifo_data_valid;\r
- DEBUG_OUT(5) <= fifo_new_frame;\r
- DEBUG_OUT(6) <= NX_NEW_TIMESTAMP_OUT;\r
- DEBUG_OUT(7) <= fifo_almost_empty;\r
- DEBUG_OUT(15 downto 8) <= (others => '0');\r
- \r
--- DEBUG_OUT(0) <= CLK_IN;\r
--- \r
--- DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;\r
--- DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT;\r
--- DEBUG_OUT(3) <= NX_FRAME_SYNC_OUT;\r
--- -- DEBUG_OUT(4) <= NX_NEW_FRAME_OUT;\r
--- -- DEBUG_OUT(5) <= frame_clock_ctr_inc_o;\r
--- -- DEBUG_OUT(6) <= frame_tag_o;\r
--- -- DEBUG_OUT(7) <= '0';\r
--- DEBUG_OUT(7 downto 4) <= fifo_out(3 downto 0);\r
--- DEBUG_OUT(15 downto 8) <= fifo_out(34 downto 27);\r
- \r
- THE_INPUT_PLL : entity work.nxyter_input_pll\r
- port map(\r
- CLK => NX_TIMESTAMP_CLK_IN,\r
- CLKFB => nx_clk_in_delayed,\r
- CLKOP => nx_clk_in_delayed,\r
- LOCK => pll_lock --use this to generate FIFO reset!\r
- );\r
- \r
- nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(nx_clk_in_delayed);\r
+ DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN;\r
+ DEBUG_OUT(1) <= parity_error;\r
+ DEBUG_OUT(2) <= nx_new_frame;\r
+ DEBUG_OUT(3) <= rs_sync_set;\r
+ DEBUG_OUT(4) <= rs_sync_reset;\r
+ DEBUG_OUT(5) <= nx_frame_synced;\r
+ DEBUG_OUT(7 downto 6) <= frame_byte_pos;\r
+\r
+ DEBUG_OUT(8) <= fifo_write_enable;\r
+ DEBUG_OUT(9) <= fifo_read_enable;\r
+ DEBUG_OUT(10) <= nx_new_timestamp_o;\r
+ DEBUG_OUT(11) <= fifo_data_valid;\r
+ DEBUG_OUT(12) <= nx_clk_active;\r
+ DEBUG_OUT(13) <= resync_ctr_inc;\r
+ DEBUG_OUT(14) <= parity_error_ctr_inc;\r
+ DEBUG_OUT(15) <= reg_nx_frame_synced;\r
\r
- -----------------------------------------------------------------------------\r
- -- Dual Clock FIFO 9bit to 36bit\r
- -----------------------------------------------------------------------------\r
\r
- -- Send data to FIFO, depth is 256\r
- fifo_dc_9to36_dyn_1: fifo_dc_9to36_dyn\r
- port map (\r
- Data(7 downto 0) => nx_timestamp_reg,\r
- Data(8) => frame_tag_o,\r
- WrClock => nx_clk_in_delayed,\r
- RdClock => CLK_IN,\r
- WrEn => fifo_write_enable,\r
- RdEn => fifo_read_enable,\r
- Reset => fifo_reset,\r
- RPReset => fifo_reset,\r
- AmEmptyThresh => fifo_delay_r,\r
- Q => fifo_out,\r
- Empty => fifo_empty,\r
- Full => fifo_full,\r
- AlmostEmpty => fifo_almost_empty\r
- );\r
\r
- fifo_write_enable <= not RESET_IN and pll_lock;\r
- fifo_reset <= (RESET_IN or fifo_reset_r) and not pll_lock;\r
+--DEBUG_OUT(15 downto 8) <= fifo_32bit_word(15 downto 8);\r
+\r
+\r
+-- DEBUG_OUT(6) <= nx_new_timestamp_o;\r
+-- DEBUG_OUT(7) <= fifo_almost_empty;\r
+-- DEBUG_OUT(8) <= nx_frame_synced;\r
+-- DEBUG_OUT(9) <= rs_sync_reset;\r
+-- DEBUG_OUT(11 downto 10) <= frame_tag_pos;\r
+-- DEBUG_OUT(12) <= fifo_full;\r
+-- DEBUG_OUT(15 downto 13) <= (others => '0');\r
+\r
+\r
+ --DEBUG_OUT(8 downto 1) <= fifo_out(7 downto 0); --nx_timestamp_reg_t when rising_edge(NX_TIMESTAMP_CLK_IN) ; \r
\r
-----------------------------------------------------------------------------\r
- -- FIFO Input Handler\r
+ -- NX_TIMESTAMP_CLK_IN Domain\r
-----------------------------------------------------------------------------\r
- \r
- -- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal\r
- -- frame_clock_ctr_inc\r
- PROC_FIFO_IN_HANDLER_SYNC: process(nx_clk_in_delayed)\r
+\r
+ nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN);\r
+\r
+ -- Transfer 8 to 32Bit \r
+ PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN)\r
begin\r
- if( rising_edge(nx_clk_in_delayed) ) then\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- frame_clock_ctr_inc_x <= '0';\r
- frame_clock_ctr_inc_l <= '0';\r
+ frame_byte_ctr <= (others => '0');\r
+ fifo_32bit_word <= (others => '0');\r
+ nx_new_frame <= '0';\r
else\r
- frame_clock_ctr_inc_x <= frame_clock_ctr_inc_o;\r
- frame_clock_ctr_inc_l <= frame_clock_ctr_inc_x; \r
+ nx_new_frame <= '0';\r
+ \r
+ case frame_byte_pos is\r
+ when "11" => fifo_32bit_word(31 downto 24) <= nx_timestamp_reg;\r
+ frame_byte_ctr <= frame_byte_ctr + 1;\r
+ \r
+ when "10" => fifo_32bit_word(23 downto 16) <= nx_timestamp_reg;\r
+ frame_byte_ctr <= frame_byte_ctr + 1;\r
+ \r
+ when "01" => fifo_32bit_word(15 downto 8) <= nx_timestamp_reg;\r
+ frame_byte_ctr <= frame_byte_ctr + 1;\r
+ \r
+ when "00" => fifo_32bit_word( 7 downto 0) <= nx_timestamp_reg;\r
+ if (frame_byte_ctr = "11") then\r
+ nx_new_frame <= '1';\r
+ end if;\r
+ frame_byte_ctr <= (others => '0'); \r
+ end case;\r
end if;\r
end if;\r
- end process PROC_FIFO_IN_HANDLER_SYNC;\r
-\r
- -- Signal frame_tag_ctr_inc_l might be 2 clocks long --> I need 1\r
- level_to_pulse_1: level_to_pulse\r
- port map (\r
- CLK_IN => nx_clk_in_delayed,\r
- RESET_IN => RESET_IN,\r
- LEVEL_IN => frame_clock_ctr_inc_l,\r
- PULSE_OUT => frame_clock_ctr_inc\r
- );\r
- \r
- PROC_FRAME_CLOCK_GENERATOR: process(nx_clk_in_delayed)\r
+ end process PROC_8_TO_32_BIT;\r
+ \r
+ -- Frame Sync process\r
+ PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN)\r
begin\r
- if( rising_edge(nx_clk_in_delayed) ) then\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- frame_clock_ctr <= (others => '0');\r
- nx_frame_clock_o <= '0';\r
- frame_tag_o <= '0';\r
+ frame_byte_pos <= "11";\r
+ rs_sync_set <= '0';\r
+ rs_sync_reset <= '0';\r
else\r
- case frame_clock_ctr is\r
-\r
- when "00" =>\r
- nx_frame_clock_o <= '0';\r
- frame_tag_o <= '1';\r
- when "01" =>\r
- nx_frame_clock_o <= '1';\r
- frame_tag_o <= '0';\r
- when "10" =>\r
- nx_frame_clock_o <= '1';\r
- frame_tag_o <= '0';\r
- when "11" =>\r
- nx_frame_clock_o <= '0';\r
- frame_tag_o <= '0';\r
- when others => null;\r
+ rs_sync_set <= '0';\r
+ rs_sync_reset <= '0';\r
+ if (nx_new_frame = '1') then\r
+ case fifo_32bit_word is\r
+ when x"7f7f7f06" =>\r
+ rs_sync_set <= '1'; \r
+ frame_byte_pos <= frame_byte_pos - 1;\r
+ \r
+ when x"7f7f067f" =>\r
+ rs_sync_reset <= '1';\r
+ frame_byte_pos <= frame_byte_pos - 2;\r
+ \r
+ when x"7f067f7f" =>\r
+ rs_sync_reset <= '1';\r
+ frame_byte_pos <= frame_byte_pos - 3;\r
+ \r
+ when x"067f7f7f" =>\r
+ rs_sync_reset <= '1'; \r
+ frame_byte_pos <= frame_byte_pos - 4;\r
+ \r
+ when others =>\r
+ frame_byte_pos <= frame_byte_pos - 1;\r
+ end case;\r
+ else\r
+ frame_byte_pos <= frame_byte_pos - 1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_SYNC_TO_NX_FRAME;\r
\r
- end case;\r
+ -- RS FlipFlop to hold Sync Status\r
+ PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN)\r
+ begin\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+ if (RESET_IN = '1' or rs_sync_reset = '1') then\r
+ nx_frame_synced <= '0';\r
+ elsif (rs_sync_set = '1') then\r
+ nx_frame_synced <= '1';\r
+ end if;\r
+ end if;\r
+ end process PROC_RS_FRAME_SYNCED;\r
\r
- if (frame_clock_ctr_inc = '1') then\r
- frame_clock_ctr <= frame_clock_ctr + 2;\r
- else\r
- frame_clock_ctr <= frame_clock_ctr + 1;\r
+ -- Check Parity\r
+ PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN)\r
+ variable parity_bits : std_logic_vector(22 downto 0);\r
+ variable parity : std_logic;\r
+ begin\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+ if (RESET_IN = '1') then\r
+ parity_error <= '0';\r
+ else\r
+ parity_error <= '0';\r
+ if (nx_new_frame = '1' and nx_frame_synced = '1') then\r
+ -- Timestamp Bit #6 is excluded (funny nxyter-bug)\r
+ parity_bits := fifo_32bit_word(31 downto 24) &\r
+ fifo_32bit_word(21 downto 16) &\r
+ fifo_32bit_word(14 downto 8) &\r
+ fifo_32bit_word( 2 downto 1);\r
+ parity := xor_all(parity_bits);\r
+\r
+ if (parity /= fifo_32bit_word(0)) then\r
+ parity_error <= '1';\r
+ end if;\r
end if;\r
- \r
end if;\r
end if;\r
- end process PROC_FRAME_CLOCK_GENERATOR;\r
+ end process PROC_PARITY_CHECK;\r
\r
- \r
+ -- Write to FIFO\r
+ PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN)\r
+ begin\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+ if (RESET_IN = '1') then\r
+ fifo_data_input <= (others => '0');\r
+ fifo_write_enable <= '0';\r
+ else\r
+ fifo_data_input <= x"deadbeef";\r
+ fifo_write_enable <= '0';\r
+ if (nx_new_frame = '1' and nx_frame_synced = '1') then\r
+ fifo_data_input <= fifo_32bit_word; \r
+ fifo_write_enable <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_WRITE_TO_FIFO;\r
+\r
+ fifo_32to32_dc_1: fifo_32to32_dc\r
+ port map (\r
+ Data => fifo_data_input,\r
+ WrClock => NX_TIMESTAMP_CLK_IN,\r
+ RdClock => CLK_IN,\r
+ WrEn => fifo_write_enable,\r
+ RdEn => fifo_read_enable,\r
+ Reset => fifo_reset,\r
+ RPReset => fifo_reset,\r
+ AmEmptyThresh => fifo_delay_r,\r
+ Q => fifo_out,\r
+ Empty => fifo_empty,\r
+ Full => fifo_full,\r
+ AlmostEmpty => fifo_almost_empty\r
+ );\r
+\r
+ fifo_reset <= (RESET_IN or fifo_reset_r);\r
+\r
+-- -- Reset NX_TIMESTAMP_CLK Domain\r
+-- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN)\r
+-- begin\r
+-- if( rising_edge(CLK_IN) ) then\r
+-- if( RESET_IN = '1' ) then\r
+-- reset_nx_domain_ctr <= (others => '0');\r
+-- reset_nx_domain <= '1';\r
+-- else\r
+-- if (nx_clk_pulse = '1') then\r
+-- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1;\r
+-- end if;\r
+-- \r
+-- end if;\r
+-- \r
+-- end if;\r
+-- end process PROC_NX_CLK_DOMAIN_RESET;\r
+\r
+ PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN)\r
+ begin\r
+ if(rising_edge(NX_TIMESTAMP_CLK_IN)) then\r
+ if(RESET_IN = '1' ) then\r
+ nx_clk_active <= '0';\r
+ else\r
+ nx_clk_active <= not nx_clk_active;\r
+ end if;\r
+ end if;\r
+ end process PROC_NX_CLK_ACT;\r
+ \r
-----------------------------------------------------------------------------\r
- -- FIFO Output Handler and Sync FIFO\r
+ -- CLK_IN Domain\r
-----------------------------------------------------------------------------\r
\r
+ -- FIFO Read Handler\r
PROC_FIFO_READ_ENABLE: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- fifo_almost_empty_prev <= '0';\r
fifo_read_enable <= '0';\r
- fifo_data_valid_x <= '0';\r
+ read_enable_pause <= '0';\r
+ fifo_data_valid_t <= '0';\r
fifo_data_valid <= '0';\r
else\r
- if (fifo_almost_empty = '0' and fifo_almost_empty_prev = '1') then\r
+ if (fifo_almost_empty = '0' and read_enable_pause = '0') then\r
fifo_read_enable <= '1';\r
+ read_enable_pause <= '1';\r
else\r
fifo_read_enable <= '0';\r
-\r
+ read_enable_pause <= '0';\r
end if;\r
- fifo_almost_empty_prev <= fifo_almost_empty;\r
- fifo_data_valid_x <= fifo_read_enable;\r
- fifo_data_valid <= fifo_data_valid_x;\r
+\r
+ -- Delay read signal by one CLK\r
+ fifo_data_valid_t <= fifo_read_enable;\r
+ fifo_data_valid <= fifo_data_valid_t;\r
+\r
end if;\r
end if;\r
end process PROC_FIFO_READ_ENABLE;\r
- \r
- -- Read only in case FIFO is not empty, i.e. data_valid is set\r
\r
PROC_FIFO_READ: process(CLK_IN)\r
-\r
- variable frame_tag : std_logic_vector(3 downto 0);\r
-\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1') then\r
- fifo_new_frame <= '0';\r
+ nx_new_timestamp_o <= '0';\r
register_fifo_data <= (others => '0');\r
else\r
- frame_tag := fifo_out( 8) & fifo_out(17) &\r
- fifo_out(26) & fifo_out(35);\r
- fifo_new_frame <= '0';\r
- register_fifo_data <= x"deadbeef";\r
-\r
+ nx_new_timestamp_o <= '0';\r
+ register_fifo_data <= x"affebabe";\r
+ \r
if (fifo_data_valid = '1') then\r
-\r
- case frame_tag is\r
-\r
- when "1000" =>\r
- register_fifo_data(31 downto 24) <= fifo_out( 7 downto 0);\r
- register_fifo_data(23 downto 16) <= fifo_out(16 downto 9);\r
- register_fifo_data(15 downto 8) <= fifo_out(25 downto 18);\r
- register_fifo_data( 7 downto 0) <= fifo_out(34 downto 27);\r
- fifo_new_frame <= '1'; \r
-\r
- when "0100" => \r
- register_fifo_data(31 downto 24) <= fifo_out(16 downto 9);\r
- register_fifo_data(23 downto 16) <= fifo_out(25 downto 18);\r
- register_fifo_data(15 downto 8) <= fifo_out(34 downto 27);\r
- register_fifo_data( 7 downto 0) <= fifo_out( 7 downto 0);\r
- fifo_new_frame <= '1'; \r
-\r
- when "0010" => \r
- register_fifo_data(31 downto 24) <= fifo_out(25 downto 18);\r
- register_fifo_data(23 downto 16) <= fifo_out(34 downto 27);\r
- register_fifo_data(15 downto 8) <= fifo_out( 7 downto 0);\r
- register_fifo_data( 7 downto 0) <= fifo_out(16 downto 9);\r
- fifo_new_frame <= '1'; \r
-\r
- when "0001" => \r
- register_fifo_data(31 downto 24) <= fifo_out(34 downto 27);\r
- register_fifo_data(23 downto 16) <= fifo_out( 7 downto 0);\r
- register_fifo_data(15 downto 8) <= fifo_out(16 downto 9);\r
- register_fifo_data( 7 downto 0) <= fifo_out(25 downto 18);\r
- fifo_new_frame <= '1'; \r
-\r
- when others => null;\r
- \r
- end case;\r
-\r
+ register_fifo_data <= fifo_out;\r
+ nx_new_timestamp_o <= '1';\r
end if;\r
end if;\r
end if;\r
end process PROC_FIFO_READ;\r
- \r
\r
-----------------------------------------------------------------------------\r
- -- Sync to NX_DATA FRAME\r
+ -- Status Counters\r
-----------------------------------------------------------------------------\r
- \r
- -- RS FlipFlop to hold Sync Status\r
- PROC_RS_FRAME_SYNCED: process(CLK_IN)\r
- begin\r
- if( rising_edge(CLK_IN) ) then\r
- if (RESET_IN = '1' or rs_sync_reset = '1') then\r
- nx_frame_synced <= '0';\r
- elsif (rs_sync_set = '1') then\r
- nx_frame_synced <= '1';\r
- end if;\r
- end if;\r
- end process PROC_RS_FRAME_SYNCED;\r
\r
- -- Frame Resync Timer_done Timer\r
- nx_timer_1: nx_timer\r
- generic map (\r
- CTR_WIDTH => 8\r
- )\r
+ -- Domain Transfers\r
+ pulse_sync_1: pulse_sync\r
port map (\r
- CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
- TIMER_START_IN => frame_sync_wait_ctr,\r
- TIMER_DONE_OUT => frame_sync_wait_done\r
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => rs_sync_reset,\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => resync_ctr_inc \r
);\r
\r
- -- Frame Sync process\r
- PROC_SYNC_TO_NX_FRAME: process(CLK_IN)\r
- \r
- variable fifo_tag_given : std_logic_vector(3 downto 0);\r
+ pulse_sync_2: pulse_sync\r
+ port map (\r
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => parity_error,\r
+ CLK_B_IN => CLK_IN,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => parity_error_ctr_inc\r
+ );\r
\r
+ PROC_SYNC_FRAME_SYNC: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
- if( RESET_IN = '1' ) then\r
- rs_sync_set <= '0';\r
- rs_sync_reset <= '1';\r
- frame_clock_ctr_inc_s <= '0';\r
- nx_frame_resync_ctr <= (others => '0');\r
- frame_sync_wait_ctr <= (others => '0');\r
- STATE_SYNC <= S_SYNC_CHECK;\r
+ if(RESET_IN = '1' ) then\r
+ reg_nx_frame_synced_t <= '0';\r
+ reg_nx_frame_synced <= '0';\r
else\r
- rs_sync_set <= '0';\r
- rs_sync_reset <= '0';\r
- frame_clock_ctr_inc_s <= '0';\r
- nx_frame_resync_ctr <= nx_frame_resync_ctr;\r
- frame_sync_wait_ctr <= (others => '0');\r
-\r
- fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
- fifo_out(17) & fifo_out(8);\r
-\r
- case STATE_SYNC is\r
- when S_SYNC_CHECK =>\r
- if (fifo_new_frame = '1') then \r
- case register_fifo_data is\r
- when x"7f7f7f06" =>\r
- rs_sync_set <= '1';\r
- STATE_SYNC <= S_SYNC_CHECK;\r
-\r
- when x"067f7f7f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when x"7f067f7f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when x"7f7f067f" =>\r
- STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when others =>\r
- STATE_SYNC <= S_SYNC_CHECK;\r
- \r
- end case;\r
- else\r
- STATE_SYNC <= S_SYNC_CHECK;\r
- end if;\r
-\r
- when S_SYNC_RESYNC =>\r
- rs_sync_reset <= '1';\r
- frame_clock_ctr_inc_s <= '1';\r
- if (reset_ctr = '0') then\r
- nx_frame_resync_ctr <= nx_frame_resync_ctr + 1; \r
- end if;\r
-\r
- frame_sync_wait_ctr <= x"14";\r
- STATE_SYNC <= S_SYNC_WAIT;\r
-\r
- when S_SYNC_WAIT =>\r
- if (frame_sync_wait_done = '0') then\r
- STATE_SYNC <= S_SYNC_WAIT;\r
- else\r
- STATE_SYNC <= S_SYNC_CHECK;\r
- end if;\r
- \r
- end case;\r
- \r
- if (reset_ctr = '1') then\r
- nx_frame_resync_ctr <= (others => '0'); \r
+ reg_nx_frame_synced_t <= nx_frame_synced;\r
+ reg_nx_frame_synced <= reg_nx_frame_synced_t; \r
+ end if;\r
+ end if;\r
+ end process PROC_SYNC_FRAME_SYNC;\r
+\r
+ -- Counters\r
+ PROC_RESYNC_COUNTER: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if (RESET_IN = '1' or reset_resync_ctr = '1') then\r
+ resync_counter <= (others => '0');\r
+ else\r
+ if (resync_ctr_inc = '1') then\r
+ resync_counter <= resync_counter + 1;\r
end if;\r
end if;\r
end if;\r
- end process PROC_SYNC_TO_NX_FRAME;\r
+ end process PROC_RESYNC_COUNTER; \r
\r
+ PROC_PARITY_ERROR_COUNTER: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if (RESET_IN = '1' or reset_parity_error_ctr = '1') then\r
+ parity_error_counter <= (others => '0');\r
+ else\r
+ if (parity_error_ctr_inc = '1') then\r
+ parity_error_counter <= parity_error_counter + 1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_PARITY_ERROR_COUNTER;\r
+ \r
-----------------------------------------------------------------------------\r
-- TRBNet Slave Bus\r
-----------------------------------------------------------------------------\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- slv_data_out_o <= (others => '0');\r
- slv_ack_o <= '0';\r
- slv_unknown_addr_o <= '0';\r
- slv_no_more_data_o <= '0';\r
- frame_clock_ctr_inc_r <= '0';\r
- reset_ctr <= '0';\r
- fifo_delay_r <= "000010";\r
- fifo_reset_r <= '0';\r
- else\r
- slv_data_out_o <= (others => '0');\r
- slv_ack_o <= '0';\r
- slv_unknown_addr_o <= '0';\r
- slv_no_more_data_o <= '0';\r
- frame_clock_ctr_inc_r <= '0';\r
- reset_ctr <= '0';\r
- fifo_reset_r <= '0';\r
-\r
+ slv_data_out_o <= (others => '0');\r
+ slv_ack_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ reset_resync_ctr <= '0';\r
+ reset_parity_error_ctr <= '0';\r
+ fifo_delay_r <= "000010";\r
+ fifo_reset_r <= '0';\r
+ else \r
+ slv_data_out_o <= (others => '0');\r
+ slv_ack_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ reset_resync_ctr <= '0';\r
+ reset_parity_error_ctr <= '0';\r
+ fifo_reset_r <= '0';\r
+ \r
if (SLV_READ_IN = '1') then\r
case SLV_ADDR_IN is\r
when x"0000" =>\r
when x"0001" =>\r
slv_data_out_o(0) <= fifo_full;\r
slv_data_out_o(1) <= fifo_empty;\r
- slv_data_out_o(3 downto 2) <= (others => '0');\r
+ slv_data_out_o(2) <= fifo_almost_empty;\r
+ slv_data_out_o(3) <= '0';\r
slv_data_out_o(4) <= fifo_data_valid;\r
- slv_data_out_o(5) <= fifo_new_frame;\r
- slv_data_out_o(30 downto 6) <= (others => '0');\r
- slv_data_out_o(31) <= nx_frame_synced;\r
+ slv_data_out_o(29 downto 5) <= (others => '0');\r
+ slv_data_out_o(30) <= '0';\r
+ slv_data_out_o(31) <= reg_nx_frame_synced;\r
slv_ack_o <= '1'; \r
\r
when x"0002" =>\r
- slv_data_out_o(7 downto 0) <= nx_frame_resync_ctr;\r
- slv_data_out_o(31 downto 8) <= (others => '0');\r
+ slv_data_out_o(11 downto 0) <= resync_counter;\r
+ slv_data_out_o(31 downto 12) <= (others => '0');\r
slv_ack_o <= '1'; \r
\r
when x"0003" =>\r
- slv_data_out_o(5 downto 0) <= fifo_delay_r;\r
+ slv_data_out_o(11 downto 0) <= parity_error_counter;\r
+ slv_data_out_o(31 downto 12) <= (others => '0');\r
+ slv_ack_o <= '1'; \r
+\r
+ when x"0004" =>\r
+ slv_data_out_o( 5 downto 0) <= fifo_delay_r;\r
slv_data_out_o(31 downto 6) <= (others => '0');\r
slv_ack_o <= '1'; \r
- \r
+\r
when others =>\r
slv_unknown_addr_o <= '1';\r
end case;\r
\r
elsif (SLV_WRITE_IN = '1') then\r
case SLV_ADDR_IN is\r
- when x"0001" =>\r
- frame_clock_ctr_inc_r <= '1';\r
- slv_ack_o <= '1'; \r
-\r
when x"0002" => \r
- reset_ctr <= '1';\r
- slv_ack_o <= '1'; \r
- \r
+ reset_resync_ctr <= '1';\r
+ slv_ack_o <= '1'; \r
+\r
when x"0003" => \r
- if (SLV_DATA_IN < x"0000003c" and\r
- SLV_DATA_IN > x"00000001") then\r
- fifo_delay_r <= SLV_DATA_IN(5 downto 0);\r
- fifo_reset_r <= '1';\r
+ reset_parity_error_ctr <= '1';\r
+ slv_ack_o <= '1'; \r
+\r
+ when x"0004" => \r
+ if (SLV_DATA_IN < x"0000003c" and\r
+ SLV_DATA_IN > x"00000001") then\r
+ fifo_delay_r <= SLV_DATA_IN(5 downto 0);\r
+ fifo_reset_r <= '1';\r
end if;\r
- slv_ack_o <= '1';\r
+ slv_ack_o <= '1';\r
\r
when others =>\r
- slv_unknown_addr_o <= '1'; \r
+ slv_unknown_addr_o <= '1'; \r
end case; \r
end if;\r
end if;\r
end if;\r
end process PROC_FIFO_REGISTERS;\r
\r
- frame_clock_ctr_inc_o <= frame_clock_ctr_inc_r or frame_clock_ctr_inc_s;\r
- \r
-- Output Signals\r
+ NX_TIMESTAMP_OUT <= register_fifo_data;\r
+ NX_NEW_TIMESTAMP_OUT <= nx_new_timestamp_o;\r
+\r
SLV_DATA_OUT <= slv_data_out_o; \r
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
SLV_ACK_OUT <= slv_ack_o;\r
-\r
- NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
- NX_TIMESTAMP_OUT <= register_fifo_data;\r
- NX_NEW_TIMESTAMP_OUT <= fifo_new_frame and nx_frame_synced;\r
- \r
+ \r
end Behavioral;\r
jspc29 / trb3.git / commitdiff