]> jspc29.x-matter.uni-frankfurt.de Git - trb3sc.git/commitdiff
Update TRB3sc pulser design
authorJan Michel <j.michel@gsi.de>
Wed, 26 Jul 2017 16:23:52 +0000 (18:23 +0200)
committerJan Michel <j.michel@gsi.de>
Wed, 26 Jul 2017 16:28:09 +0000 (18:28 +0200)
pulser/config.vhd
pulser/config_compile_frankfurt.pl
pulser/trb3sc_pulser.prj

index 999ee039c4ade8c0f7288a847575534275ad099f..b4000e652a3d5f8a2d1bdcadead14c5d482147e6 100644 (file)
@@ -23,7 +23,7 @@ package config is
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61";
     
 --set to 0 for backplane serdes, set to 3 for front SFP serdes
-    constant SERDES_NUM             : integer := 0;   
+    constant SERDES_NUM             : integer := 3;   
 
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
index 2e74381a1700b127d4b752ff4a7651fa4bc91adf..467604849b863d3b8326ff043087aa44ed5f8cc5 100644 (file)
@@ -1,9 +1,9 @@
 TOPNAME                      => "trb3sc_pulser",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.9_x64/',
+synplify_path                => '/d/jspc29/lattice/synplify/J-2015.03-SP1/',
+synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodes_frankfurt.txt',
index 267734338812c5449298dc7175c6a27c1d08542b..e350e8e0bcb7170b927a900fadd7690fb744df79 100644 (file)
@@ -92,6 +92,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
@@ -115,7 +116,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"