"FIFO Shared Memory Error",
"Termination Status Warning",
"RPC Error",
- "Pexor DMA Error",
- "Pexor Device Error ioctl call"
+ "Pexor DMA Error, Kernel fatal, call SysAdmin",
+ "Pexor Device Error ioctl call, Kernel Fatal, call SysAdmin",
+ "Pexor Device Error ioctl call, TRBNet Timeout",
+ "Pexor Device Error ioctl call, DMA Polling Timeout",
+ "Pexor Device Error ioctl call, Out of DMA buffers",
+ "Pexor Device Error ioctl call, Invalid DMA Size"
};
- if (trberrno < 30) {
+ if (trberrno < 34) {
return errorstring[trberrno];
} else {
return "Unknown Error";
-const char trbnet_version[] = "$Revision: 4.12 $ Local";
+const char trbnet_version[] = "$Revision: 4.13 $ Local";
#include <stdlib.h>
#include <signal.h>
#else /* PEXOR */
-static inline int write32_to_FPGA(uint32_t address, uint32_t value)
+static int pexor_to_trb_error(int error)
+{
+ switch (error) {
+ case -129:
+ return TRB_PEXOR_DEVICE_ERROR;
+ break;
+
+ case -130:
+ return TRB_PEXOR_DEVICE_TRB_TIMEOUT;
+ break;
+
+ case -131:
+ return TRB_PEXOR_DEVICE_POLLING_TIMEOUT;
+ break;
+
+ case -132:
+ return TRB_PEXOR_DEVICE_DMA_EMPTY;
+ break;
+
+ case -133:
+ return TRB_PEXOR_DEVICE_INVALID_DMA_SIZE;
+ break;
+ }
+
+ return TRB_PEXOR_DEVICE_ERROR;
+}
+
+static int write32_to_FPGA(uint32_t address, uint32_t value)
{
struct pexor_reg_io descriptor;
int status = 0;
status = ioctl(pexorFileHandle, PEXOR_IOC_WRITE_REGISTER, &descriptor);
if(status == -1) {
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
status = ioctl(pexorFileHandle, PEXOR_IOC_READ_REGISTER, &descriptor);
if(status == -1) {
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
unsigned int timeout = 0;
do {
read32_from_FPGA(fifoAddress, &tmp);
- } while (((tmp & MASK_FIFO_VALID) == 0) && (++timeout < 10/*MAX_TIMEOUT*/));
+ } while (((tmp & MASK_FIFO_VALID) == 0) &&
+ (++timeout < 10/*MAX_TIMEOUT*/));
/* DEBUG INFO */
if ((trb_debug > 1) && ((tmp & MASK_FIFO_VALID) != 0)) {
fprintf(stderr, "FLUSH_FIFO_%03d: 0x%08x\n", counter, tmp);
}
/* Check for TX not Busy */
-#ifdef ETRAX
read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
if (tmp != 0) {
+#ifdef ETRAX
/* FIFO_TOGGLE_BIT-BUG Workaround */
com_reset_FPGA();
+#else
+ /* First try to resolve it by flushing the fifo */
+ fifo_flush(channel);
+#endif
+ /* Try again */
+ read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
+ if (tmp != 0) {
+ trb_errno = TRB_TX_BUSY;
+ return -1;
+ }
}
-#endif
- read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
- if (tmp != 0) {
- trb_errno = TRB_TX_BUSY;
- return -1;
- }
-
+
/* Check receiver FIFO empty */
#ifdef ETRAX
read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4),
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
/* Send command to pexor driver */
if (write(pexorFileHandle,
(void*)(data + ctr), len * 4) != len * 4) {
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;
&pexorDescriptor);
if (status < 0) {
unlockPorts(0);
- trb_errno = TRB_PEXOR_DEVICE_ERROR;
+ trb_errno = pexor_to_trb_error(status);
return -1;
}
dataBufferSize = status;