DATA_VALID_OUT(i) <= '1';
counter(i) <= counter(i) + 1;
else
+ DATA_OUT(i * 40 + 39 downto i * 40 + 0) <= (others => '0');
DATA_VALID_OUT(i) <= '0';
end if;
end process;
signal baseline, input : unsigned(RESOLUTION - 1 downto 0);
- signal baseline_average : unsigned(RESOLUTION + 2 ** CONF.BaselineAverage'length - 1 - 1 downto 0);
+ signal baseline_average : unsigned(RESOLUTION + 2 ** CONF.BaselineAverage'length - 1 - 1 downto 0) := (others => '0');
type delay_baseline_t is array (31 downto 0) of unsigned_in_thresh_t;
signal delay_baseline : delay_baseline_t := (others => unsigned_in_thresh_t_INIT);