signal fwd_mac_int : std_logic_vector(47 downto 0);
signal fwd_ip_int : std_logic_vector(31 downto 0);
signal fwd_port_int : std_logic_vector(15 downto 0);
+ signal fwd_data_int : std_logic_vector(7 downto 0);
+ signal fwd_ready_int : std_logic;
+ signal fwd_full_int : std_logic;
+ signal fwd_data_valid_int : std_logic;
+ signal fwd_sop_int : std_logic;
+ signal fwd_eop_int : std_logic;
+ signal fwd_busy_int : std_logic;
+ signal control_reg : std_logic_vector(31 downto 0);
+
begin
---------------------------------------------------------------------------
-- debug(33..20) are on GPIO
-- 33 = CLK2 (white/green)
-- 32 = CLK1 (white/blue)
-
- debug(7 downto 0) <= ul_rx_data(7 downto 0);
- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
- debug(16) <= ul_rx_data(9);
- debug(17) <= ul_tx_data_q(9);
- debug(18) <= ul_rx_data(10);
- debug(19) <= ul_tx_data_q(10);
- debug(20) <= ul_rx_data(8);
- debug(21) <= ul_tx_data_q(8);
- debug(22) <= ul_rx_frame_req;
- debug(23) <= ul_rx_frame_ack;
- debug(24) <= ul_rx_frame_avail;
- debug(25) <= dl_rx_frame_req(0);
- debug(26) <= dl_rx_frame_ack(0);
- debug(27) <= dl_rx_frame_avail(0);
- debug(28) <= port_sel(0);
- debug(29) <= ul_rx_fifofull;
- debug(30) <= ul_tx_fifofull;
- debug(31) <= '0';
- debug(32) <= tick_int;
- debug(33) <= clk_sys;
+--
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data_q(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data_q(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data_q(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(28) <= port_sel(0);
+-- debug(29) <= ul_rx_fifofull;
+-- debug(30) <= ul_tx_fifofull;
+-- debug(31) <= '0';
+-- debug(32) <= tick_int;
+-- debug(33) <= clk_sys;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
LINK_HAS_DHCP => '1',
LINK_HAS_ARP => '1',
LINK_HAS_PING => '1',
- LINK_HAS_FWD => '0'
+ LINK_HAS_FWD => '1'
)
port map(
CLK_125_IN => clk_sys,
FWD_DST_MAC_IN => fwd_mac_int,
FWD_DST_IP_IN => fwd_ip_int,
FWD_DST_UDP_IN => fwd_port_int,
- FWD_DATA_IN => x"00", --: in std_logic_vector(7 downto 0) := (others => '0');
- FWD_DATA_VALID_IN => '0', --: in std_logic := '0';
- FWD_SOP_IN => '0', --: in std_logic := '0';
- FWD_EOP_IN => '0', --: in std_logic := '0';
- FWD_READY_OUT => open, --: out std_logic;
- FWD_FULL_OUT => open, --: out std_logic;
+ FWD_DATA_IN => fwd_data_int,
+ FWD_DATA_VALID_IN => fwd_data_valid_int,
+ FWD_SOP_IN => fwd_sop_int,
+ FWD_EOP_IN => fwd_eop_int,
+ FWD_READY_OUT => fwd_ready_int,
+ FWD_FULL_OUT => fwd_full_int,
-- reset
MAKE_RESET_OUT => reset_via_gbe,
-- debug
STATUS_OUT => status(15 downto 8),
- DEBUG_OUT => debug(95 downto 64)
+ DEBUG_OUT => debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
);
+
+ THE_FWD_TEST: entity fwd_test
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ FWD_ENABLE_IN => additional_reg(31),
+ FWD_DELAY_IN => control_reg(31 downto 16),
+ FWD_SIZE_IN => control_reg(15 downto 0),
+ FWD_START_IN => tick_int,
+ FWD_BUSY_OUT => fwd_busy_int, --open
+ --
+ FWD_READY_IN => fwd_ready_int,
+ FWD_FULL_IN => fwd_full_int,
+ FWD_DATA_OUT => fwd_data_int,
+ FWD_DATA_VALID_OUT => fwd_data_valid_int,
+ FWD_SOP_OUT => fwd_sop_int,
+ FWD_EOP_OUT => fwd_eop_int,
+ --
+ DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+
+ debug(7 downto 0) <= fwd_data_int;
+ debug(8) <= fwd_ready_int;
+ debug(9) <= fwd_full_int;
+ debug(10) <= fwd_sop_int;
+ debug(11) <= fwd_eop_int;
+ debug(12) <= fwd_data_valid_int;
+ debug(13) <= fwd_busy_int;
+ debug(14) <= additional_reg(31);
+ debug(15) <= tick_int;
+ debug(16) <= debug(64);
+ debug(17) <= debug(65);
+ debug(18) <= debug(66);
+ debug(19) <= debug(68);
+ debug(20) <= debug(69);
+ debug(21) <= debug(70);
+ debug(22) <= debug(71);
+ debug(23) <= debug(72);
+ debug(24) <= debug(73);
+ debug(25) <= debug(74);
+ debug(26) <= debug(75);
+ debug(27) <= debug(76);
+ debug(28) <= debug(77);
+ debug(29) <= debug(78);
+ debug(30) <= debug(79);
+ debug(31) <= debug(80);
+ debug(32) <= debug(81);
+ debug(33) <= clk_sys;
+
+--DEBUG_OUT(3 downto 0) <= state;
+--DEBUG_OUT(4) <= ff_empty;
+--DEBUG_OUT(5) <= ff_full;
+--DEBUG_OUT(6) <= ff_wr_en;
+--DEBUG_OUT(7) <= ff_rd_en;
+--DEBUG_OUT(15 downto 8) <= ff_q(7 downto 0);
+--DEBUG_OUT(16) <= ff_q(8);
+--DEBUG_OUT(17) <= local_eop;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
-- Additional register
ADDITIONAL_REG => additional_reg,
+ CTRL_REG => control_reg,
-- Ethernet registers
- FWD_MAC_OUT => open,
- FWD_IP_OUT => open,
- FWD_PORT_OUT => open,
+ FWD_MAC_OUT => fwd_mac_int,
+ FWD_IP_OUT => fwd_ip_int,
+ FWD_PORT_OUT => fwd_port_int,
--Slowcontrol
BUS_RX => bustools_rx,
BUS_TX => bustools_tx,
LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
- LED(3) <= not additional_reg(31); --'0';
- LED(2) <= not additional_reg(30); --'0';
- LED(1) <= not additional_reg(29); --'0';
- LED(0) <= not additional_reg(28); --'0';
+ LED(3) <= not additional_reg(7); --'0';
+ LED(2) <= not additional_reg(6); --'0';
+ LED(1) <= not additional_reg(5); --'0';
+ LED(0) <= not additional_reg(4); --'0';
-- 0 red
-- 1 orange