]> jspc29.x-matter.uni-frankfurt.de Git - TOMcat.git/commitdiff
first working version of forwarder
authorMichael Boehmer <mboehmer@ph.tum.de>
Tue, 19 Jul 2022 06:55:53 +0000 (08:55 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Tue, 19 Jul 2022 06:55:53 +0000 (08:55 +0200)
code/tomcat_tools.vhd
gbe/tomcat_gbe.prj
gbe/tomcat_gbe.vhd

index 2af7719a2ba763175db14ea4e11be99c35582d41..ad8596e348cb84363eaa9630122fcc97e85702d7 100644 (file)
@@ -28,6 +28,7 @@ entity tomcat_tools is
     BUS_MASTER_ACTIVE : out   std_logic;
     -- Additional regs
     ADDITIONAL_REG    : out   std_logic_vector(31 downto 0);
+    CTRL_REG          : out   std_logic_vector(31 downto 0);
     -- Ethernet registers
     FWD_MAC_OUT       : out   std_logic_vector(47 downto 0);
     FWD_IP_OUT        : out   std_logic_vector(31 downto 0);
@@ -67,13 +68,13 @@ signal i2c_start_x        : std_logic;
 signal i2c_start          : std_logic;
 
 signal add_reg0_i         : std_logic_vector(31 downto 0) := x"0000_0000";
-signal add_reg1_i         : std_logic_vector(31 downto 0) := x"0000_0011";
-signal add_reg2_i         : std_logic_vector(31 downto 0) := x"0000_0022";
-signal add_reg3_i         : std_logic_vector(31 downto 0) := x"0000_0033";
-signal add_reg4_i         : std_logic_vector(31 downto 0) := x"0000_0044";
-signal add_reg5_i         : std_logic_vector(31 downto 0) := x"0000_0055";
-signal add_reg6_i         : std_logic_vector(31 downto 0) := x"0000_0066";
-signal add_reg7_i         : std_logic_vector(31 downto 0) := x"0000_0077";
+signal add_reg1_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg2_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg3_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg4_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg5_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg6_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg7_i         : std_logic_vector(31 downto 0) := x"0000_0000";
 
 begin
 
@@ -233,6 +234,8 @@ end generate;
 
   ADDITIONAL_REG <= add_reg0_i;
 
+  CTRL_REG <= add_reg1_i;
+  
   FWD_MAC_OUT(31 downto 0)  <= add_reg4_i;
   FWD_MAC_OUT(47 downto 32) <= add_reg5_i(15 downto 0);
   FWD_IP_OUT                <= add_reg6_i;
index 72fb0b106a977c315bf0506fd4b094f2dd2cf1c5..0bd91e388a411b0f21c20d24489662ac986ec789 100644 (file)
@@ -174,6 +174,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/rb_4k_9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/fifo_4k_9.vhd"
 
 
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test.vhd"
+
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
index c3cf2f810989fc001092c4ed5e625de004e8c6d9..e5b8000f75f9a1aac637c5560e84e4f205d0b4f4 100644 (file)
@@ -155,7 +155,16 @@ architecture arch of tomcat_gbe is
   signal fwd_mac_int                : std_logic_vector(47 downto 0);
   signal fwd_ip_int                 : std_logic_vector(31 downto 0);
   signal fwd_port_int               : std_logic_vector(15 downto 0);
+  signal fwd_data_int               : std_logic_vector(7 downto 0);
+  signal fwd_ready_int              : std_logic;
+  signal fwd_full_int               : std_logic;
+  signal fwd_data_valid_int         : std_logic;
+  signal fwd_sop_int                : std_logic;
+  signal fwd_eop_int                : std_logic;
+  signal fwd_busy_int               : std_logic;
   
+  signal control_reg                : std_logic_vector(31 downto 0);
+
 begin
 
 ---------------------------------------------------------------------------
@@ -237,27 +246,27 @@ begin
 -- debug(33..20) are on GPIO
 -- 33 = CLK2 (white/green)
 -- 32 = CLK1 (white/blue)
-  
-  debug(7 downto 0)    <= ul_rx_data(7 downto 0);
-  debug(15 downto 8)   <= ul_tx_data_q(7 downto 0);
-  debug(16)            <= ul_rx_data(9);
-  debug(17)            <= ul_tx_data_q(9);
-  debug(18)            <= ul_rx_data(10);
-  debug(19)            <= ul_tx_data_q(10);
-  debug(20) <= ul_rx_data(8);
-  debug(21) <= ul_tx_data_q(8);
-  debug(22) <= ul_rx_frame_req;
-  debug(23) <= ul_rx_frame_ack;
-  debug(24) <= ul_rx_frame_avail;
-  debug(25) <= dl_rx_frame_req(0);
-  debug(26) <= dl_rx_frame_ack(0);
-  debug(27) <= dl_rx_frame_avail(0);
-  debug(28) <= port_sel(0);
-  debug(29) <= ul_rx_fifofull;
-  debug(30) <= ul_tx_fifofull;
-  debug(31) <= '0';
-  debug(32) <= tick_int;
-  debug(33) <= clk_sys;
+--  
+--  debug(7 downto 0)    <= ul_rx_data(7 downto 0);
+--  debug(15 downto 8)   <= ul_tx_data_q(7 downto 0);
+--  debug(16)            <= ul_rx_data(9);
+--  debug(17)            <= ul_tx_data_q(9);
+--  debug(18)            <= ul_rx_data(10);
+--  debug(19)            <= ul_tx_data_q(10);
+--  debug(20) <= ul_rx_data(8);
+--  debug(21) <= ul_tx_data_q(8);
+--  debug(22) <= ul_rx_frame_req;
+--  debug(23) <= ul_rx_frame_ack;
+--  debug(24) <= ul_rx_frame_avail;
+--  debug(25) <= dl_rx_frame_req(0);
+--  debug(26) <= dl_rx_frame_ack(0);
+--  debug(27) <= dl_rx_frame_avail(0);
+--  debug(28) <= port_sel(0);
+--  debug(29) <= ul_rx_fifofull;
+--  debug(30) <= ul_tx_fifofull;
+--  debug(31) <= '0';
+--  debug(32) <= tick_int;
+--  debug(33) <= clk_sys;
 ---------------------------------------------------------------------------
 ---------------------------------------------------------------------------
 
@@ -312,7 +321,7 @@ begin
       LINK_HAS_DHCP             => '1',
       LINK_HAS_ARP              => '1',
       LINK_HAS_PING             => '1',
-      LINK_HAS_FWD              => '0'
+      LINK_HAS_FWD              => '1'
     )
     port map(
       CLK_125_IN               => clk_sys,
@@ -361,18 +370,85 @@ begin
       FWD_DST_MAC_IN           => fwd_mac_int,
       FWD_DST_IP_IN            => fwd_ip_int,
       FWD_DST_UDP_IN           => fwd_port_int,
-      FWD_DATA_IN              => x"00", --: in  std_logic_vector(7 downto 0) := (others => '0');
-      FWD_DATA_VALID_IN        => '0', --: in  std_logic := '0';
-      FWD_SOP_IN               => '0', --: in  std_logic := '0';
-      FWD_EOP_IN               => '0', --: in  std_logic := '0';
-      FWD_READY_OUT            => open, --: out std_logic;
-      FWD_FULL_OUT             => open, --: out std_logic;
+      FWD_DATA_IN              => fwd_data_int,
+      FWD_DATA_VALID_IN        => fwd_data_valid_int,
+      FWD_SOP_IN               => fwd_sop_int,
+      FWD_EOP_IN               => fwd_eop_int,
+      FWD_READY_OUT            => fwd_ready_int,
+      FWD_FULL_OUT             => fwd_full_int,
       -- reset
       MAKE_RESET_OUT           => reset_via_gbe,
       -- debug
       STATUS_OUT               => status(15 downto 8),
-      DEBUG_OUT                => debug(95 downto 64)
+      DEBUG_OUT                => debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
     );
+  
+  THE_FWD_TEST: entity fwd_test
+  port map(
+    CLK                 => clk_sys,
+    RESET               => reset_i,
+    --
+    FWD_ENABLE_IN       => additional_reg(31),
+    FWD_DELAY_IN        => control_reg(31 downto 16),
+    FWD_SIZE_IN         => control_reg(15 downto 0),
+    FWD_START_IN        => tick_int,
+    FWD_BUSY_OUT        => fwd_busy_int, --open
+    --
+    FWD_READY_IN        => fwd_ready_int,
+    FWD_FULL_IN         => fwd_full_int,
+    FWD_DATA_OUT        => fwd_data_int,
+    FWD_DATA_VALID_OUT  => fwd_data_valid_int,
+    FWD_SOP_OUT         => fwd_sop_int,
+    FWD_EOP_OUT         => fwd_eop_int, 
+    --
+    DEBUG               => open
+  );
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+  
+  debug(7 downto 0)    <= fwd_data_int;
+  debug(8)             <= fwd_ready_int;
+  debug(9)             <= fwd_full_int;
+  debug(10)            <= fwd_sop_int;
+  debug(11)            <= fwd_eop_int;
+  debug(12)            <= fwd_data_valid_int;
+  debug(13)            <= fwd_busy_int;
+  debug(14)            <= additional_reg(31);
+  debug(15)            <= tick_int;
+  debug(16)            <= debug(64);
+  debug(17)            <= debug(65);
+  debug(18)            <= debug(66);
+  debug(19)            <= debug(68);
+  debug(20) <= debug(69);
+  debug(21) <= debug(70);
+  debug(22) <= debug(71);
+  debug(23) <= debug(72);
+  debug(24) <= debug(73);
+  debug(25) <= debug(74);
+  debug(26) <= debug(75);
+  debug(27) <= debug(76);
+  debug(28) <= debug(77);
+  debug(29) <= debug(78);
+  debug(30) <= debug(79);
+  debug(31) <= debug(80);
+  debug(32) <= debug(81);
+  debug(33) <= clk_sys;
+
+--DEBUG_OUT(3 downto 0)   <= state;
+--DEBUG_OUT(4)            <= ff_empty;
+--DEBUG_OUT(5)            <= ff_full;
+--DEBUG_OUT(6)            <= ff_wr_en;
+--DEBUG_OUT(7)            <= ff_rd_en;
+--DEBUG_OUT(15 downto 8)  <= ff_q(7 downto 0);
+--DEBUG_OUT(16)           <= ff_q(8);
+--DEBUG_OUT(17)           <= local_eop;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
 
 ---------------------------------------------------------------------------
 ---------------------------------------------------------------------------
@@ -479,10 +555,11 @@ begin
       SCL_INOUT          => SFP_MOD_1, --open, --SI2C_SCL,      
       -- Additional register
       ADDITIONAL_REG     => additional_reg,
+      CTRL_REG           => control_reg,
       -- Ethernet registers
-      FWD_MAC_OUT        => open,
-      FWD_IP_OUT         => open,
-      FWD_PORT_OUT       => open,
+      FWD_MAC_OUT        => fwd_mac_int,
+      FWD_IP_OUT         => fwd_ip_int,
+      FWD_PORT_OUT       => fwd_port_int,
       --Slowcontrol
       BUS_RX             => bustools_rx,
       BUS_TX             => bustools_tx,
@@ -531,10 +608,10 @@ begin
   LED_SFP_GREEN   <= not (status(0) and status(1) and status(2)); --'0';
   LED_SFP_YELLOW  <= not status(5); --'0';
   LED_SFP_RED     <= not status(6); --'0';
-  LED(3)          <= not additional_reg(31); --'0';
-  LED(2)          <= not additional_reg(30); --'0';
-  LED(1)          <= not additional_reg(29); --'0';
-  LED(0)          <= not additional_reg(28); --'0';
+  LED(3)          <= not additional_reg(7); --'0';
+  LED(2)          <= not additional_reg(6); --'0';
+  LED(1)          <= not additional_reg(5); --'0';
+  LED(0)          <= not additional_reg(4); --'0';
 
   -- 0 red
   -- 1 orange