*** empty log message ***

diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd
index 652df26286abe0ea1eea12349f3dd5c8d7ddeb00..9aeeb9fe4d7a129a93232c1c3b616898479f96c2 100644 (file)
--- a/trb_net16_med_ecp_sfp.vhd
+++ b/trb_net16_med_ecp_sfp.vhd
@@ -165,6 +165,8 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal counter       : std_logic_vector(28 downto 0);
   signal tx_allow      : std_logic;
   signal rx_allow      : std_logic;
+  signal serdes_reset  : std_logic;
+  signal serdes_reset_counter : std_logic_vector(6 downto 0);
 
 
 begin
@@ -330,30 +332,40 @@ begin
 --link start-up state machine
 ----------------------
 
- medium_states : process(ff_rxhalfclk, RESET)
+--generate quad reset with primary clock
+  gen_serdes_reset : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          serdes_reset_counter <= (others => '0');
+          serdes_reset <= '1';
+        else
+          if serdes_reset_counter(6) = '1' then
+            serdes_reset <= '0';
+          else
+            serdes_reset_counter <= serdes_reset_counter + 1;
+          end if;
+        end if;
+      end if;
+    end process;
+
+--start-up with derived clock
+  medium_states : process(ff_rxhalfclk, RESET)
     begin
       if RESET = '1' then
         swap_bytes <= '0';
         tx_allow <= '0';
         rx_allow <= '0';
-        state <= start;
+        state <= waitplolandrlol;
         MED_ERROR_OUT <= ERROR_NC;
         counter <= (others => '0');
       elsif rising_edge(ff_rxhalfclk) then
         counter <= counter + 1;
         case state is
-          when start =>
-            if counter(7 downto 0) = x"FF" then
-              counter <= (others => '0');
-              state <= waitplolandrlol;
-            end if;
-            MED_ERROR_OUT <= ERROR_NC;
-            rx_allow <= '0';
-            tx_allow <= '0';
           when waitplolandrlol =>
-            counter <= (others => '0');
             if (link_error(5) = '0' and link_error(4) = '0') THEN
               state   <= waitrxallow;
+              counter <= (others => '0');
             end if;
             MED_ERROR_OUT <= ERROR_NC;
           when waitrxallow =>
@@ -389,9 +401,9 @@ begin
       end if;
     end process;
 
-  ffc_quad_rst         <= '1' when state = start else RESET;
-  ffc_lane_tx_rst_ch2  <= '1' when state = start or state = waitplolandrlol   else '0';
-  ffc_lane_rx_rst_ch2  <= '1' when state = start or state = waitplolandrlol   else '0';
+  ffc_quad_rst         <= '1' when serdes_reset = '1' else RESET;
+  ffc_lane_tx_rst_ch2  <= '1' when serdes_reset = '1' or state = waitplolandrlol   else '0';
+  ffc_lane_rx_rst_ch2  <= '1' when serdes_reset = '1' or state = waitplolandrlol   else '0';
 
 
   process(state)