removing some warnings from compiling

diff --git a/mupix/Mupix8/sources/DatasourceSelector.vhd b/mupix/Mupix8/sources/DatasourceSelector.vhd
index d62da28acb000557c037a79e938f9dfc2f9ee196..287d728204450679190e233530c1e0447bd5e08f 100644 (file)
--- a/mupix/Mupix8/sources/DatasourceSelector.vhd
+++ b/mupix/Mupix8/sources/DatasourceSelector.vhd
@@ -34,7 +34,6 @@ entity DataSourceSelector is
         sd_rden   : out std_logic_vector(3 downto 0);
         
         sel       : in std_logic;   -- Selects FrameGen
-        clk       : in std_logic;
         rst       : in std_logic;
         
         out_data0 : out std_logic_vector(WIDTH - 1 downto 0);
@@ -51,7 +50,10 @@ architecture Behavioral of DataSourceSelector is
 
 begin
 
-    Dsel: process (rst, sel)
+  Dsel: process (rst, sel,
+                 fg0in, fg1in, fg2in, fg3in,
+                 serdes0, serdes1, serdes2, serdes3,
+                 fg_full, fg_empty, sd_full, sd_empty, fifo_rdenx)
     begin
         if rst = '1' then
             out_data0  <= (others => '0');

diff --git a/mupix/Mupix8/sources/FrameGeneratorMux.vhd b/mupix/Mupix8/sources/FrameGeneratorMux.vhd
index 13e439f2fa06c7ca74c529185585e8a5b9cd8f67..d8cf0950dbd390eaaf6aad88c58748794d57e334 100644 (file)
--- a/mupix/Mupix8/sources/FrameGeneratorMux.vhd
+++ b/mupix/Mupix8/sources/FrameGeneratorMux.vhd
@@ -98,7 +98,6 @@ component DataSourceSelector is
         sd_rden   : out std_logic_vector(3 downto 0);
                 
         sel       : in std_logic;   -- Selects FrameGen
-        clk       : in std_logic;
         rst       : in std_logic;
                 
         out_data0 : out std_logic_vector(WIDTH - 1 downto 0);
@@ -174,7 +173,6 @@ begin -- Behavioral
         WIDTH => DATAWIDTH
     )
     port map(
-        clk => clk,
         rst => reset,
         sel => mux_sel,
         fg0in => fifo_data(0),

diff --git a/mupix/Mupix8/sources/Generator3.vhd b/mupix/Mupix8/sources/Generator3.vhd
index 9a3a7f0d1a17476a8c8a354e2606beab387e2e26..898be09f7648df33fc5cc35e4f593c6f2e61b1e7 100644 (file)
--- a/mupix/Mupix8/sources/Generator3.vhd
+++ b/mupix/Mupix8/sources/Generator3.vhd
@@ -40,7 +40,7 @@ signal num_ctr     : unsigned(31 downto 0) := (others => '0');
 signal pause_ctr   : unsigned(31 downto 0) := (others => '0');
 signal down_ctr    : unsigned(31 downto 0) := (others => '0');
 --signal data_int    : unsigned(15 downto 0) := (others => '0');
-signal chan_sig : chan_type := (
+constant chan_sig : chan_type := (
     0      => x"CA00",
     1      => x"CA01",
     2      => x"CA02",

diff --git a/mupix/Mupix8/sources/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/MuPixDataLink_new.vhd
index a180c641946cec6a11b88e74d6c1a3b8fd678198..f476c8af9b36ac3c25314bc75395a335269f4fcf 100644 (file)
--- a/mupix/Mupix8/sources/MuPixDataLink_new.vhd
+++ b/mupix/Mupix8/sources/MuPixDataLink_new.vhd
@@ -499,4 +499,6 @@ begin
     end if;
   end process slowcontrol_proc;
 
+  channel_status_led <= link_sync_flag_i and not rx_dataerror_sync;
+
 end architecture;

diff --git a/mupix/Mupix8/sources/TriggerHandler.vhd b/mupix/Mupix8/sources/TriggerHandler.vhd
index 21175b82d4c27e63fcb109054c0c3adbda6ff5f4..cbbf5d8cf3b8330718c7adc71b7ec6762162480f 100644 (file)
--- a/mupix/Mupix8/sources/TriggerHandler.vhd
+++ b/mupix/Mupix8/sources/TriggerHandler.vhd
@@ -129,7 +129,7 @@ begin
       else
         buffer_readout_end_int   <= buffer_readout_end_int(0) & TRIGGER_BUSY_BUFFER_READ_IN;
         timing_trigger_edge      <= timing_trigger_edge(0) & TIMING_TRIGGER_IN;
-        reset_trigger_state_edge <= reset_trigger_state_edge(1) & reset_trigger_state;
+        reset_trigger_state_edge <= reset_trigger_state_edge(0) & reset_trigger_state;
       end if;
     end if;
   end process Signal_Edge_Detect;

diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd
index bb15ba19c7bdab353cd425e91a74b6790534fa61..e94bcd66bdf5f673db443705cc6a46130461e558 100644 (file)
--- a/mupix/Mupix8/trb3_periph.vhd
+++ b/mupix/Mupix8/trb3_periph.vhd
@@ -365,6 +365,9 @@ architecture trb3_periph_arch of trb3_periph is
 
   --dummy
   signal dummy_counter : integer range 0 to 8 := 0;
+  signal syncres_i : std_logic := '0';
+
+  --mupix clocks   
   signal mupix_clk_i   : std_logic;
 
 begin
@@ -834,13 +837,14 @@ begin
   begin
     if rising_edge(clk_100_i) then
       if dummy_counter = 7 then
-        syncres       <= not syncres;
+        syncres_i       <= not syncres_i;
         dummy_counter <= 0;
       else
-        syncres       <= syncres;
         dummy_counter <= dummy_counter + 1;
       end if;
     end if;
   end process dummy_proc;
 
+  syncres <= syncres_i;
+  
 end architecture;