use work.trb_net16_hub_func.all;
entity flexi_PCS_channel_synch is
+ generic (
+ SYSTEM : positive);
port (
RESET : in std_logic;
SYSTEM_CLK : in std_logic;
PULSE : out std_logic);
end component;
+ component cross_clk
+ port (
+ WrAddress : in std_logic_vector(2 downto 0);
+ Data : in std_logic_vector(31 downto 0);
+ WrClock : in std_logic;
+ WE : in std_logic;
+ WrClockEn : in std_logic;
+ RdAddress : in std_logic_vector(2 downto 0);
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0));
+ end component;
+
+ component trbv2_cross_clk
+ port (
+ addra : in std_logic_vector(2 downto 0);
+ addrb : in std_logic_vector(2 downto 0);
+ clka : in std_logic;
+ clkb : in std_logic;
+ dina : in std_logic_vector(31 downto 0);
+ dinb : in std_logic_vector(31 downto 0);
+ douta : out std_logic_vector(31 downto 0);
+ doutb : out std_logic_vector(31 downto 0);
+ wea : in std_logic;
+ web : in std_logic);
+ end component;
+
+ component trbv2_link_fifo
+ port (
+ din : IN std_logic_VECTOR(17 downto 0);
+ rd_clk : IN std_logic;
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_clk : IN std_logic;
+ wr_en : IN std_logic;
+ almost_empty : OUT std_logic;
+ almost_full : OUT std_logic;
+ dout : OUT std_logic_VECTOR(17 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic);
+ end component;
+
type SYNC_MACHINE is (FIRST_DUMMY_STATE, START_COUNTER, RESYNC0, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, WAIT_3, NORMAL_OPERATION_1, NORMAL_OPERATION_2);
signal SYNC_CURRENT, SYNC_NEXT : SYNC_MACHINE;
- attribute syn_enum_encoding : string;
- attribute syn_enum_encoding of SYNC_MACHINE : type is "safe";
- attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential";
+-- attribute syn_enum_encoding : string;
+-- attribute syn_enum_encoding of SYNC_MACHINE : type is "safe";
+-- attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential";
signal fsm_debug_register : std_logic_vector(3 downto 0);
signal resync_counter_up :std_logic;
signal tx_k_i : std_logic;
signal fifo_opt_empty_synch_synch : std_logic;
signal fifo_rd_en_hub : std_logic;
- constant SYSTEM : Integer := 1;
+-- constant SYSTEM : Integer := 1;
signal wait_for_write_up : std_logic;
signal wait_for_write_counter : std_logic_vector(28 downto 0);
signal link_reset_counter : std_logic_vector(2 downto 0);
signal cv_counter_reset : std_logic;
signal rx_comma : std_logic_vector(1 downto 0);
signal rx_comma_synch : std_logic_vector(1 downto 0);
+
+ --crossing clk memory
+ signal cross_wraddress_i : std_logic_vector(2 downto 0);
+ signal cross_data_i : std_logic_vector(31 downto 0);
+ signal cross_rdaddress_i : std_logic_vector(2 downto 0);
+ signal cross_q_i : std_logic_vector(31 downto 0);
+ signal rx_comma_synch_err : std_logic;
+ signal lost_connection_count : std_logic_vector(15 downto 0);
+
begin
--reset from link
end if;
end process RESET_LINK_ERROR_COUNTER;
- LINK_RESET_COUNTER: up_down_counter
+ LINK_RESET_COUNTER_INST: up_down_counter
generic map (
NUMBER_OF_BITS => 3)
port map (
LINK_DEBUG(7 downto 4) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full;--fifo_almost_full &
--'0';
LINK_DEBUG(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); -- LINK_DEBUG(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
- LINK_DEBUG(31 downto 16) <= fifo_data_in(7 downto 0) & rx_k_synch_i & resync_counter_clr & RESET & CV & resync_counter(0) & MEDIA_STATUS(0) ;
+ LINK_DEBUG(31 downto 16) <= fifo_data_out(3 downto 0) & lost_connection_count(7 downto 0) & '0' & rx_comma_synch & MEDIA_STATUS(0) ;
end if;
end if;
end process LINK_STATUS;
-----------------------------------------------------------------------------
-- data from hub to link
-----------------------------------------------------------------------------
+
+
+ CROSS_WR_ADDRESS: process (RX_CLK, RESET)
+ begin
+ if rising_edge (RX_CLK) then
+ if RESET = '1' then
+ cross_wraddress_i <= "000";
+ else
+ cross_wraddress_i <= cross_wraddress_i + 1;
+ end if;
+ end if;
+ end process CROSS_WR_ADDRESS;
+
+ CROSS_RD_ADDRESS: process (SYSTEM_CLK, RESET)
+ begin
+ if rising_edge (SYSTEM_CLK) then
+ if RESET = '1' then
+ cross_rdaddress_i <= "000";
+ else
+ cross_rdaddress_i <= cross_rdaddress_i + 1;
+ end if;
+ end if;
+ end process CROSS_RD_ADDRESS;
+
+ cross_data_i <= x"0000000" & "00" & rx_comma;
data_opt_in <= "00" & MED_DATA_IN;
+
SYSTEM_SCM_MEMa: if SYSTEM=1 generate
CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR
port map (
AlmostEmpty => fifo_opt_almost_empty,
AlmostFull => fifo_opt_almost_full
);
+
+ CROSS_CLK_DPMEM: cross_clk
+ port map (
+ WrAddress => cross_wraddress_i,
+ Data => cross_data_i,
+ WrClock => RX_CLK,
+ WE => '1',
+ WrClockEn => '1',
+ RdAddress => cross_rdaddress_i,
+ RdClock => SYSTEM_CLK,
+ RdClockEn => '1',
+ Reset => Reset,
+ Q => cross_q_i);
+
end generate SYSTEM_SCM_MEMa;
SYSTEM_ECP2_MEMa: if SYSTEM=2 generate
AlmostFull => fifo_opt_almost_full
);
end generate SYSTEM_ECP2_MEMa;
+
+ SYSTEMT_TRBv2_MEMa: if SYSTEM=6 generate
+
+ CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo
+ port map (
+ din => data_opt_in,
+ rd_clk => TX_CLK,
+ rd_en => fifo_opt_not_empty,
+ rst => fifo_rst,
+ wr_clk => SYSTEM_CLK,
+ wr_en => MED_DATAREADY_IN,
+ almost_empty => fifo_opt_almost_empty,
+ almost_full => fifo_opt_almost_full,
+ dout => txd_fifo_out,
+ empty => fifo_opt_empty,
+ full => fifo_opt_full);
+
+ TRBv2_CROSS_CLK_INST: trbv2_cross_clk
+ port map (
+ addra => cross_wraddress_i,
+ addrb => cross_rdaddress_i,
+ clka => RX_CLK,
+ clkb => SYSTEM_CLK,
+ dina => cross_data_i,
+ dinb => x"00000000",
+ douta => open,
+ doutb => cross_q_i,
+ wea => '1',
+ web => '0');
+
+ end generate SYSTEMT_TRBv2_MEMa;
DATA_SEND_TO_LINK: process (TX_CLK, RESET, MED_DATAREADY_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
begin
AlmostFull => fifo_almost_full
);
end generate SYSTEM_ECP2_MEMb;
+
+ SYSTEM_TRBv2: if SYSTEM=6 generate
+
+ CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo
+ port map (
+ din => fifo_data_in,
+ rd_clk => SYSTEM_CLK,
+ rd_en => fifo_rd_en,
+ rst => fifo_rst,
+ wr_clk => RX_CLK,
+ wr_en => fifo_wr_en,
+ almost_empty => fifo_almost_empty,
+ almost_full => fifo_almost_full,
+ dout => fifo_data_out,
+ empty => fifo_empty,
+ full => fifo_full);
+
+ end generate SYSTEM_TRBv2;
not_fifo_empty <= not fifo_empty;
RD_FIFO_PULSE: edge_to_pulse
end if;
end if;
end process SAVE_COMA;
+
SYNC_CLOCK : process (SYSTEM_CLK, RESET)
begin
resync_counter_clr <= resync_counter_clr_fsm;
wait_for_write_up <= wait_for_write_up_fsm;
MED_READ_OUT <= MED_READ_OUT_fsm;
- rx_comma_synch <= rx_comma;
+ rx_comma_synch <= cross_q_i(1 downto 0);
end if;
end if;
end process SYNC_CLOCK;
SYNC_NEXT <= NORMAL_OPERATION_2;
elsif wait_for_write_counter(28)='1' and rx_comma_synch = "10" then
SYNC_NEXT <= NORMAL_OPERATION_1;
+ elsif rx_comma_synch = "11" then
+ SYNC_NEXT <= START_COUNTER;
else
SYNC_NEXT <= WAIT_3;
end if;
resync_counter_up_fsm <= '0';
MED_READ_OUT_fsm <= '1';
if rx_comma_synch = "11" then
+-- if MEDIA_STATUS(0) = '1' then
+
SYNC_NEXT <= START_COUNTER;
else
SYNC_NEXT <= NORMAL_OPERATION_1;
resync_counter_up_fsm <= '0';
MED_READ_OUT_fsm <= '1';
if rx_comma_synch = "11" then
+-- if MEDIA_STATUS(0) = '1' then
SYNC_NEXT <= START_COUNTER;
else
SYNC_NEXT <= NORMAL_OPERATION_2;
if rising_edge(SYSTEM_CLK) then
if RESET = '1' then
MED_STAT_OP(9) <= '1';
- elsif fsm_debug_register < 9 then
+ elsif fsm_debug_register < 9 and fsm_debug_register > 3 then
MED_STAT_OP(9) <= diod_counter(23);
elsif fsm_debug_register = 9 then
MED_STAT_OP(9) <= diod_counter(26);
UP_IN => wait_for_write_up,
DOWN_IN => '0');
- RESYNC_COUNTER: up_down_counter
+ RESYNC_COUNTER_INST: up_down_counter
generic map (
NUMBER_OF_BITS => 32)
port map (
DOWN_IN => '0');
cv_or <= cv_i(0) or cv_i(1);
- CV_COUNTER: up_down_counter
+
+ CV_COUNTER_INST: up_down_counter
generic map (
NUMBER_OF_BITS => 16)
port map (
COUNT_OUT => cv_counter,
UP_IN => cv_or,
DOWN_IN => '0');
+ SYNCH_ERR_COUNT : process (SYSTEM_CLK, RESET)
+ begin
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ rx_comma_synch_err <= '0';
+ elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then
+ rx_comma_synch_err <= rx_comma_synch(1) and rx_comma_synch(0);
+ else
+ rx_comma_synch_err <= '0';
+ end if;
+ end if;
+ end process SYNCH_ERR_COUNT;
+
+ LINK_CONECTION_LOST_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => RX_CLK,
+ RESET => RESET,
+ COUNT_OUT => lost_connection_count,
+ UP_IN => rx_comma_synch_err,
+ DOWN_IN => '0');
WRITE_COUNTER: up_down_counter
generic map (
component flexi_PCS_synch
generic (
- HOW_MANY_CHANNELS : positive);
+ HOW_MANY_CHANNELS : positive;
+ SYSTEM : positive );
port (
RESET : in std_logic;
SYSTEM_CLK : in std_logic;
--sim-- end generate SIMULATION_CONNECTION;
FLEXI_PCS_INT : flexi_PCS_synch
generic map (
- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
+ HOW_MANY_CHANNELS => HOW_MANY_CHANNELS,
+ SYSTEM => 1)
port map (
RESET => global_reset_i,
SYSTEM_CLK => LVDS_CLK_200P,
port map (
CLK => LVDS_CLK_200P,
RESET => global_reset_i,
--- DATA_IN => med_data_out_i,
- DATA_IN => med_data_out_i_test,
+ DATA_IN => med_data_out_i,
+-- DATA_IN => med_data_out_i_test,
DATA_OUT => med_data_in_i,
DATA_IN_VALID => med_dataready_out_i,
--- SEND_DATA => med_dataready_in_i,
- SEND_DATA => med_dataready_in_i_test,
+ SEND_DATA => med_dataready_in_i,
+-- SEND_DATA => med_dataready_in_i_test,
ENABLE_CHANNELS => fpga_register_06_i(15 downto 0),
READ_DATA => med_read_in_i,
HUB_DEBUG => hub_debug_i
-- -- fpga_register_08_i <= rxd_i(63 downto 32);
-- fpga_register_0a_i(15 downto 0) <= cv_i(7 downto 0) & rx_k_i(3 downto 0) & "0000";
-
+
COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i )
begin
begin
-- lok_i(synch_fsm_state+1) <= not link_debug_i(2+synch_fsm_state*31);
lok_i(synch_fsm_state+1) <= med_stat_op_i(9 + synch_fsm_state*16);
- media_status_i(synch_fsm_state*16) <= '0';--SFP_LOS(synch_fsm_state);
+ media_status_i(synch_fsm_state*16) <= SFP_LOS(synch_fsm_state+1);
end generate LOK_STATUS_DIOD_EN;
-- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate
end if;
end if;
end process CV_COUNTERaab;
- RT(8) <= cv_counter(23);
- RT(9) <= med_read_in_i(0);
- RT(16 downto 10) <= link_debug_i(7 downto 1);
- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
- RT(1) <= not switch_rx_clk;--ref_pclk(0);
+-- RT(8) <= cv_counter(23);
+-- RT(9) <= med_read_in_i(0);
+-- RT(16 downto 10) <= link_debug_i(7 downto 1);
+-- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
+-- RT(1) <= not switch_rx_clk;--ref_pclk(0);
- RT(3) <= LVDS_CLK_200P;
-
- RT(4) <= rx_k_i(0);
+-- RT(3) <= LVDS_CLK_200P;
- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
- RT(6) <= med_data_out_i(0);--serdes_ref_clks;
- RT(7) <= med_data_out_i(1);--serdes_ref_lock;
+-- RT(4) <= rx_k_i(0);
+-- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
+-- RT(6) <= med_data_out_i(0);--serdes_ref_clks;
+-- RT(7) <= med_data_out_i(1);--serdes_ref_lock;
+ RT <= (others => '1');
end hub;
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