port(
CLK : in std_logic;
TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
RESET : in std_logic;
GSR_N : in std_logic;
-- Debug
signal monitor_sm : std_logic_vector(31 downto 0);
signal monitor_lr : std_logic_vector(31 downto 0);
signal monitor_hr : std_logic_vector(31 downto 0);
+signal monitor_fifos : std_logic_vector(31 downto 0);
+signal monitor_fifos_q : std_logic_vector(31 downto 0);
+
begin
MONITOR_SM_IN => monitor_sm,
MONITOR_LR_IN => monitor_lr,
MONITOR_HDR_IN => monitor_hr,
+ MONITOR_FIFOS_IN => monitor_fifos_q,
-- gk 01.06.10
DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
MONITOR_OUT(95 downto 64) => monitor_hr,
MONITOR_OUT(127 downto 96) => monitor_sm,
MONITOR_OUT(159 downto 128) => monitor_lr,
+ MONITOR_OUT(191 downto 160) => monitor_fifos,
DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
DEBUG_OUT(31 downto 0) => dbg_pc1,
DEBUG_OUT(63 downto 32) => dbg_pc2
);
-
+
+monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0);
+monitor_fifos_q(7 downto 4) <= b"1111" when ((dbg_pc1(28) = '1') or (dbg_pc1(31) = '1'))
+ else b"0000";
+monitor_fifos_q(11 downto 8) <= b"1111" when (dbg_fc1(28) = '1') else b"0000";
+monitor_fifos_q(15 downto 12) <= b"1111" when (pcs_an_complete = '0') else b"0000";
+
-- Third stage: Frame Constructor
FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
port map(
-- ports for user logic
- RESET => RESET,
- CLK => CLK,
+ RESET => RESET,
+ CLK => CLK,
+ LINK_OK_IN => pcs_an_complete, -- gk 03.08.10
--
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
+ WR_EN_IN => fc_wr_en,
+ DATA_IN => fc_data,
START_OF_DATA_IN => fc_sod,
END_OF_DATA_IN => fc_eod,
IP_F_SIZE_IN => fc_ip_size,
UDP_P_SIZE_IN => fc_udp_size,
HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
+ READY_OUT => fc_ready,
DEST_MAC_ADDRESS_IN => fc_dest_mac,
DEST_IP_ADDRESS_IN => fc_dest_ip,
DEST_UDP_PORT_IN => fc_dest_udp,
SRC_UDP_PORT_IN => fc_src_udp,
FRAME_TYPE_IN => fc_type,
IHL_VERSION_IN => fc_ihl_version,
- TOS_IN => fc_tos,
+ TOS_IN => fc_tos,
IDENTIFICATION_IN => fc_ident,
FLAGS_OFFSET_IN => fc_flags_offset,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_protocol,
+ TTL_IN => fc_ttl,
+ PROTOCOL_IN => fc_protocol,
-- ports for packetTransmitter
- RD_CLK => serdes_clk_125,
+ RD_CLK => serdes_clk_125,
FT_DATA_OUT => ft_data,
--FT_EOD_OUT => ft_eod, -- gk 04.05.10
FT_TX_EMPTY_OUT => ft_tx_empty,
FT_TX_RD_EN_IN => mac_tx_read,
- FT_START_OF_PACKET_OUT => ft_start_of_packet,
+ FT_START_OF_PACKET_OUT => ft_start_of_packet,
FT_TX_DONE_IN => mac_tx_done,
-- debug ports
BSM_CONSTR_OUT => fc_bsm_constr,
BSM_TRANS_OUT => fc_bsm_trans,
DEBUG_OUT(31 downto 0) => dbg_fc1,
DEBUG_OUT(63 downto 32) => dbg_fc2
-);
-
+);
+
FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
port map(
- CLK => CLK,
- RESET => RESET,
- TX_MAC_CLK => serdes_clk_125,
- TX_EMPTY_IN => ft_tx_empty,
+ CLK => CLK,
+ RESET => RESET,
+ LINK_OK_IN => pcs_an_complete, -- gk 03.08.10
+ TX_MAC_CLK => serdes_clk_125,
+ TX_EMPTY_IN => ft_tx_empty,
START_OF_PACKET_IN => ft_start_of_packet,
DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
-- MAC interface
- HADDR_OUT => mac_haddr,
- HDATA_OUT => mac_hdataout,
- HCS_OUT => mac_hcs,
- HWRITE_OUT => mac_hwrite,
- HREAD_OUT => mac_hread,
- HREADY_IN => mac_hready,
- HDATA_EN_IN => mac_hdata_en,
+ HADDR_OUT => mac_haddr,
+ HDATA_OUT => mac_hdataout,
+ HCS_OUT => mac_hcs,
+ HWRITE_OUT => mac_hwrite,
+ HREAD_OUT => mac_hread,
+ HREADY_IN => mac_hready,
+ HDATA_EN_IN => mac_hdata_en,
TX_FIFOAVAIL_OUT => mac_fifoavail,
TX_FIFOEOF_OUT => mac_fifoeof,
TX_FIFOEMPTY_OUT => mac_fifoempty,
- TX_DONE_IN => mac_tx_done,
+ TX_DONE_IN => mac_tx_done,
-- Debug
BSM_INIT_OUT => ft_bsm_init,
- BSM_MAC_OUT => ft_bsm_mac,
+ BSM_MAC_OUT => ft_bsm_mac,
BSM_TRANS_OUT => ft_bsm_trans,
DBG_RD_DONE_OUT => open,
DBG_INIT_DONE_OUT => open,
RESET => RESET,
GSR_N => GSR_N,
CLK_125_OUT => serdes_clk_125,
- CLK_RX_OUT => open,
- CLK_TX_OUT => open,
- CLK_125_TX_IN => CLK_125_TX_IN,
- CLK_125_RX_IN => CLK_125_RX_IN,
+ CLK_125_IN => CLK_125_IN,
FT_TX_CLK_EN_OUT => mac_tx_clk_en,
FT_RX_CLK_EN_OUT => mac_rx_clk_en,
--connection to frame transmitter (tsmac)
port map( RESET => RESET,
GSR_N => GSR_N,
CLK_125_OUT => serdes_clk_125,
- CLK_RX_OUT => open,
- CLK_TX_OUT => open,
- CLK_125_TX_IN => '0', -- not used
- CLK_125_RX_IN => '0', -- not used
+ CLK_125_IN => '0', -- not used
FT_TX_CLK_EN_OUT => mac_tx_clk_en,
FT_RX_CLK_EN_OUT => mac_rx_clk_en,
--connection to frame transmitter (tsmac)
-- ports for user logic\r
RESET : in std_logic;\r
CLK : in std_logic;\r
+ LINK_OK_IN : in std_logic; -- gk 03.08.10\r
--\r
WR_EN_IN : in std_logic;\r
DATA_IN : in std_logic_vector(7 downto 0);\r
\r
architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is\r
\r
+-- -- Placer Directives\r
+-- attribute HGROUP : string;\r
+-- -- for whole architecture\r
+-- attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_frame_constr_group";\r
+\r
component fifo_4096x9 is\r
port( \r
Data : in std_logic_vector(8 downto 0);\r
signal bsm_constr : std_logic_vector(7 downto 0);\r
attribute sys_encoding of constructCurrentState: signal is "safe,gray";\r
\r
-type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_CLEANUP);\r
+type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
signal bsm_trans : std_logic_vector(3 downto 0);\r
\r
end if;\r
when T_TRANSMIT =>\r
bsm_trans <= x"2";\r
- if( ft_tx_done_in = '1' ) then\r
+ -- gk 03.08.10\r
+ if (LINK_OK_IN = '1') and (ft_tx_done_in = '1') then\r
transmitNextState <= T_CLEANUP;\r
+ elsif (LINK_OK_IN = '0') then\r
+ transmitNextState <= T_PAUSE;\r
else\r
transmitNextState <= T_TRANSMIT;\r
end if;\r
+ when T_PAUSE =>\r
+ transmitNextState <= T_CLEANUP;\r
when T_CLEANUP =>\r
bsm_trans <= x"3";\r
transmitNextState <= T_IDLE;\r
end case;\r
end process transmitMachine;\r
\r
+\r
+\r
sopProc: process( RD_CLK )\r
begin\r
if rising_edge(RD_CLK) then\r
if rising_edge(RD_CLK) then\r
if ( RESET = '1' ) then\r
sent_frames_ctr <= (others => '0');\r
- elsif( ft_tx_done_in = '1' ) then\r
+ -- gk 03.08.10\r
+ elsif( ft_tx_done_in = '1' ) or (transmitCurrentState = T_PAUSE) then\r
sent_frames_ctr <= sent_frames_ctr + 1;\r
end if;\r
end if;\r
jspc29 / trbnet.git / commitdiff