-const char trbnet_version[] = "$Revision: 4.19 $ Local";
+const char trbnet_version[] = "$Revision: 4.20 $ Local";
#include <stdlib.h>
#include <signal.h>
char pexor_deviceName[256] = "/dev/pexor-0";
int pexorFileHandle = -1;
int pexor_dma = 1;
+
+#elif defined TRB3
+
+#include <sys/socket.h>
+#include <sys/wait.h>
+#include <netinet/in.h>
+#include <netdb.h>
+
+static uint16_t udpBuffer[750]; /* Maxminum is payload of one Ethernet-Frame */
+static uint32_t dataBuffer[4096 * 1024];
+static unsigned int dataBufferSize = 0;
+static int trb3_sockfd = -1;
+static uint16_t trb3_port = 26000;
+uint16_t sender_address = 0x5555;
#endif
+
#include <trberror.h>
#include "trbnet.h"
fifoToggleBit = 0;
}
-#else /* PEXOR */
+#endif
+
+#ifdef PEXOR /* PEXOR */
static int pexor_to_trb_error()
{
#endif /* End PEXOR */
+#ifdef TRB3
+
+static int sendTrbPackage(size_t size)
+{
+ int status;
+
+ if (send(trb3_sockfd, (void*)udpBuffer, size, MSG_CONFIRM) == -1) {
+ trb_errno = TRB_TRB3_SOCKET_ERROR;
+ return -1;
+ }
+
+ /* GetData */
+ status = recv(trb3_sockfd, (void*)dataBuffer, 1500, 0);
+ if (status == -1) {
+ trb_errno = TRB_TRB3_SOCKET_ERROR;
+ return -1;
+ }
+ dataBufferSize = status;
+
+ return status;
+}
+#endif /* TRB3 */
+
/* ------ Internal Functions -------------------------------------------- */
static void TRB_Package_dump(const TRB_Package* pkg)
static void fifo_flush(uint8_t channel)
{
+#ifdef TRB3
+ return;
+#else
+
uint32_t tmp = 0;
uint32_t fifoAddress;
unsigned int counter = 0;
counter++;
}
} while ((tmp & MASK_FIFO_VALID) != 0);
+
+#endif
}
static int trb_init_transfer(uint8_t channel)
{
+#ifndef TRB3
uint32_t tmp = 0;
-
if (channel >= 4) {
trb_errno = TRB_INVALID_CHANNEL;
return -1;
/* Check for TX not Busy */
read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
if (tmp != 0) {
+
#ifdef ETRAX
/* FIFO_TOGGLE_BIT-BUG Workaround */
com_reset_FPGA();
-#else
+#endif
+
+#ifdef PEXOR
/* First try to resolve it by flushing the fifo */
if (trb_debug > 0) {
fprintf(stderr,"trb_init_transfer: flushing fifo because of TX Busy\n");
}
fifo_flush(channel);
#endif
- /* Try again */
+
+ /* Try again */
read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
if (tmp != 0) {
trb_errno = TRB_TX_BUSY;
trb_errno = TRB_FIFO_NOT_EMPTY;
return -1;
}
+#endif
/* No Errors */
return 0;
uint32_t* tmp = &dataBuffer;
uint32_t fifoBuffer = 0;
unsigned int timeout = 0;
-#else /* Pexor DMA */
+#elif defined PEXOR || defined TRB3
uint32_t* tmp = dataBuffer;
#endif
uint32_t memLen = 0; /* used by FIFO_MODE_REG_READ_MEM
and FIFO_MODE_IPU_DATA Mode */
-#ifdef PEXOR
- if (dataBufferSize == 0) {
- trb_errno = TRB_PEXOR_DATA_ERROR;
- return -1;
- }
- if (read(pexorFileHandle,
- (void*)dataBuffer, dataBufferSize * 4) != dataBufferSize * 4) {
- trb_errno = TRB_PEXOR_DATA_ERROR;
- return -1;
- }
-#else
-
+#ifdef ETRAX
/* Determin FIFO-Address */
if (channel >= 4) {
trb_errno = TRB_INVALID_CHANNEL;
trb_errno = TRB_FIFO_TIMEOUT;
return -1;
}
+#else
+ if (dataBufferSize == 0) {
+ trb_errno = TRB_PEXOR_DATA_ERROR;
+ return -1;
+ }
+#ifdef PEXOR
+ if (read(pexorFileHandle,
+ (void*)dataBuffer, dataBufferSize * 4) != dataBufferSize * 4) {
+ trb_errno = TRB_PEXOR_DATA_ERROR;
+ return -1;
+ }
#endif
-
+#endif
+
/* Read FIFO-Buffer, copy to User-Buffer */
while ((*tmp & MASK_FIFO_VALID) != 0) {
!= channel)) {
/* Error Package inconsistencies, flush FIFO-BUFFER and exit */
-#ifdef ETRAX
fifo_flush(channel);
-#endif
trb_errno = TRB_FIFO_HEADERS;
return -1;
}
if (headerType == HEADER_TRM) {
break;
}
-
-#ifdef PEXOR
- if (tmp - dataBuffer >= dataBufferSize) {
- trb_errno = TRB_PEXOR_DATA_ERROR;
- return -1;
- }
- tmp++;
-#else
+#ifdef ETRAX
timeout = 0;
do {
read32_from_FPGA(fifoBuffer, tmp);
trb_errno = TRB_FIFO_TIMEOUT;
return -1;
}
+#else
+ if (tmp - dataBuffer >= dataBufferSize) {
+ trb_errno = TRB_PEXOR_DATA_ERROR;
+ return -1;
+ }
+ tmp++;
#endif
-
} /* end while () */
/* Copy StatusBits and Sequenze of TerminationPackage */
GPIOC_OUT_OFFSET = NULL;
}
-#else /* PEXOR */
+#elif defined PEXOR
void close_ports()
{
return 0;
}
-#endif /* End Pexor */
+#elif defined TRB3
+
+void close_ports()
+{
+ /* Close FileHandler */
+ return;
+}
+
+int init_ports()
+{
+ char* trb3_name = NULL;
+ struct sockaddr_in server_addr;
+ struct hostent *host = NULL;
+
+ trb_errno = TRB_NONE;
+
+ if (trb_debug > 0) {
+ fprintf(stderr, "init_ports: called\n");
+ }
+
+ trb3_name = getenv("TRB3_SERVER");
+ if (trb3_name == NULL) {
+ trb3_name = "pexor";
+ }
+
+ if ((host = gethostbyname(trb3_name)) == NULL) {
+ trb_errno = TRB_TRB3_SOCKET_ERROR;
+ return -1;
+ }
+
+ trb3_sockfd = socket(AF_INET, SOCK_DGRAM, 0);
+ if (trb3_sockfd == -1) {
+ trb_errno = TRB_TRB3_SOCKET_ERROR;
+ return -1;
+ }
+ server_addr.sin_family = AF_INET;
+ server_addr.sin_port = htons(trb3_port);
+ server_addr.sin_addr = *((struct in_addr *)host->h_addr);
+ memset(&(server_addr.sin_zero), 0, 8);
+ if (connect(trb3_sockfd,
+ (struct sockaddr *)&server_addr,
+ sizeof(struct sockaddr)) == -1) {
+ trb_errno = TRB_TRB3_SOCKET_ERROR;
+ return -1;
+ }
+
+ if (trb_debug > 0) {
+ fprintf(stderr, "init_ports: TRB3-Socket opened = %d\n", trb3_sockfd);
+ }
+
+ /* Init semaphore and signal handling */
+ if (init_semaphore() == -1) return -1;
+
+ return 0;
+}
+
+#endif
int trb_fifo_flush(uint8_t channel)
{
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
-#else
+#elif defined TRB3
+ /* Create TRBPackage */
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_READ;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = reg_address;
+ udpBuffer[7] = 0;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+ udpBuffer[11] = 0;
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_REGISTER_READ;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
+#else
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ);
+
+#elif defined TRB3
+ /* Create TRBPackage */
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_READ;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = reg_address;
+ udpBuffer[7] = 0;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+ udpBuffer[11] = 0;
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_REGISTER_READ;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
+
+#elif defined TRB3
+ /* Create TRBPackage */
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_READ_MEM;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = reg_address;
+ udpBuffer[7] = length;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_REGISTER_READ_MEM;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
+
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
pexorDescriptor.reg_address = reg_address;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM);
+
+#elif defined TRB3
+
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_READ_MEM;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = reg_address;
+ udpBuffer[7] = length;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+ udpBuffer[11] = 0;
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_REGISTER_READ_MEM;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
+
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
pexorDescriptor.reg_address = reg_address;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE);
+
+#elif defined TRB3
+
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_WRITE;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = reg_address;
+ udpBuffer[7] = (value >> 16) & 0xffff;
+ udpBuffer[8] = value & 0xffff;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+ udpBuffer[11] = 0;
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_REGISTER_WRITE;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
uint16_t config;
uint16_t ctr = 0;
int status = -1;
-#ifdef ETRAX
+#if defined ETRAX || defined TRB3
uint16_t i;
#endif
+#ifdef TRB3
+ unsigned int udpCtr = 0;
+#endif
trb_errno = TRB_NONE;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
}
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
+
+#elif defined TRB3
+
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_REGISTER_WRITE_MEM;
+
+ udpBuffer[5] = HEADER_DAT;
+ if (option == 0) {
+ udpBuffer[6] = reg_address + ctr;
+ } else {
+ udpBuffer[6] = reg_address;
+ }
+ udpBuffer[7] = config;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpCtr = 10;
+ for (i = 0; i < len; i++, ctr++) {
+ udpBuffer[udpCtr++] = HEADER_DAT;
+ udpBuffer[udpCtr++] = 0x00000000;
+ udpBuffer[udpCtr++] = (data[ctr] >> 16) & 0xffff;
+ udpBuffer[udpCtr++] = data[ctr] & 0xffff;
+ udpBuffer[udpCtr++] = 0x00000000;
+ }
+
+ udpBuffer[udpCtr++] = HEADER_TRM;
+ udpBuffer[udpCtr++] = 0;
+ udpBuffer[udpCtr++] = 0;
+ udpBuffer[udpCtr++] = 0;
+ udpBuffer[udpCtr++] = CMD_REGISTER_WRITE_MEM;
+
+ status = sendTrbPackage(udpCtr);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
+
/* Send command to pexor driver */
if (write(pexorFileHandle,
(void*)(data + ctr), len * 4) != len * 4) {
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
+
+#elif defined TRB3
+
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_NETADMINISTRATION;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = NET_READUNIQUEID;
+ udpBuffer[7] = 0;
+ udpBuffer[8] = 0;
+ udpBuffer[9] = 0;
+
+ udpBuffer[10] = HEADER_TRM;
+ udpBuffer[11] = 0;
+ udpBuffer[12] = 0;
+ udpBuffer[13] = 0;
+ udpBuffer[14] = CMD_NETADMINISTRATION;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
write32_to_FPGA(CHANNEL_3_SENDER_DATA, trb_address);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION);
+
+#elif defined TRB3
+
+ udpBuffer[0] = HEADER_HDR;
+ udpBuffer[1] = sender_address;
+ udpBuffer[2] = trb_address;
+ udpBuffer[3] = 0;
+ udpBuffer[4] = CMD_NETADMINISTRATION;
+
+ udpBuffer[5] = HEADER_DAT;
+ udpBuffer[6] = NET_SETADDRESS;
+ udpBuffer[7] = (uint16_t)(uid);
+ udpBuffer[8] = (uint16_t)(uid >> 16);
+ udpBuffer[9] = (uint16_t)(uid >> 32);
+
+ udpBuffer[10] = HEADER_DAT;
+ udpBuffer[11] = (uint16_t)(uid >> 48);
+ udpBuffer[12] = endpoint;
+ udpBuffer[13] = trb_address;
+ udpBuffer[14] = 0;
+
+ udpBuffer[15] = HEADER_TRM;
+ udpBuffer[16] = 0;
+ udpBuffer[17] = 0;
+ udpBuffer[18] = 0;
+ udpBuffer[19] = CMD_NETADMINISTRATION;
+
+ status = sendTrbPackage(15);
+
+ if (status < 0) {
+ unlockPorts(0);
+ return -1;
+ }
+ dataBufferSize = status;
+
#else
+
/* Send command to pexor driver */
pexorDescriptor.trb_address = trb_address;
pexorDescriptor.arg0 = (unsigned long)(uid & 0xffffffff);
return 0;
}
+#ifndef TRB3
int trb_ipu_data_read(uint8_t type,
uint8_t trg_info,
uint8_t trg_random,
return 0;
}
+#else /* NOT TRB3 */
+
+int trb_ipu_data_read(uint8_t type,
+ uint8_t trg_info,
+ uint8_t trg_random,
+ uint16_t trg_number,
+ uint32_t *data,
+ unsigned int dsize)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int trb_send_trigger(uint8_t type,
+ uint32_t trg_info,
+ uint8_t trg_random,
+ uint16_t trg_number)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int trb_send_trigger_rich(uint8_t trg_input,
+ uint8_t type,
+ uint32_t trg_info,
+ uint8_t trg_random,
+ uint16_t trg_number)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int fpga_register_read(uint32_t reg_address, uint32_t* value)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int fpga_register_write(uint32_t reg_address, uint32_t value)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int network_reset()
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int com_reset()
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+int trb_register_modify(uint16_t trb_address,
+ uint16_t reg_address,
+ int mode,
+ uint32_t bitMask,
+ uint32_t bitValue)
+{
+ trb_errno = TRB_TRB3_CMD_NOT_SUPPORTED;
+ return -1;
+}
+
+
+
+#endif
int trb_nettrace(uint16_t trb_address,
uint32_t *data,
jspc29 / trbnettools.git / commitdiff