Update to UART, fix for wrong bit start signals

diff --git a/special/uart_rec.vhd b/special/uart_rec.vhd
index 3d2ab2d363c5bc9961bfd4d70a7406563b9e75bc..f1688326f99758f603b1767accdf83afbb4fdae1 100644 (file)
--- a/special/uart_rec.vhd
+++ b/special/uart_rec.vhd
@@ -38,7 +38,7 @@ signal data_waiting_sig: std_logic := '0';
 signal current_data_out: std_logic_vector(7 downto 0) := "00000000";
 signal symbol_start_pulse : std_logic := '0'; -- just debug
 signal rst_clk_div_counter : std_logic;
-
+signal rx_reg : std_logic;
 
 begin
 ----------------------------
@@ -55,7 +55,8 @@ DEBUG(3) <= '0';
 ----------------------------
   sync_input : process begin
     wait until rising_edge(CLK);
-    symbol <= RX;
+    rx_reg <= RX;
+    symbol <= rx_reg;
   end process;
   
 ----------------------------
@@ -110,36 +111,38 @@ DEBUG(3) <= '0';
   --  state machine rules:
   case state is
     when idle =>
-
+      rst_clk_div_counter<= '1';
       if symbol = '0' then -- the start bit comes!
         state <= receiving;
         -- restart the divcounter
   --       clk_div_counter <= x"0000";
-        rst_clk_div_counter<= '1';
         symbol_counter <= x"0";
         
       end if;
     
     when receiving =>
       if symbol_pulse = '1' then
-        if symbol_counter <= 9 then -- reception process
+        if symbol_counter <= x"9" then -- reception process
           rx_shift_register(to_integer(symbol_counter)) <= symbol;
           symbol_counter <= symbol_counter + 1;
         end if;
-        if symbol_counter = 9 then
+        if symbol_counter = x"9" then
           state <= update_parallel_output;
         end if;
         
 
       end if;
     when update_parallel_output =>
-      state <= idle;
       -- check start and stop bit consistency
       -- (checking the start bit again seems a little obsolete)
       -- only if bit was received correctly output the data!
-      if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then
-        current_data_out <= rx_shift_register(8 downto 1);
-        data_waiting_sig <= '1';
+--       if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then
+      if symbol = '1' then
+        state <= idle;
+        if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then
+          current_data_out <= rx_shift_register(8 downto 1);
+          data_waiting_sig <= '1';
+        end if;  
       end if;
       
   end case;

diff --git a/special/uart_trans.vhd b/special/uart_trans.vhd
index 3b5f3ab8b21b08856e9d595fc3804baea40cd3b0..01967dc368fdaf75156c835bfd6d7c19e416a6ae 100644 (file)
--- a/special/uart_trans.vhd
+++ b/special/uart_trans.vhd
@@ -85,7 +85,7 @@ DEBUG(3) <= '0';
     end if;
 
     
-    if clk_div_counter = x"0000" then
+    if clk_div_counter = x"0001" then
       symbol_start_pulse <= '1';
     else 
       symbol_start_pulse <= '0';
@@ -107,11 +107,13 @@ DEBUG(3) <= '0';
     
     case state is
       when idle =>
+        rst_clk_div_counter <= '1';
+        ready_sig <= '1';
         if SEND = '1' then
           state <= transmitting;
           symbol_counter <= x"0";
           -- capture the byte at the parallel input
-          tx_shift_register(8 downto 1) <= DATA_IN;
+          tx_shift_register <= '1' & DATA_IN & '0';
           ready_sig <= '0';
         end if;
       
@@ -119,18 +121,16 @@ DEBUG(3) <= '0';
         if symbol_start_pulse = '1' then
           if symbol_counter <= 9 then -- transmission process
             symbol <= tx_shift_register(to_integer(symbol_counter));
-            symbol_counter <= symbol_counter + 1;
           end if;
-          
-        end if;
-        if symbol_counter = 10 then -- pulse #10 (1 start, 8 data, 1 stop) has been sent
-          --, time to go to idle mode again
-          -- pull the tx line high again, actually obsolete, because stop bit is 1
-          symbol <= '1';
-          ready_sig <= '1';
-          state <= idle;
-        end if;
-    
+
+          symbol_counter <= symbol_counter + 1;
+          if symbol_counter = 10 then -- pulse #10 (1 start, 8 data, 1 stop) has been sent
+            --, time to go to idle mode again
+            -- pull the tx line high again, actually obsolete, because stop bit is 1
+            symbol <= '1';
+            state <= idle;
+          end if;
+        end if;    
     end case; 
     
     -- reset clock divider counters when reset signal is on