changed compile projects'

diff --git a/linkdesignfiles.sh b/linkdesignfiles.sh
index 5e032f9a8c4c9d280a64843ca06ed6151c82807c..0edd4561959a3586e1ae81ceb76b98610c396d81 120000 (symlink)
--- a/linkdesignfiles.sh
+++ b/linkdesignfiles.sh
@@ -1 +1 @@
-/d/jspc22/trb/cvs/trb3/base/linkdesignfiles.sh
\ No newline at end of file
+../trb3/base/linkdesignfiles.sh
\ No newline at end of file

diff --git a/soda_source/compile_periph_frankfurt.pl b/soda_source/compile_periph_frankfurt.pl
index 7b30f33984cd374e11f11cad95daa80211c4290d..6b520ec587794bcf89c7aaafb02dd30f0f5e744e 100755 (executable)
--- a/soda_source/compile_periph_frankfurt.pl
+++ b/soda_source/compile_periph_frankfurt.pl
@@ -39,7 +39,7 @@ my $SPEEDGRADE="8";
 
 
 #create full lpf file
-system("cp ../base/trb3_periph_hub.lpf workdir/$TOPNAME.lpf");
+system("cp ../../trb3/base/trb3_periph_hub.lpf workdir/$TOPNAME.lpf");
 #system("cat ../tdc_releases/tdc_v1.1.1/tdc_constraints.lpf >> workdir/$TOPNAME.lpf");
 system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
 

diff --git a/soda_source/project/SODA_source.ldf b/soda_source/project/SODA_source.ldf
index d704f732d61c3ae92f85c978e67fac2aac79524c..f3daabf6292aea2242891dd728786d4ed2a4d781 100644 (file)
--- a/soda_source/project/SODA_source.ldf
+++ b/soda_source/project/SODA_source.ldf
@@ -12,7 +12,7 @@
         <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
@@ -237,64 +237,23 @@
         <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/BusHandler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Channel.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Channel_200.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Readout.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/TDC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/up_counter.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+
         <Source name="trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
             <Options top_module="trb3_periph_sodasource"/>
         </Source>
-        <Source name="../tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="soda_intercept.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../source/soda_intercept.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="trb3_periph_sodasource.lpf" type="Logic Preference" type_short="LPF">
+        <Source name="../trb3_periph_sodasource.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
     </Implementation>

diff --git a/soda_source/trb3_periph_sodasource.prj b/soda_source/trb3_periph_sodasource.prj
index 7c4698d11f8283bc8f9c2369cb4b179468a36833..91aeffb18c4bd3931138775e9caa9992e89ac806 100644 (file)
--- a/soda_source/trb3_periph_sodasource.prj
+++ b/soda_source/trb3_periph_sodasource.prj
@@ -54,7 +54,7 @@ impl -active "workdir"
 add_file -vhdl -lib work "version.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+add_file -vhdl -lib "work" "../../trb3/base/trb3_components.vhd"
 
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
@@ -151,30 +151,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-
-
-
-###############
-#Change path to tdc release also in compile script!
-###############
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd"
-#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
+add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in200_out100.vhd"
+
+
 
 add_file -vhdl -lib "work" "trb3_periph_sodasource.vhd"
 

diff --git a/soda_source/workdir/.gitignore b/soda_source/workdir/.gitignore
index 0a52d36b97d8c5be52e446a10182886ce57529de..ad0fa125f75d1de0ad9f2200fb94cfebc89a5245 100644 (file)
--- a/soda_source/workdir/.gitignore
+++ b/soda_source/workdir/.gitignore
@@ -1,4 +1,5 @@
 *
+run_options.txt
 
 !*txt
 !pmi*ngo

diff --git a/soft/README.txt b/soft/README.txt
new file mode 100644 (file)
index 0000000..1bb8803
--- /dev/null
+++ b/soft/README.txt
@@ -0,0 +1 @@
+The place for all Soda related scripts.