<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 08 23:14:15.031" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 04 16:09:21.103" version="5.6" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_nx_clk250.lpc" type="lpc" modified="2014 04 08 23:14:13.000"/>
- <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2014 04 08 23:14:13.000"/>
- <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2014 04 08 23:14:13.000"/>
+ <File name="pll_nx_clk250.lpc" type="lpc" modified="2014 08 04 16:09:19.000"/>
+ <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2014 08 04 16:09:19.000"/>
+ <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2014 08 04 16:09:19.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.3
+CoreRevision=5.6
ModuleName=pll_nx_clk250
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/08/2014
-Time=23:14:13
+Date=08/04/2014
+Time=16:09:19
[Parameters]
Verilog=0
;DelayControl=No
EnCLKOS=0
ClkOSBp=0
-EnCLKOK=0
+EnCLKOK=1
ClkOKBp=0
enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module Version: 5.6
+--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw
--- Tue Apr 8 23:14:13 2014
+-- Mon Aug 4 16:09:19 2014
library IEEE;
use IEEE.std_logic_1164.all;
CLK: in std_logic;
RESET: in std_logic;
CLKOP: out std_logic;
+ CLKOK: out std_logic;
LOCK: out std_logic);
attribute dont_touch : boolean;
attribute dont_touch of pll_nx_clk250 : entity is true;
end component;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "125.000000";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo,
DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo,
FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo,
- FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
+ FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>CLKOK,
CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
CLKOP <= CLKOP_t;
-----------------------------------------------------------------------------
- adc_ddr_generic_1: adc_ddr_generic
+ adc_ddr_generic_1: entity work.adc_ddr_generic
port map (
clk_0 => ADC0_DCLK_IN,
clk_1 => ADC1_DCLK_IN,
-- Tansfer to CLK_IN
-----------------------------------------------------------------------------
- fifo_adc_48to48_dc_1: fifo_adc_48to48_dc
+ fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc
port map (
Data(11 downto 0) => adc0_data_m(0),
Data(23 downto 12) => adc0_data_m(1),
-----------------------------------------------------------------------------
- fifo_adc_48to48_dc_2: fifo_adc_48to48_dc
+ fifo_adc_48to48_dc_2: entity work.fifo_adc_48to48_dc
port map (
Data(11 downto 0) => adc1_data_m(0),
Data(23 downto 12) => adc1_data_m(1),
-----------------------------------------------------------------------------
- ram_fifo_delay_256x44_1: ram_fifo_delay_256x44
+ ram_fifo_delay_256x44_1: entity work.ram_fifo_delay_256x44
port map (
WrAddress => write_address,
RdAddress => read_address,
port(
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ NX_DATA_CLK_IN : in std_logic;
TRIGGER_IN : in std_logic;
NX_ONLINE_IN : in std_logic;
NX_CLOCK_ON_IN : in std_logic;
-
+
-- nXyter Ports
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_TIMESTAMP_RESET_OUT : out std_logic;
-----------------------------------------------------------------------------
-- NX_TIMESTAMP_IN Process
+ signal fifo_fw_reset_i : std_logic;
+ signal fifo_fw_write_enable : std_logic;
+ signal fifo_fw_read_enable : std_logic;
+ signal fifo_fw_empty : std_logic;
+ signal fifo_fw_full : std_logic;
+
signal nx_timestamp_delay_f : unsigned(2 downto 0);
signal nx_timestamp_delay : unsigned(2 downto 0);
signal nx_shift_register_delay : std_logic_vector(5 downto 0);
+ signal nx_frame_word_fff : std_logic_vector(7 downto 0);
signal nx_frame_word_ff : std_logic_vector(7 downto 0);
signal nx_frame_word_f : std_logic_vector(7 downto 0);
signal nx_frame_word_s : std_logic_vector(7 downto 0);
-- Reset Domain Transfers
signal reset_nx_timestamp_clk_in_ff : std_logic;
signal reset_nx_timestamp_clk_in_f : std_logic;
- signal RESET_NX_DATA_CLK_IN : std_logic;
+ signal RESET_NX_DATA_CLK_IN : std_logic;
signal debug_state : std_logic_vector(3 downto 0);
signal debug_frame_on : std_logic;
attribute syn_keep of nx_frame_word_delay_f : signal is true;
attribute syn_keep of nx_frame_word_delay : signal is true;
- attribute syn_keep of nx_frame_word_f : signal is true;
+ attribute syn_keep of nx_frame_word_ff : signal is true;
- attribute syn_keep of nx_frame_word_delay_rr : signal is true;
- attribute syn_keep of nx_frame_word_delay_r : signal is true;
+ --attribute syn_keep of nx_frame_word_delay_rr : signal is true;
+ --attribute syn_keep of nx_frame_word_delay_r : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true;
attribute syn_preserve of nx_frame_word_delay_f : signal is true;
attribute syn_preserve of nx_frame_word_delay : signal is true;
- attribute syn_preserve of nx_frame_word_f : signal is true;
+ attribute syn_preserve of nx_frame_word_ff : signal is true;
- attribute syn_preserve of nx_frame_word_delay_rr : signal is true;
- attribute syn_preserve of nx_frame_word_delay_r : signal is true;
+ --attribute syn_preserve of nx_frame_word_delay_rr : signal is true;
+ --attribute syn_preserve of nx_frame_word_delay_r : signal is true;
begin
when rising_edge(NX_DATA_CLK_IN);
reset_nx_timestamp_clk_in_f <= reset_nx_timestamp_clk_in_ff
when rising_edge(NX_DATA_CLK_IN);
- RESET_NX_DATA_CLK_IN <= reset_nx_timestamp_clk_in_f
+ RESET_NX_DATA_CLK_IN <= reset_nx_timestamp_clk_in_f
when rising_edge(NX_DATA_CLK_IN);
-----------------------------------------------------------------------------
end if;
end process PROC_PLL_PHASE_SETUP;
- pll_adc_sampling_clk_2: pll_adc_sampling_clk
+ pll_adc_sampling_clk_2: entity work.pll_adc_sampling_clk
port map (
CLK => adc_sampling_clk,
SIGNAL_A_IN => adc_locked,
SIGNAL_OUT => adc_locked_c100
);
-
+
+ -----------------------------------------------------------------------------
-- ADC Sampling Clock Generator using a Johnson Counter
+ -----------------------------------------------------------------------------
+
PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_DATA_CLK_IN)
begin
if (rising_edge(NX_DATA_CLK_IN)) then
-- NX Timestamp Handler
-----------------------------------------------------------------------------
- -- First use two FFs for NX_TIMESTAMP_IN
- nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_DATA_CLK_IN);
- nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_DATA_CLK_IN);
-
- -- Second delay NX_TIMESTAMP_IN relatively to ADC Clock
- dynamic_shift_register8x64_1: dynamic_shift_register8x64
+ -- First: use two FFs for NX_TIMESTAMP_IN
+ nx_frame_word_fff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN);
+ nx_frame_word_ff <= nx_frame_word_fff when rising_edge(NX_TIMESTAMP_CLK_IN);
+
+ -- Second: Clock Domain Transfer to NX_DATA_CLK_IN
+ fifo_nx_frame_8to8_dc_1: entity work.fifo_nx_frame_8to8_dc
+ port map (
+ Data => nx_frame_word_ff,
+ WrClock => NX_TIMESTAMP_CLK_IN,
+ RdClock => NX_DATA_CLK_IN,
+ WrEn => fifo_fw_write_enable,
+ RdEn => fifo_fw_read_enable,
+ Reset => fifo_fw_reset_i,
+ RPReset => fifo_fw_reset_i,
+ Q => nx_frame_word_f,
+ Empty => fifo_fw_empty,
+ Full => fifo_fw_full
+ );
+ fifo_fw_reset_i <= '0'; --RESET_IN or RESET_NX_DATA_CLK_IN;
+ fifo_fw_write_enable <= not fifo_fw_full;
+ fifo_fw_read_enable <= not fifo_fw_empty;
+
+ -- Third: delay NX_TIMESTAMP_IN relatively to ADC Clock
+ dynamic_shift_register8x64_1: entity work.dynamic_shift_register8x64
port map (
Din => nx_frame_word_f,
Addr => nx_shift_register_delay,
fifo_full_rr <= fifo_full;
fifo_empty_rr <= fifo_empty;
nx_frame_synced_rr <= nx_frame_synced;
- nx_frame_word_delay_rr <= nx_frame_word_delay_f;
+ --nx_frame_word_delay_rr <= nx_frame_word_delay_f;
if (RESET_IN = '1') then
fifo_full_r <= '0';
new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr;
adc_notlock_ctr_r <= adc_notlock_ctr;
merge_error_ctr_r <= merge_error_ctr;
- nx_frame_word_delay_r <= nx_frame_word_delay_rr;
+ --nx_frame_word_delay_r <= nx_frame_word_delay_rr;
end if;
end if;
end process PROC_SLAVE_BUS_BUFFER;
std_logic_vector(nx_timestamp_delay_s);
slv_data_out_o(3) <= '0';
slv_data_out_o(5 downto 4) <=
- std_logic_vector(nx_frame_word_delay_r);
+ (others => '0');
+ -- std_logic_vector(nx_frame_word_delay_r);
slv_data_out_o(14 downto 6) <= (others => '0');
slv_data_out_o(15) <= nx_timestamp_delay_adjust;
slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr;
-----------------------------------------------------------------------------
-- Send data to FIFO
- fifo_32_data_1: fifo_32_data
+ fifo_32_data_1: entity work.fifo_32_data
port map (
Data => fifo_next_word,
Clock => CLK_IN,
SMALL: if (BUS_WIDTH = 7) generate
- ram_dp_COUNTER_HIST: ram_dp_128x40
+ ram_dp_COUNTER_HIST: entity work.ram_dp_128x40
port map (
WrAddress => write_address_hist,
RdAddress => read_address_hist,
Q(39 downto 32) => read_data_ctr_hist
);
- ram_dp_RESULT_HIST: ram_dp_128x32
+ ram_dp_RESULT_HIST: entity work.ram_dp_128x32
port map (
WrAddress => write_address,
RdAddress => read_address,
LARGE: if (BUS_WIDTH = 9) generate
- ram_dp_COUNTER_HIST: ram_dp_512x40
+ ram_dp_COUNTER_HIST: entity work.ram_dp_512x40
port map (
WrAddress => write_address_hist,
RdAddress => read_address_hist,
Q(39 downto 32) => read_data_ctr_hist
);
- ram_dp_RESULT_HIST: ram_dp_512x32
+ ram_dp_RESULT_HIST: entity work.ram_dp_512x32
port map (
WrAddress => write_address,
RdAddress => read_address,
CLK_IN : in std_logic;
RESET_IN : in std_logic;
CLK_NX_MAIN_IN : in std_logic;
+ NX_DATA_CLK_IN : in std_logic;
CLK_ADC_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
SPI_SCLK_OUT : out std_logic;
SPI_SDIO_INOUT : inout std_logic;
SPI_CSB_OUT : out std_logic;
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_RESET_OUT : out std_logic;
NX_TESTPULSE_OUT : out std_logic;
);
end component;
-component adc_ddr_generic
- port (
- clk_0 : in std_logic;
- clk_1 : in std_logic;
- clkdiv_reset : in std_logic;
- eclk : in std_logic;
- reset_0 : in std_logic;
- reset_1 : in std_logic;
- sclk : out std_logic;
- datain_0 : in std_logic_vector(4 downto 0);
- datain_1 : in std_logic_vector(4 downto 0);
- q_0 : out std_logic_vector(19 downto 0);
- q_1 : out std_logic_vector(19 downto 0)
- );
-end component;
-
-component ddr_generic_single
- port (
- clk_0 : in std_logic;
- clkdiv_reset : in std_logic;
- eclk : in std_logic;
- reset_0 : in std_logic;
- sclk : out std_logic;
- datain_0 : in std_logic_vector(4 downto 0);
- q_0 : out std_logic_vector(19 downto 0)
- );
-end component;
-
-component fifo_adc_48to48_dc
- port (
- Data : in std_logic_vector(47 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(47 downto 0);
- Empty : out std_logic;
- Full : out std_logic
- );
-end component;
-
-------------------------------------------------------------------------------
-- TRBNet Registers
-------------------------------------------------------------------------------
);
end component;
-component clock10MHz
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
component fifo_data_stream_44to44_dc
port (
Data : in std_logic_vector(43 downto 0);
);
end component;
-component dynamic_shift_register8x64
- port (
- Din : in std_logic_vector(7 downto 0);
- Addr : in std_logic_vector(5 downto 0);
- Clock : in std_logic;
- ClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(7 downto 0)
- );
-end component;
-
-component ram_fifo_delay_256x44
- port (
- WrAddress : in std_logic_vector(7 downto 0);
- RdAddress : in std_logic_vector(7 downto 0);
- Data : in std_logic_vector(43 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(43 downto 0)
- );
-end component;
-
component fifo_44_data_delay_my
port (
Data : in std_logic_vector(43 downto 0);
);
end component;
-component fifo_32_data
- port (
- Data : in std_logic_vector(31 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- AmFullThresh : in std_logic_vector(10 downto 0);
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
- );
-end component;
-
component nx_data_receiver
generic (
DEBUG_ENABLE : boolean
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ NX_DATA_CLK_IN : in std_logic;
TRIGGER_IN : in std_logic;
NX_ONLINE_IN : in std_logic;
NX_CLOCK_ON_IN : in std_logic;
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_TIMESTAMP_RESET_OUT : out std_logic;
ADC_CLK_DAT_IN : in std_logic;
);
end component;
-component ram_dp_128x40
- port (
- WrAddress : in std_logic_vector(6 downto 0);
- RdAddress : in std_logic_vector(6 downto 0);
- Data : in std_logic_vector(39 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(39 downto 0)
- );
-end component;
-
-component ram_dp_128x32
- port (
- WrAddress : in std_logic_vector(6 downto 0);
- RdAddress : in std_logic_vector(6 downto 0);
- Data : in std_logic_vector(31 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(31 downto 0)
- );
-end component;
-
-component ram_dp_512x40
- port (
- WrAddress : in std_logic_vector(8 downto 0);
- RdAddress : in std_logic_vector(8 downto 0);
- Data : in std_logic_vector(39 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(39 downto 0)
- );
-end component;
-
-component ram_dp_512x32
- port (
- WrAddress : in std_logic_vector(8 downto 0);
- RdAddress : in std_logic_vector(8 downto 0);
- Data : in std_logic_vector(31 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(31 downto 0)
- );
-end component;
-
-------------------------------------------------------------------------------
component level_to_pulse
);
end component;
--------------------------------------------------------------------------------
--- PLLs
--------------------------------------------------------------------------------
-
-component pll_nx_clk250
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_adc_clk
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_adc_sampling_clk
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- FINEDELB0 : in std_logic;
- FINEDELB1 : in std_logic;
- FINEDELB2 : in std_logic;
- FINEDELB3 : in std_logic;
- DPHASE0 : in std_logic;
- DPHASE1 : in std_logic;
- DPHASE2 : in std_logic;
- DPHASE3 : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
component nx_fpga_timestamp
port (
CLK_IN : in std_logic;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
CLK_NX_MAIN_IN : in std_logic;
+ NX_DATA_CLK_IN : in std_logic;
CLK_ADC_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
SPI_CSB_OUT : out std_logic;
-- nXyter Timestamp Ports
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_RESET_OUT : out std_logic;
NX_TESTPULSE_OUT : out std_logic;
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+ NX_DATA_CLK_IN => NX_DATA_CLK_IN,
TRIGGER_IN => trigger_timing, -- for debugging only
NX_ONLINE_IN => nxyter_online,
NX_CLOCK_ON_IN => nxyter_clock_on,
- NX_DATA_CLK_IN => NX_DATA_CLK_IN,
+ NX_TIMESTAMP_CLK_IN => NX_TIMESTAMP_CLK_IN,
NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset,
add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd"
add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd"
+add_file -vhdl -lib "work" "cores/fifo_nx_frame_8to8_dc.vhd"
add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd"
+++ /dev/null
-trb3_periph_nx1.vhd
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+use work.nxyter_components.all;
+
+library ecp3;
+use ecp3.components.all;
+
+
+entity trb3_periph is
+ port(
+ --Clocks
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --Den Da nehmen sagt Jan midestend
+ -- , right side trigger input from fan-out
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+
+ ---------------------------------------------------------------------------
+ -- BEGIN AddonBoard nXyter
+ ---------------------------------------------------------------------------
+ --Connections to NXYTER-FEB 1
+
+ NX1_RESET_OUT : out std_logic;
+ NX1_I2C_SDA_INOUT : inout std_logic;
+ NX1_I2C_SCL_INOUT : inout std_logic;
+ NX1_I2C_SM_RESET_OUT : inout std_logic;
+ NX1_I2C_REG_RESET_OUT : out std_logic;
+ NX1_SPI_SCLK_OUT : out std_logic;
+ NX1_SPI_SDIO_INOUT : inout std_logic;
+ NX1_SPI_CSB_OUT : out std_logic;
+ NX1_DATA_CLK_IN : in std_logic;
+ NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX1_MAIN_CLK_OUT : out std_logic;
+ NX1_TESTPULSE_OUT : out std_logic;
+ NX1_TS_HOLD_OUT : out std_logic;
+ NX1_ADC_FCLK_IN : in std_logic;
+ NX1_ADC_DCLK_IN : in std_logic;
+ NX1_ADC_SAMPLE_CLK_OUT : out std_logic;
+ NX1_ADC_A_IN : in std_logic;
+ NX1_ADC_B_IN : in std_logic;
+ NX1_ADC_NX_IN : in std_logic;
+ NX1_ADC_D_IN : in std_logic;
+ NX1B_ADC_FCLK_IN : in std_logic;
+ NX1B_ADC_DCLK_IN : in std_logic;
+ NX1B_ADC_A_IN : in std_logic;
+ NX1B_ADC_B_IN : in std_logic;
+ NX1B_ADC_NX_IN : in std_logic;
+ NX1B_ADC_D_IN : in std_logic;
+
+ ---------------------------------------------------------------------------
+ -- END AddonBoard nXyter
+ ---------------------------------------------------------------------------
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0);
+ NX1_DEBUG_LINE : out std_logic_vector(15 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ --important signals
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is false;
+ attribute syn_useioff of NX1_DEBUG_LINE : signal is false;
+ --attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of DAC_SDO : signal is true;
+ --attribute syn_useioff of DAC_SDI : signal is true;
+ --attribute syn_useioff of DAC_SCK : signal is true;
+ --attribute syn_useioff of DAC_CS : signal is true;
+
+
+end entity;
+
+
+architecture trb3_periph_arch of trb3_periph is
+
+ constant NUM_NXYTER : integer := 1;
+
+ -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
+ attribute ODDRAPPS : string;
+ attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED";
+
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 5;
+ constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i : std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_trg_statusbits_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
+ signal fee_data_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
+ signal fee_data_write_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_data_finished_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+ signal fee_almost_full_i : std_logic_vector(NUM_NXYTER-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+ signal spidac_read_en : std_logic;
+ signal spidac_write_en : std_logic;
+ signal spidac_data_in : std_logic_vector(31 downto 0);
+ signal spidac_addr : std_logic_vector(4 downto 0);
+ signal spidac_data_out : std_logic_vector(31 downto 0);
+ signal spidac_ack : std_logic;
+ signal spidac_busy : std_logic;
+
+ signal dac_cs_i : std_logic_vector(3 downto 0);
+ signal dac_sck_i : std_logic;
+ signal dac_sdi_i : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ --FPGA Test
+
+ signal time_counter : unsigned(31 downto 0);
+
+ -- SED Detection
+ signal sed_error : std_logic;
+ signal sed_din : std_logic_vector(31 downto 0);
+ signal sed_dout : std_logic_vector(31 downto 0);
+ signal sed_write : std_logic := '0';
+ signal sed_read : std_logic := '0';
+ signal sed_ack : std_logic := '0';
+ signal sed_nack : std_logic := '0';
+ signal sed_addr : std_logic_vector(15 downto 0) := (others => '0');
+
+ -- nXyter-FEB-Board Clocks
+ signal nx_main_clk : std_logic;
+ signal nx_data_clk : std_logic;
+ signal nx_pll_clk_lock : std_logic;
+ signal nx_pll_reset : std_logic;
+
+ signal NX_CLK_ADC_DAT : std_logic;
+ signal nx_pll_adc_clk_lock : std_logic;
+ signal nx1_adc_sample_clk : std_logic;
+
+ -- nXyter 1 Regio Bus
+ signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
+ signal nx1_regio_data_in : std_logic_vector (31 downto 0);
+ signal nx1_regio_data_out : std_logic_vector (31 downto 0);
+ signal nx1_regio_read_enable_in : std_logic;
+ signal nx1_regio_write_enable_in : std_logic;
+ signal nx1_regio_timeout_in : std_logic;
+ signal nx1_regio_dataready_out : std_logic;
+ signal nx1_regio_write_ack_out : std_logic;
+ signal nx1_regio_no_more_data_out : std_logic;
+ signal nx1_regio_unknown_addr_out : std_logic;
+
+ signal nx1_debug_line_o : std_logic_vector(15 downto 0);
+
+ -- Internal Trigger
+ signal fee1_trigger : std_logic;
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+ THE_MAIN_PLL : entity work.pll_in200_out100
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"49",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100_6000",
+ REGIO_INIT_ADDRESS => x"3800",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+
+ -- Feature Register, see TRB# Docu page 12
+ REGIO_INCLUDED_FEATURES => x"0101_0000_0000_0000",
+
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => NUM_NXYTER,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEB
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEB, i.e. nXyter #0
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
+ FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+ timing_trg_received_i <= TRIGGER_LEFT;
+
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000",
+ 1 => x"d100",
+ 2 => x"8000",
+ 3 => x"d500",
+ others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1,
+ 1 => 6,
+ 2 => 12,
+ 3 => 4,
+ others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
+ BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+ BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
+ BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
+ BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
+
+ BUS_READ_ENABLE_OUT(3) => sed_read,
+ BUS_WRITE_ENABLE_OUT(3) => sed_write,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => sed_din,
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => sed_addr,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => sed_dout,
+ BUS_DATAREADY_IN(3) => sed_ack,
+ BUS_WRITE_ACK_IN(3) => sed_ack,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => sed_nack,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+ -- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN
+ );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= timing_trg_received_i;
+ LED_YELLOW <= not med_stat_op(11);
+
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #1
+-----------------------------------------------------------------------------
+
+ nXyter_FEE_board_0: nXyter_FEE_board
+ generic map (
+ BOARD_ID => "01"
+ )
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ CLK_NX_MAIN_IN => nx_main_clk,
+ NX_DATA_CLK_IN => nx_data_clk,
+ CLK_ADC_IN => NX_CLK_ADC_DAT,
+ PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock,
+ PLL_ADC_DCLK_LOCK_IN => nx_pll_adc_clk_lock,
+ PLL_RESET_OUT => nx_pll_reset,
+
+ TRIGGER_OUT => fee1_trigger,
+
+ I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX1_SPI_CSB_OUT,
+
+ NX_TIMESTAMP_CLK_IN => NX1_DATA_CLK_IN,
+ NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
+
+ NX_RESET_OUT => NX1_RESET_OUT,
+ NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
+ NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT,
+
+ ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk,
+ ADC_A_IN(0) => NX1_ADC_A_IN,
+ ADC_A_IN(1) => NX1B_ADC_A_IN,
+ ADC_B_IN(0) => NX1_ADC_B_IN,
+ ADC_B_IN(1) => NX1B_ADC_B_IN,
+ ADC_NX_IN(0) => NX1_ADC_NX_IN,
+ ADC_NX_IN(1) => NX1B_ADC_NX_IN,
+ ADC_D_IN(0) => NX1_ADC_D_IN,
+ ADC_D_IN(1) => NX1B_ADC_D_IN,
+
+ TIMING_TRIGGER_IN => TRIGGER_RIGHT,
+ LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_IN => trg_invalid_i,
+ LVL1_TRG_TYPE_IN => trg_type_i,
+ LVL1_TRG_NUMBER_IN => trg_number_i,
+ LVL1_TRG_CODE_IN => trg_code_i,
+ LVL1_TRG_INFORMATION_IN => trg_information_i,
+ LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
+
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
+ FEE_DATA_OUT => fee_data_i(31 downto 0),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(0),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
+
+ REGIO_ADDR_IN => nx1_regio_addr_in,
+ REGIO_DATA_IN => nx1_regio_data_in,
+ REGIO_DATA_OUT => nx1_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+
+ DEBUG_LINE_OUT => nx1_debug_line_o
+ --DEBUG_LINE_OUT => open
+ );
+
+ TEST_LINE <= nx1_debug_line_o;
+ NX1_DEBUG_LINE <= nx1_debug_line_o;
+
+ FPGA5_COMM(10) <= fee1_trigger;
+
+ ---------------------------------------------------------------------------
+ -- SED Detection
+ ---------------------------------------------------------------------------
+
+ THE_SED : entity work.sedcheck
+ port map(
+ CLK => clk_100_i,
+ ERROR_OUT => sed_error,
+
+ DATA_IN => sed_din,
+ DATA_OUT => sed_dout,
+ WRITE_IN => sed_write,
+ READ_IN => sed_read,
+ ACK_OUT => sed_ack,
+ NACK_OUT => sed_nack,
+ ADDR_IN => sed_addr
+ );
+
+ -----------------------------------------------------------------------------
+ -- nXyter Main and ADC Clocks
+ -----------------------------------------------------------------------------
+
+ -- nXyter Main Clock (250MHz)
+ pll_nx_clk250_1: entity work.pll_nx_clk250
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ RESET => nx_pll_reset,
+ CLKOP => nx_main_clk,
+ CLKOK => nx_data_clk,
+ LOCK => nx_pll_clk_lock
+ );
+
+ -- Port FF for Nxyter Main Clocks
+ THE_NX_MAIN_ODDR_1: ODDRXD1
+ port map(
+ SCLK => nx_main_clk,
+ DA => '1',
+ DB => '0',
+ Q => NX1_MAIN_CLK_OUT
+ );
+
+ NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk;
+
+ -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
+ -- based on same ClockSource as nXyter Main Clock)
+ pll_adc_clk_1: entity work.pll_adc_clk
+ port map (
+ CLK => CLK_PCLK_RIGHT,
+ RESET => nx_pll_reset,
+ CLKOP => NX_CLK_ADC_DAT,
+ LOCK => nx_pll_adc_clk_lock
+ );
+
+end architecture;
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
- USE PRIMARY NET "nx_main_clk_c";
- USE PRIMARY NET "clk_100_i_c";
- USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+ USE PRIMARY NET "nx_main_clk_c";
+ USE PRIMARY NET "nx_data_clk_c";
+ USE PRIMARY NET "clk_100_i_c";
+ USE PRIMARY NET "CLK_PCLK_RIGHT_c";
#################################################################
# Reset Nets
PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c";
DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 0.5 ns HOLD 0.5 ns CLKPORT="NX1_DATA_CLK_IN";
+INPUT_SETUP GROUP "NX1_IN" 1.3 ns HOLD 1.3 ns CLKPORT="NX1_DATA_CLK_IN";
UGROUP NXYTER1 BBOX 100 70
BLKNAME nXyter_FEE_board_0;
-w
-i 2
-l 5
--n 20
+-n 2
-t 5
-s 1
-c 1
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-use work.nxyter_components.all;
-
-library ecp3;
-use ecp3.components.all;
-
-
-entity trb3_periph is
- port(
- --Clocks
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- --Trigger
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- TRIGGER_RIGHT : in std_logic; --Den Da nehmen sagt Jan midestend
- -- , right side trigger input from fan-out
- --Serdes
- CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- SERDES_INT_TX : out std_logic_vector(3 downto 0);
- SERDES_INT_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
-
- ---------------------------------------------------------------------------
- -- BEGIN AddonBoard nXyter
- ---------------------------------------------------------------------------
- --Connections to NXYTER-FEB 1
-
- NX1_RESET_OUT : out std_logic;
- NX1_I2C_SDA_INOUT : inout std_logic;
- NX1_I2C_SCL_INOUT : inout std_logic;
- NX1_I2C_SM_RESET_OUT : inout std_logic;
- NX1_I2C_REG_RESET_OUT : out std_logic;
- NX1_SPI_SCLK_OUT : out std_logic;
- NX1_SPI_SDIO_INOUT : inout std_logic;
- NX1_SPI_CSB_OUT : out std_logic;
- NX1_DATA_CLK_IN : in std_logic;
- NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX1_MAIN_CLK_OUT : out std_logic;
- NX1_TESTPULSE_OUT : out std_logic;
- NX1_TS_HOLD_OUT : out std_logic;
- NX1_ADC_FCLK_IN : in std_logic;
- NX1_ADC_DCLK_IN : in std_logic;
- NX1_ADC_SAMPLE_CLK_OUT : out std_logic;
- NX1_ADC_A_IN : in std_logic;
- NX1_ADC_B_IN : in std_logic;
- NX1_ADC_NX_IN : in std_logic;
- NX1_ADC_D_IN : in std_logic;
- NX1B_ADC_FCLK_IN : in std_logic;
- NX1B_ADC_DCLK_IN : in std_logic;
- NX1B_ADC_A_IN : in std_logic;
- NX1B_ADC_B_IN : in std_logic;
- NX1B_ADC_NX_IN : in std_logic;
- NX1B_ADC_D_IN : in std_logic;
-
- ---------------------------------------------------------------------------
- -- END AddonBoard nXyter
- ---------------------------------------------------------------------------
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0);
- NX1_DEBUG_LINE : out std_logic_vector(15 downto 0)
- );
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of TRIGGER_LEFT : signal is false;
- attribute syn_useioff of TRIGGER_RIGHT : signal is false;
- --important signals
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_useioff of TEST_LINE : signal is false;
- attribute syn_useioff of NX1_DEBUG_LINE : signal is false;
- --attribute syn_useioff of INP : signal is false;
- attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
-
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
-
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of DAC_SDO : signal is true;
- --attribute syn_useioff of DAC_SDI : signal is true;
- --attribute syn_useioff of DAC_SCK : signal is true;
- --attribute syn_useioff of DAC_CS : signal is true;
-
-
-end entity;
-
-
-architecture trb3_periph_arch of trb3_periph is
-
- constant NUM_NXYTER : integer := 1;
-
- -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1
- attribute ODDRAPPS : string;
- attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED";
- -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED";
-
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 5;
- constant REGIO_NUM_CTRL_REGS : integer := 3;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- --Clock / Reset
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
-
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
-
- --LVL1 channel
- signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i : std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic_vector(NUM_NXYTER-1 downto 0);
- signal fee_trg_statusbits_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
- signal fee_data_i : std_logic_vector(NUM_NXYTER*32-1 downto 0);
- signal fee_data_write_i : std_logic_vector(NUM_NXYTER-1 downto 0);
- signal fee_data_finished_i : std_logic_vector(NUM_NXYTER-1 downto 0);
- signal fee_almost_full_i : std_logic_vector(NUM_NXYTER-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spictrl_read_en : std_logic;
- signal spictrl_write_en : std_logic;
- signal spictrl_data_in : std_logic_vector(31 downto 0);
- signal spictrl_addr : std_logic;
- signal spictrl_data_out : std_logic_vector(31 downto 0);
- signal spictrl_ack : std_logic;
- signal spictrl_busy : std_logic;
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(5 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_ack : std_logic;
- signal spidac_read_en : std_logic;
- signal spidac_write_en : std_logic;
- signal spidac_data_in : std_logic_vector(31 downto 0);
- signal spidac_addr : std_logic_vector(4 downto 0);
- signal spidac_data_out : std_logic_vector(31 downto 0);
- signal spidac_ack : std_logic;
- signal spidac_busy : std_logic;
-
- signal dac_cs_i : std_logic_vector(3 downto 0);
- signal dac_sck_i : std_logic;
- signal dac_sdi_i : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
- --FPGA Test
-
- signal time_counter : unsigned(31 downto 0);
-
- -- SED Detection
- signal sed_error : std_logic;
- signal sed_din : std_logic_vector(31 downto 0);
- signal sed_dout : std_logic_vector(31 downto 0);
- signal sed_write : std_logic := '0';
- signal sed_read : std_logic := '0';
- signal sed_ack : std_logic := '0';
- signal sed_nack : std_logic := '0';
- signal sed_addr : std_logic_vector(15 downto 0) := (others => '0');
-
- -- nXyter-FEB-Board Clocks
- signal nx_main_clk : std_logic;
- signal nx_pll_clk_lock : std_logic;
- signal nx_pll_reset : std_logic;
-
- signal NX_CLK_ADC_DAT : std_logic;
- signal nx_pll_adc_clk_lock : std_logic;
- signal nx1_adc_sample_clk : std_logic;
-
- -- nXyter 1 Regio Bus
- signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
- signal nx1_regio_data_in : std_logic_vector (31 downto 0);
- signal nx1_regio_data_out : std_logic_vector (31 downto 0);
- signal nx1_regio_read_enable_in : std_logic;
- signal nx1_regio_write_enable_in : std_logic;
- signal nx1_regio_timeout_in : std_logic;
- signal nx1_regio_dataready_out : std_logic;
- signal nx1_regio_write_ack_out : std_logic;
- signal nx1_regio_no_more_data_out : std_logic;
- signal nx1_regio_unknown_addr_out : std_logic;
-
- signal nx1_debug_line_o : std_logic_vector(15 downto 0);
-
- -- Internal Trigger
- signal fee1_trigger : std_logic;
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
- THE_MAIN_PLL : entity work.pll_in200_out100
- port map(
- CLK => CLK_PCLK_RIGHT,
- RESET => '0',
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => c_YES, --run on 200 MHz clock
- USE_125_MHZ => c_NO,
- USE_CTC => c_NO
- )
- port map(
- CLK => CLK_PCLK_RIGHT,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => SERDES_INT_RX(2),
- SD_RXD_N_IN => SERDES_INT_RX(3),
- SD_TXD_P_OUT => SERDES_INT_TX(2),
- SD_TXD_N_OUT => SERDES_INT_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => med_stat_debug,
- CTRL_DEBUG => (others => '0')
- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"49",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100_6000",
- REGIO_INIT_ADDRESS => x"3800",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 100,
- TIMING_TRIGGER_RAW => c_YES,
-
- -- Feature Register, see TRB# Docu page 12
- REGIO_INCLUDED_FEATURES => x"0101_0000_0000_0000",
-
- --Configure data handler
- DATA_INTERFACE_NUMBER => NUM_NXYTER,
- DATA_BUFFER_DEPTH => 13, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEB
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
-
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
-
- --Response from FEB, i.e. nXyter #0
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
- FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
- FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
- FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
- timing_trg_received_i <= TRIGGER_LEFT;
-
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000",
- 1 => x"d100",
- 2 => x"8000",
- 3 => x"d500",
- others => x"0000"),
- PORT_ADDR_MASK => (0 => 1,
- 1 => 6,
- 2 => 12,
- 3 => 4,
- others => 0)
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
-
- --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
- BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
- BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
- BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
- BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
- BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
- BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
-
- BUS_READ_ENABLE_OUT(3) => sed_read,
- BUS_WRITE_ENABLE_OUT(3) => sed_write,
- BUS_DATA_OUT(3*32+31 downto 3*32) => sed_din,
- BUS_ADDR_OUT(3*16+15 downto 3*16) => sed_addr,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => sed_dout,
- BUS_DATAREADY_IN(3) => sed_ack,
- BUS_WRITE_ACK_IN(3) => sed_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => sed_nack,
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
- THE_SPI_MASTER : spi_master
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => spictrl_read_en,
- BUS_WRITE_IN => spictrl_write_en,
- BUS_BUSY_OUT => spictrl_busy,
- BUS_ACK_OUT => spictrl_ack,
- BUS_ADDR_IN(0) => spictrl_addr,
- BUS_DATA_IN => spictrl_data_in,
- BUS_DATA_OUT => spictrl_data_out,
- -- SPI connections
- SPI_CS_OUT => FLASH_CS,
- SPI_SDI_IN => FLASH_DOUT,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SCK_OUT => FLASH_CLK,
- -- BRAM for read/write data
- BRAM_A_OUT => spi_bram_addr,
- BRAM_WR_D_IN => spi_bram_wr_d,
- BRAM_RD_D_OUT => spi_bram_rd_d,
- BRAM_WE_OUT => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
- -- data memory for SPI accesses
- THE_SPI_MEMORY : spi_databus_memory
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_ACK_OUT => spimem_ack,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
- -- state machine connections
- BRAM_ADDR_IN => spi_bram_addr,
- BRAM_WR_D_OUT => spi_bram_wr_d,
- BRAM_RD_D_IN => spi_bram_rd_d,
- BRAM_WE_IN => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
- THE_FPGA_REBOOT : fpga_reboot
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- DO_REBOOT => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_GREEN <= not med_stat_op(9);
- LED_ORANGE <= not med_stat_op(10);
- LED_RED <= timing_trg_received_i;
- LED_YELLOW <= not med_stat_op(11);
-
------------------------------------------------------------------------------
--- The xXyter-FEB #1
------------------------------------------------------------------------------
-
- nXyter_FEE_board_0: nXyter_FEE_board
- generic map (
- BOARD_ID => "01"
- )
- port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- CLK_NX_MAIN_IN => nx_main_clk,
- CLK_ADC_IN => NX_CLK_ADC_DAT,
- PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock,
- PLL_ADC_DCLK_LOCK_IN => nx_pll_adc_clk_lock,
- PLL_RESET_OUT => nx_pll_reset,
-
- TRIGGER_OUT => fee1_trigger,
-
- I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
- I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
- I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
- I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
-
- SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
- SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
- SPI_CSB_OUT => NX1_SPI_CSB_OUT,
-
- NX_DATA_CLK_IN => NX1_DATA_CLK_IN,
- NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
-
- NX_RESET_OUT => NX1_RESET_OUT,
- NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
- NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT,
-
- ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
- ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
- ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
- ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
- ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk,
- ADC_A_IN(0) => NX1_ADC_A_IN,
- ADC_A_IN(1) => NX1B_ADC_A_IN,
- ADC_B_IN(0) => NX1_ADC_B_IN,
- ADC_B_IN(1) => NX1B_ADC_B_IN,
- ADC_NX_IN(0) => NX1_ADC_NX_IN,
- ADC_NX_IN(1) => NX1B_ADC_NX_IN,
- ADC_D_IN(0) => NX1_ADC_D_IN,
- ADC_D_IN(1) => NX1B_ADC_D_IN,
-
- TIMING_TRIGGER_IN => TRIGGER_RIGHT,
- LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
- LVL1_INVALID_TRG_IN => trg_invalid_i,
- LVL1_TRG_TYPE_IN => trg_type_i,
- LVL1_TRG_NUMBER_IN => trg_number_i,
- LVL1_TRG_CODE_IN => trg_code_i,
- LVL1_TRG_INFORMATION_IN => trg_information_i,
- LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
-
- FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
- FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
- FEE_DATA_OUT => fee_data_i(31 downto 0),
- FEE_DATA_WRITE_OUT => fee_data_write_i(0),
- FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
- FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
-
- REGIO_ADDR_IN => nx1_regio_addr_in,
- REGIO_DATA_IN => nx1_regio_data_in,
- REGIO_DATA_OUT => nx1_regio_data_out,
- REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
- REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
- REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
- REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
- REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
- REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
-
- DEBUG_LINE_OUT => nx1_debug_line_o
- --DEBUG_LINE_OUT => open
- );
-
- TEST_LINE <= nx1_debug_line_o;
- NX1_DEBUG_LINE <= nx1_debug_line_o;
-
- FPGA5_COMM(10) <= fee1_trigger;
-
- ---------------------------------------------------------------------------
- -- SED Detection
- ---------------------------------------------------------------------------
-
- THE_SED : entity work.sedcheck
- port map(
- CLK => clk_100_i,
- ERROR_OUT => sed_error,
-
- DATA_IN => sed_din,
- DATA_OUT => sed_dout,
- WRITE_IN => sed_write,
- READ_IN => sed_read,
- ACK_OUT => sed_ack,
- NACK_OUT => sed_nack,
- ADDR_IN => sed_addr
- );
-
- -----------------------------------------------------------------------------
- -- nXyter Main and ADC Clocks
- -----------------------------------------------------------------------------
-
- -- nXyter Main Clock (250MHz)
- pll_nx_clk250_1: entity work.pll_nx_clk250
- port map (
- CLK => CLK_PCLK_RIGHT,
- RESET => nx_pll_reset,
- CLKOP => nx_main_clk,
- LOCK => nx_pll_clk_lock
- );
-
- -- Port FF for Nxyter Main Clocks
- THE_NX_MAIN_ODDR_1: ODDRXD1
- port map(
- SCLK => nx_main_clk,
- DA => '1',
- DB => '0',
- Q => NX1_MAIN_CLK_OUT
- );
-
- NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk;
-
- -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
- -- based on same ClockSource as nXyter Main Clock)
- pll_adc_clk_1: pll_adc_clk
- port map (
- CLK => CLK_PCLK_RIGHT,
- RESET => nx_pll_reset,
- CLKOP => NX_CLK_ADC_DAT,
- LOCK => nx_pll_adc_clk_lock
- );
-
-end architecture;
jspc29 / trb3.git / commitdiff