entity MupixShiftReg is
generic(
- pixeldac_shift_length : integer := 64;
- chipdac_shift_length : integer := 16
+ pixeldac_shift_length : integer := 64
);
port(
- ck_c : in std_logic;
- ck_d : in std_logic;
+ clk1 : in std_logic;
+ clk2 : in std_logic;
sin : in std_logic;
- sout_c : out std_logic;
- sout_d : out std_logic);
+ sout : out std_logic);
end entity MupixShiftReg;
architecture RTL of MupixShiftReg is
signal pixeldac_shift_reg : std_logic_vector(pixeldac_shift_length - 1 downto 0) := (others => '0');
- signal chipdac_shift_reg : std_logic_vector(chipdac_shift_length - 1 downto 0) := (others => '0');
+ signal input_register : std_logic := '0';
begin
- process(ck_c)
+ process(clk1)
begin
- if ck_c'event and ck_c = '1' then
- pixeldac_shift_reg <= pixeldac_shift_reg(pixeldac_shift_length - 2 downto 0) & sin;
+ if clk1'event and clk1 = '1' then
+ input_register <= sin after 10 ns;
end if;
end process;
- process(ck_d)
+ process(clk2)
begin
- if ck_d'event and ck_d = '1' then
- chipdac_shift_reg <= chipdac_shift_reg(chipdac_shift_length - 2 downto 0) & sin;
+ if clk2'event and clk2 = '1' then
+ pixeldac_shift_reg <= pixeldac_shift_reg(pixeldac_shift_length - 2 downto 0) & input_register after 10 ns;
end if;
end process;
- sout_c <= pixeldac_shift_reg(pixeldac_shift_length - 1);
- sout_d <= chipdac_shift_reg(chipdac_shift_length - 1);
+ sout <= pixeldac_shift_reg(pixeldac_shift_length - 1) after 10 ns;
end architecture RTL;
architecture simulation of PixCtrlTest is
- component PixCtr
+ component PixelControl
generic(
fpga_clk_speed : integer := 1e8;
spi_clk_speed : integer := 1e4
);
port(
- clk : in std_logic;
- reset : in std_logic;
- sout_c_from_mupix : in std_logic;
- sout_d_from_mupix : in std_logic;
- mupix_ctrl : out MupixSlowControl;
+ clk : in std_logic; --clock
+ reset : in std_logic; --reset
+ mupixslctrl : out MupixSlowControl;
+ ctrl_dout : in std_logic; --serial data from mupix
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic
);
- end component PixCtr;
+ end component PixelControl;
component MupixShiftReg
generic(
- pixeldac_shift_length : integer := 64;
- chipdac_shift_length : integer := 16
+ pixeldac_shift_length : integer := 64
);
port(
- ck_c : in std_logic;
- ck_d : in std_logic;
- sin : in std_logic;
- sout_c : out std_logic;
- sout_d : out std_logic
- );
+ clk1 : in std_logic;
+ clk2 : in std_logic;
+ sin : in std_logic;
+ sout : out std_logic);
end component MupixShiftReg;
signal clk : std_logic;
signal reset : std_logic := '0';
- signal sout_c_from_mupix : std_logic := '0';
- signal sout_d_from_mupix : std_logic := '0';
+ signal sout : std_logic := '0';
signal mupix_ctrl : MupixSlowControl;
signal SLV_READ_IN : std_logic := '0';
signal SLV_WRITE_IN : std_logic := '0';
signal SLV_UNKNOWN_ADDR_OUT : std_logic;
constant clk_period : time := 10 ns;
+ constant c_shiftregister_length : integer := 80;
+ constant c_time_per_word : time := 32*clk_period*1e8/1e7;
begin
- dut : entity work.PixCtr
+ dut : entity work.PixelControl
generic map(
fpga_clk_speed => 1e8,
- spi_clk_speed => 5e7
+ spi_clk_speed => 1e7
)
port map(
clk => clk,
reset => reset,
- sout_c_from_mupix => sout_c_from_mupix,
- sout_d_from_mupix => sout_d_from_mupix,
- mupix_ctrl => mupix_ctrl,
+ ctrl_dout => sout,
+ mupixslctrl => mupix_ctrl,
SLV_READ_IN => SLV_READ_IN,
SLV_WRITE_IN => SLV_WRITE_IN,
SLV_DATA_OUT => SLV_DATA_OUT,
mupix : entity work.MupixShiftReg
generic map(
- pixeldac_shift_length => 64,
- chipdac_shift_length => 16
+ pixeldac_shift_length => c_shiftregister_length
)
port map(
- ck_c => mupix_ctrl.ck_c,
- ck_d => mupix_ctrl.ck_d,
- sin => mupix_ctrl.sin,
- sout_c => sout_c_from_mupix,
- sout_d => sout_d_from_mupix
+ clk1 => mupix_ctrl.clk1,
+ clk2 => mupix_ctrl.clk2,
+ sin => mupix_ctrl.sin,
+ sout => sout
);
clk_gen : process is
stimulus_gen : process is
begin
wait for 100 ns;
- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"004F0000",x"0083");
+ --test control through trb slow control
+-- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000011",x"0083");
+-- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000013",x"0083");
+-- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000014",x"0083");
+-- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000",x"0083");
+ --test programming with data from FIFO via FPGA state machine
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083");
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA",x"0080");
TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB",x"0080");
+ wait for 3*c_time_per_word;
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000",x"0080");
+ --test of crc checksum computation
+ wait for 1.5*c_time_per_word;
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0060", x"0083");
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083");
TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA",x"0080");
- TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCCCCCC",x"0080");
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB",x"0080");
+ TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000",x"0080");
+
wait;
end process stimulus_gen;
jspc29 / trb3.git / commitdiff