bugfix in monitoring -AW

diff --git a/combiner_calib/code_EBR/Calibration.vhd b/combiner_calib/code_EBR/Calibration.vhd
index db3fc0af46b71460ae143eab6f9ae11466ec395f..57baf25fa7add7845ef92a5f49721f02d107db40 100644 (file)
--- a/combiner_calib/code_EBR/Calibration.vhd
+++ b/combiner_calib/code_EBR/Calibration.vhd
@@ -115,17 +115,18 @@ architecture Behavioral of TDC_Calibration is
        signal FPGA_mntr_i          : array_16_16_t := (others => (others=> '0'));
        signal FPGA_cnt_mntr        : std_logic_vector( 3 downto 0);
        signal FPGA_mntr            : std_logic_vector(15 downto 0);
-       type MinMax_t is array (0 to 15, 0 to 32) of std_logic_vector(19 downto 0);
+       type MinMax_t is array (0 to 15, 0 to 63) of std_logic_vector(19 downto 0);
        signal MinMax_Monitor       : MinMax_t := (others=>(others=>(others=>'0')));
 begin
 
 --BUS Handler
-       proc_reg : process begin
+       proc_reg : process 
+       begin
        wait until rising_edge(CLK);
        BUS_TX.ack     <= '0';
        BUS_TX.nack    <= '0';
        BUS_TX.unknown <= '0';
-       Flash_flag       <= '0';
+       Flash_flag         <= '0';
 
        if BUS_RX.write = '1' then
                BUS_TX.ack <= '1';
@@ -176,22 +177,59 @@ begin
                                                                                                        BUS_TX.data(19 downto  0) <= std_logic_vector(cal_cnt_in);
                                when x"A"                       =>      BUS_TX.data <= Debug_Data_min;
                                when x"B"                       =>      BUS_TX.data <= Debug_Data_max;
+                               when x"C"                       =>      BUS_TX.data(31 downto 20) <= (others => '0');
+                                                                                                       BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,16);
+                               when x"D"                       =>      BUS_TX.data(31 downto 20) <= (others => '0');
+                                                                                                       BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,17);
+                               when x"E"                       =>      BUS_TX.data(31 downto 20) <= (others => '0');
+                                                                                                       BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,18);
+                               when x"F"                       =>      BUS_TX.data(31 downto 20) <= (others => '0');
+                                                                                                       BUS_TX.data(19 downto  0) <= MinMax_Monitor(0,19);
                                when others   =>        BUS_TX.ack               <= '0';
                                                                                                        BUS_TX.unknown <= '1';
                        end case;
-               elsif BUS_RX.addr(11 downto 4) = x"01" then
+               elsif BUS_RX.addr(11 downto 4) = x"02" then
                        BUS_TX.data(31 downto 16) <= x"0000";
                        BUS_TX.data(15 downto  0) <= FPGA_mntr_i(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
-               elsif (BUS_RX.addr(11 downto 4) = x"02" or BUS_RX.addr(11 downto 4) = x"03") then --ch 0
+               elsif BUS_RX.addr(11 downto 4) = x"03" then --ch 0
                        BUS_TX.data(31 downto 20) <= (others => '0');
                        BUS_TX.data(19 downto  0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(3 downto 0))),0);
                elsif (BUS_RX.addr(11 downto 4) > x"03") and (BUS_RX.addr(11 downto 4) < x"20")  then
                        BUS_TX.data(31 downto 20) <= (others => '0');
-                       if BUS_RX.addr(4) = '0' then -- ch1 to ch 16
-                         BUS_TX.data(19 downto  0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),to_integer(unsigned(BUS_RX.addr(3 downto 0)) + 1));
-                       else--ch17 to ch 32
-                         BUS_TX.data(19 downto  0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),to_integer(unsigned(BUS_RX.addr(3 downto 0)) + 17));
-                       end if;
+      case BUS_RX.addr(4 downto 0) is
+        when "00000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 1);
+        when "00001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 2);
+        when "00010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 3);
+        when "00011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 4);
+        when "00100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 5);
+        when "00101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 6);
+        when "00110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 7);
+        when "00111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 8);
+        when "01000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 9);
+        when "01001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),10);
+        when "01010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),11);
+        when "01011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),12);
+        when "01100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),13);
+        when "01101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),14);
+        when "01110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),15);
+        when "01111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),16);
+        when "10000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),17);
+        when "10001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),18);
+        when "10010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),19);
+        when "10011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),20);
+        when "10100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),21);
+        when "10101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),22);
+        when "10110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),23);
+        when "10111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),24);
+        when "11000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),25);
+        when "11001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),26);
+        when "11010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),27);
+        when "11011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),28);
+        when "11100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),29);
+        when "11101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),30);
+        when "11110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),31);
+        when "11111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),32);
+      end case;
                else
                        BUS_TX.ack                      <= '0';
                        BUS_TX.unknown  <= '1';
@@ -440,8 +478,8 @@ begin
        begin 
                if rising_edge(CLK) then
                  if do_cal_LIM = '1' then
-                         MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim)))( 9 downto  0) <= min_out_Lim;
-                         MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim)))(19 downto 10) <= max_out_Lim;
+                         MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))( 9 downto  0) <= min_out_Lim;
+                         MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))(19 downto 10) <= max_out_Lim;
                        end if;
                end if; 
        end process;