LOCATE COMP "WATCHDOG" SITE "E13"; # TPS_WDI
IOBUF PORT "WATCHDOG" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+#################################################################
+# Extension "Jumper"
+#################################################################
+
+ LOCATE COMP "J2_P" SITE "M1"; # LVDS J2
+ IOBUF PORT "J2_P" IO_TYPE=LVDS25;
+
#################################################################
#Misc TTL Ports
#################################################################
end process;
APL_FEE_SEND_IN <= cts_start_readout_rising;
+ APL_FEE_READ_IN <= FEE_READ_IN;
APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= buf_CTS_NUMBER_OUT;
APL_FEE_ERROR_PATTERN_IN(23 downto 16) <= buf_CTS_CODE_OUT;
- APL_FEE_ERROR_PATTERN_IN(31 downto 24) <= buf_CTS_INFORMATION_OUT;
+ APL_FEE_ERROR_PATTERN_IN(31 downto 24) <= buf_CTS_INFORMATION_OUT(7 downto 0);
APL_FEE_DTYPE_IN <= buf_CTS_READOUT_TYPE_OUT;
CTS_NUMBER_OUT <= buf_CTS_NUMBER_OUT;
end process;
+
+
+ PROC_IPU_DATA : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if IPU_READ_IN = '1' then
+ buf_IPU_DATAREADY_OUT <= '0';
+ end if;
+ if buf_APL_READ_IN(1) = '1' and buf_APL_DATAREADY_OUT(1) = '1' and buf_APL_TYP_OUT(5 downto 3) = TYPE_DAT then
+ if buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F0 or buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F2 then
+ buf_IPU_DATA_OUT(31 downto 16) <= buf_APL_DATA_OUT(31 downto 16);
+ elsif buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F1 or buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F3 then
+ buf_IPU_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT(31 downto 16);
+ buf_IPU_DATAREADY_OUT <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
end architecture;
\ No newline at end of file
--standard values for output registers
REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
--set to 0 for unused ctrl registers to save resources
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := (others => '1');
--set to 0 for each unused bit in a register
REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
-- Misc
CLK : in std_logic;
RESET : in std_logic;
- CLK_EN : in std_logic;
+ CLK_EN : in std_logic := '1';
-- Media direction port
MED_DATAREADY_OUT : out std_logic;
STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
MED_STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_MPLEX : in std_logic_vector (31 downto 0);
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0);
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
STAT_ONEWIRE : out std_logic_vector (31 downto 0);
STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0)
);
signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal HUB_CTRL_media_interfaces_off: std_logic_vector (31 downto 0);
+ signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (15 downto 0);
signal HUB_ADDRESS : std_logic_vector (15 downto 0);
signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0);
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
+ CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
end generate;
STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
STAT_FSM => stat_ipu_fsm,
+ CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
generic map(
NUM_STAT_REGS => 4,
NUM_CTRL_REGS => 3,
- INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+ INIT_CTRL_REGS => x"00000000_00000000_00009999_00000000" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
- USED_CTRL_REGS => "00011111",
- USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ USED_CTRL_REGS => "00111111",
+ USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_0000FFFF_FFFFFFFF" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
USE_DAT_PORT => c_YES,
INIT_ADDRESS => INIT_ADDRESS,
MY_ADDRESS_OUT <= HUB_ADDRESS;
STAT_REGS <= HC_STAT_REGS;
STAT_CTRL_REGS <= HC_CTRL_REGS;
+ HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+15 downto 5*32);
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
STAT_DEBUG <= buf_STAT_DEBUG;
HUB_STAT_GEN <= (others => '0');
STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
+ CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
);
end component;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
+ CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0)
);
end component;
STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
+ CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
);
end entity;
signal enable_packing : std_logic;
- type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(25 downto 0);
+ type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(31 downto 0);
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
timeout_found <= or_all(connection_timed_out);
if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' then
timeout_counter(i) <= (others => '0');
- elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then
+ elsif timeout_counter(i)(to_integer(unsigned('0'&CTRL_TIMEOUT_TIME)+to_unsigned(16,5))) = '1' then
connection_timed_out(i) <= '1';
else
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
+ CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
);
end entity;
signal register_buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0');
- type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(25 downto 0);
+ type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(31 downto 0);
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
signal timeout_found : std_logic;
+
begin
----------------------------------
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' then
timeout_counter(i) <= (others => '0');
- elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then
+ elsif timeout_counter(i)(conv_integer(('0'&CTRL_TIMEOUT_TIME)+16)) = '1' then
connection_timed_out(i) <= '1';
else
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);