-A set of control registers are assigned in order to access the basic controls,
-edit the features and debug information of the TDC. A detailed explanation of
-the control registers are given in Table \ref{tab:tdcControlReg}.
-
-\begin{center}
-\begin{longtable}{|l|l|l|p{7.6cm}|}
-\caption{The control registers of the TDC. Note that these registers have been moved from 0xc0\ldots0xc8 at the beginning of 2013.}
-\label{tab:tdcControlReg}\\
-
-\hline \multicolumn{1}{|c|}{\textbf{Address}} & \multicolumn{1}{c|}{\textbf{Name}} & \multicolumn{1}{c|}{\textbf{Bits}} & \multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline
-\endfirsthead
-
-\multicolumn{4}{c}%
-{{\bfseries \tablename\ \thetable{} -- continued from previous page}} \\
-\hline \multicolumn{1}{|c|}{\textbf{Address}} &
-\multicolumn{1}{c|}{\textbf{Name}} &
-\multicolumn{1}{c|}{\textbf{Bits}} &
-\multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline
-\endhead
-
-\hline \multicolumn{4}{|r|}{Continued on next page} \\ \hline
-\endfoot
-
-\hline \hline
-\endlastfoot
-
- 0xc800 & Basic controls & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
- & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
- & & 5 & Enables the \textit{Light Mode}. No header and reference channel information is sent if there are no recorded hits. Works only in the free streaming mode (trigger window off)\\
- & & 7-6 & reserved.\\
- & & 8 & Resets the internal counters (active high).\\
- & & 11-9 & reserved.\\
- & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; \textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). \textbf{This feature is disabled after tdc\_v2.0.}\\
- & & 13 & Used to reset the coarse counters. Setting this bit signals for the coarse counter reset but the action will take place with the arrival of the next valid trigger in order to synchronise the coarse counters in a large system.\\
- & & 27-14 & reserved.\\
- & & 31-28 & Used to divide the calibration hit frequency.\\
- & & & $Freq_{hit}=2.5~MHz/2^n$ (Oscillator frequency is increased to 20~MHz after tdc\_v2.0.1\\
-
- \hline
- 0xc801 & Trigger window & 10-0 & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
- & & 15-11 & reserved.\\
- & & 26-16 & Defines the trigger window width after the trigger with granularity of 5~ns. \textbf{ATTENTION! Minimum value can be set is x"00f".}\\
- & & 30-27 & reserved.\\
- & & 31 & Enables trigger window feature.\\
-
- \hline
- 0xc802 & Channel enable 1 & 31-0 & Enable signals for the channels 1-32.\\
-
- \hline
- 0xc803 & Channel enable 2 & 31-0 & Enable signals for the channels 33-64.\\
-
- \hline
- 0xc804 & Data transfer limit & 7-0 & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout.\\
- & Removed after version 2.1.1 & & \textbf{ATTENTION! This control is implemented only for debug reasons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\
- & & 31-8 & reserved.\\
-
- \hline
- 0xc804 & TDC channel & 6-0 & Defines the size of the channel buffer size (from tdc\_v2.1).\\
- & buffer limit & & Replaced with the ``Data limit'' register after tdc\_v2.1.1\\
- & & & Possible values 0-124\\
- & & 31-7 & reserved.\\
- \hline
- 0xc805 & Channel invert 1 & 31-0 & Invert channels 1-32\\
- \hline
- 0xc806 & Channel invert 2 & 31-0 & Invert channels 33-64\\
- \hline
-
-\end{longtable}
-\end{center}
-
-
-
-
-\begin{table}[htbp]
- \begin{center}
- \begin{tabularx}{\textwidth}{|c|c|L|}
- \hline
- Control Bits & Bit & \multicolumn{1}{c|}{Explanation}\\
- \hline \hline
- \multirow{9}{*}{x"1"} & 7-0 & Debug word of the TDC Readout FSM (see \ref{tab:tdcReadoutFsm})\\
- & 8 & REFERENCE\_TIME input\\
- & 9 & VALID\_TIMING\_TRG\_IN input\\
- & 10 & VALID\_NOTIMING\_TRG\_IN input\\
- & 11 & INVALID\_TRG\_IN input\\
- & 12 & TRG\_DATA\_VALID\_IN input\\
- & 13 & DATA\_WRITE\_OUT output\\
- & 14 & DATA\_FINISHED\_OUT output\\
- & 15 & TRG\_RELEASE\_OUT output\\
- \hline
- \multirow{7}{*}{x"2"} & 3-0 & Debug word of the TDC reference channel FSM (see \ref{tab:tdcReferenceFsm})\\
- & 4 & is set when a trigger is received\\
- & 5 & encoder start pulse\\
- & 6 & encoder finished pulse\\
- & 7 & valid timing trigger pulse from the endpoint\\
- & 8 & FIFO write pulse\\
- & 15-9 & fine time bits between 6-0\\
- \hline
- \multirow{4}{*}{x"3"} & 7-0 & Debug word of the TDC Readout FSM (see \ref{tab:tdcReadoutFsm})\\
- & 8 & REFERENCE\_TIME input\\
- & 9 & DATA\_WRITE\_OUT output\\
- & 15-9 & DATA\_OUT output bits 27-22\\
- \hline
- \end{tabularx}
- \caption{HPLA* output bitmap for different debug modes.}
- \label{tab:tdcControlRegBasicLA}
- \end{center}
-\end{table}
-
-\begin{table}[htbp]
- \begin{center}
- \begin{tabularx}{\textwidth}{|W{1cm}|rL|}
- \hline
- FSM debug & \multicolumn{2}{c|}{Explanation}\\
- \hline \hline
- x"1" & IDLE & waiting for a readout trigger\\\hline
- x"2" & WAIT\_FOR\_TRG\_WIND\_END & waiting until the end of the trigger window\\\hline
- x"3" & RD\_CH & sending read signals to the TDC channels\\\hline
- x"4" & WAIT\_FOR\_LVL1\_TRG\_A &\multirow{3}{7cm}{waiting for a trigger data validation and checking if it was a spurious trigger}\\
- x"5" & WAIT\_FOR\_LVL1\_TRG\_B &\\
- x"6" & WAIT\_FOR\_LVL1\_TRG\_C &\\\hline
- \multirow{2}{*}{x"7"} & \multirow{2}{*}{SEND\_STATUS} &\multirow{2}{7cm}{writing status information in case of a type "E" trigger or enabled \textit{Debug Mode}}\\
- & &\\\hline
- \multirow{3}{1cm}{x"8" x"9"} & \multirow{3}{4.31cm}{SEND\_TRG\_RELEASE\_A SEND\_TRG\_RELEASE\_B} &\multirow{3}{7cm}{sending a trigger release signal and waiting one extra clock cycle before going to the IDLE state}\\
- & &\\
- & &\\\hline
- \multirow{2}{*}{x"F"} & \multirow{2}{*}{OTHERS} & should never be in this state. If yes, there is a problem.\\
- \hline
- \end{tabularx}
- \caption{TDC Readout FSM debug word bitmap.}
- \label{tab:tdcReadoutFsm}
- \end{center}
-\end{table}
-
-\begin{table}[htbp]
- \begin{center}
- \begin{tabularx}{\textwidth}{|W{1cm}|rL|}
- \hline
- FSM debug & \multicolumn{2}{c|}{Explanation}\\
- \hline \hline
- x"1" & IDLE & waiting for the trigger window end\\\hline
- x"2" & WR\_CH & writing channel data information to trbnet buffers\\\hline
- x"F" & OTHERS & should never be in this state. If yes, there is a problem.\\
- \hline
- \end{tabularx}
- \caption{TDC Write-out FSM debug word bitmap.}
- \label{tab:tdcWriteoutFsm}
- \end{center}
-\end{table}
-
-\begin{table}[htbp]
- \begin{center}
- \begin{tabularx}{\textwidth}{|W{1cm}|rL|}
- \hline
- FSM debug & \multicolumn{2}{c|}{Explanation}\\
- \hline \hline
- x"01" & IDLE & waiting for a physical trigger\\\hline
- x"02" & ENCODER\_FINISHED & waiting until the encoder is finished with conversion\\\hline
- \multirow{2}{*}{x"03"} & \multirow{2}{*}{LOOK\_FOR\_VALIDITY} & waiting for a validity from the endpoint entity to write the data to the buffer\\
- \hline
- \end{tabularx}
- \caption{TDC Reference Channel FSM debug word bitmap.}
- \label{tab:tdcReferenceFsm}
- \end{center}
-\end{table}
-
-\newpage
-The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1}.
-\vspace{-0.5cm}
-
-\begin{center}
-\begin{longtable}{|l|p{2.8cm}|r|p{7.6cm}|}
-\caption{The status registers of the TDC.}
-\label{tab:tdcStatusReg1}\\
-
-\hline \multicolumn{1}{|c|}{\textbf{Address}} & \multicolumn{1}{c|}{\textbf{Name}} & \multicolumn{1}{c|}{\textbf{Bits}} & \multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline
-\endfirsthead
-
-\multicolumn{4}{c}%
-{{\bfseries \tablename\ \thetable{} -- continued from previous page}} \\
-\hline \multicolumn{1}{|c|}{\textbf{Address}} &
-\multicolumn{1}{c|}{\textbf{Name}} &
-\multicolumn{1}{c|}{\textbf{Bits}} &
-\multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline
-\endhead
-
-\hline \multicolumn{4}{|r|}{Continued on next page} \\ \hline
-\endfoot
-
-\hline \hline
-\endlastfoot
-
- 0xc100 & Basic controls & 3-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
- & & 7-4 & Debug word of the TDC write-out FSM (see \ref{tab:tdcWriteoutFsm})\\
- & & 15-8 & Implemented channel number.\\
- & & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\
- & & 27-17 & TDC version number\\
- & & 31-28 & Trigger type\\ \hline
-
- 0xc101 & Debug register & 3-0 & Debug word of the Trigger Handler FSM\\ \hline
- & & 31-4 & reserved\\ \hline
- 0xc102 & Trigger time & 31-0 & The first 32 bits of the trigger time (epoch \& coarse counter combination) measured by the reference channel\\ \hline
- 0xc103 & Trigger window controls & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\
- & & 15-11 & reserved\\
- & & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\
- & & 30-27 & reserved\\
- & & 31 & Trigger window status (1:enabled 0:disabled)\\ \hline
- 0xc104 & Trigger number & 23-0 & Number of valid triggers received\\
- & & 31-24 & reserved\\ \hline
- 0xc105 & Valid timing trigger number & 23-0 & Number of valid timing triggers received\\
- & & 31-24 & reserved\\ \hline
- 0xc106 & Valid NOtiming trigger number & 23-0 & Number of valid triggers received which are not timing triggers\\
- & & 31-24 & reserved\\ \hline
- 0xc107 & Invalid trigger number & 23-0 & Number of invalid triggers received\\
- & & 31-24 & reserved\\ \hline
- 0xc108 & Multi timing trigger number & 23-0 & Number of multi timing triggers (triggers received before trigger is released) received\\
- & & 31-24 & reserved\\ \hline
- 0xc109 & Spurious trigger number & 23-0 & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-trigger-less trigger)\\
- & & 31-24 & reserved\\ \hline
- 0xc10a & Wrong readout number & 23-0 & Number of wrong readouts due to spurious triggers\\
- & & 31-24 & reserved\\ \hline
- 0xc10b & Spike number & 23-0 & Number of spikes (pulses narrower than 40~ns) detected at the timing trigger input\\
- & & 31-24 & reserved\\ \hline
- 0xc10c & Idle time & 23-0 & Total time length, that the readout FSM waited in the idle state (with granularity of 10~ns)\\
- & & 31-24 & reserved\\ \hline
- 0xc10d & Wait time & 23-0 & Total time length, that the readout FSM waited in the wait states (with granularity of 10~ns)\\
- & & 31-24 & reserved\\ \hline
- 0xc10e & Total empty channels & 23-0 & Number of empty channels since the last reset signal\\
- & & 31-24 & reserved\\ \hline
- 0xc10f & Release number & 23-0 & Number of release signals sent\\
- & & 31-24 & reserved\\ \hline
- 0xc110 & Readout time & 23-0 & Total time length, that the readout occurred (with granularity of 10~ns)\\
- & & 31-24 & reserved\\ \hline
- 0xc111 & Time-out number & 23-0 & Number of time-outs detected (too long delay after the timing trigger)\\
- & & 31-24 & reserved\\ \hline
- 0xc112 & Finished number & 23-0 & Number of sent finished signals\\
- & & 31-24 & reserved\\ \hline
-
-
-
-\end{longtable}
-\end{center}
-
-
-\newpage
-\subsubsection{Hit Scaler Registers}
-
-In order to automatise the threshold level settings the number of hits
-detected by each channel can be reached via slow control as well as the
-current LVDS input level state. These register can be read from the bus
-address x"c0xx". The very least 8~bits are used for the channel number,
-e.g. \verb|trbcmd r 0xc001| would give the hits detected by channel 1. In the
-same register the MSB shows the logic level of the output of the input LVDS
-buffers. This bit is useful for the designs, which use the LVDS buffers as
-discriminators, e.g. cbmrich and Padiwa projects. The data format of the
-register is shown below:
-
-
-\begin{table}[ht]
- \centering
- \begin{tabular}{|W{1.2cm}|W{2.8cm}|W{9.1cm}|}
- \hline
- 1 bit & 7 bits & 24 bits\\
- LVDS level & reserved & number of hits detected\\
- \hline
- \end{tabular}
- \caption{The data format of the \textit{Hit Registers}.}
- \label{tab:tdcHitRegister}
-\end{table}
-%%% Local Variables:
-%%% mode: latex
-%%% TeX-master: "main"
-%%% End:
+ A set of control registers (0xc800) are assigned in order to access the basic
+ controls, edit the features and debug information of the TDC. A detailed
+ explanation of the control registers are given in Table
+\ref{tab:tdcControlReg}.
+ \input{TdcControlReg}
+
+ \newpage
+ Some status information and statistics of the TDC can be accessed via the
+ status registers (0xc100). The status registers of the TDC are explained in
+ Table \ref{tab:tdcStatusReg}.
+ \input{TdcStatusReg}
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