add two trigger signal outputs on CLK_RJ3/4

diff --git a/trb3_gbe/trb3_central_gbe.vhd b/trb3_gbe/trb3_central_gbe.vhd
index 3e4d3d1707eafa7d3b760100582ef9187c2347be..d5e4235c40701ceb0872fd3610367123e339430b 100644 (file)
--- a/trb3_gbe/trb3_central_gbe.vhd
+++ b/trb3_gbe/trb3_central_gbe.vhd
@@ -17,7 +17,7 @@ use work.trb_net_gbe_components.all;
 entity trb3_central_gbe is
   port(
     --Clocks
---     CLK_EXT                        : in  std_logic_vector(4 downto 3); --from RJ45
+    CLK_EXT                        : out std_logic_vector(4 downto 3); --from RJ45
     CLK_GPLL_LEFT                  : in  std_logic;  --Clock Manager 2/9, 200 MHz  <-- MAIN CLOCK
     CLK_GPLL_RIGHT                 : in  std_logic;  --Clock Manager 1/9, 125 MHz  <-- for GbE
     CLK_PCLK_LEFT                  : in  std_logic;  --Clock Fan-out, 200/400 MHz 
@@ -790,6 +790,8 @@ gen_no_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
 end generate;
 gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate 
   TRIGGER_OUT2 <= trig_gen_out_i(0);       
+  CLK_EXT(3) <= trig_gen_out_i(1);
+  CLK_EXT(4) <= trig_gen_out_i(2);
 end generate;
 
 ---------------------------------------------------------------------------
@@ -871,7 +873,7 @@ THE_CLOCK_SWITCH: entity work.clock_switch
 
 --   CLK_TEST_OUT <= clk_med_i & '0' & clk_sys_i;
   
-  CLKRJ(3 downto 0) <= "ZZZZ";
+--   CLKRJ(3 downto 0) <= "ZZZZ";