]> jspc29.x-matter.uni-frankfurt.de Git - trb3sc.git/commitdiff
First files for the backplane master
authorJan Michel <j.michel@gsi.de>
Mon, 10 Aug 2015 09:29:12 +0000 (11:29 +0200)
committerJan Michel <j.michel@gsi.de>
Mon, 10 Aug 2015 09:29:12 +0000 (11:29 +0200)
backplanemaster/compile.pl [new symlink]
backplanemaster/config.vhd [new file with mode: 0644]
backplanemaster/config_compile_frankfurt.pl [new file with mode: 0644]
backplanemaster/par.p2t [new file with mode: 0644]
backplanemaster/trb3sc_master.lpf [new file with mode: 0644]
backplanemaster/trb3sc_master.prj [new file with mode: 0644]
backplanemaster/trb3sc_master.vhd [new file with mode: 0644]
pinout/trb3sc_master.lpf [new file with mode: 0644]
template/trb3sc_basic.vhd

diff --git a/backplanemaster/compile.pl b/backplanemaster/compile.pl
new file mode 120000 (symlink)
index 0000000..4456748
--- /dev/null
@@ -0,0 +1 @@
+../scripts/compile.pl
\ No newline at end of file
diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
new file mode 100644 (file)
index 0000000..6d5f5f3
--- /dev/null
@@ -0,0 +1,116 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--Runs with 120 MHz instead of 100 MHz     
+    constant USE_120_MHZ            : integer := c_NO; 
+    constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    
+--Use sync mode, RX clock for all parts of the FPGA
+    constant USE_RXCLOCK            : integer := c_NO;
+   
+--Address settings   
+    constant INIT_ADDRESS           : std_logic_vector := x"F3CD";
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60";
+   
+
+    constant INCLUDE_UART           : integer  := c_YES;
+    constant INCLUDE_SPI            : integer  := c_YES;
+    constant INCLUDE_LCD            : integer  := c_YES;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+  constant LCD_DATA : data_t := (
+      x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+      x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+      
+      x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+      x"0a",
+      x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80",                     x"0a",                            
+      x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84",                      x"83",                     x"0a", 
+      x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82",                      x"81",                     x"0a",
+      others => x"00");
+
+
+
+
+
+
+--With GbE:
+-- for MII_NUMBER=5 (4 downlinks, 1 uplink):
+-- port 0,1,2,3: downlinks to other FPGA
+-- port 4: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL
+-- port 5: SCTRL channel on uplink to CTS
+-- port 6: SCTRL channel from GbE interface
+
+ constant INTERFACE_NUM       : integer := 5;
+ constant MII_IS_UPLINK       : hub_mii_config_t := (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0);
+ constant MII_IS_DOWNLINK     : hub_mii_config_t := (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0);
+ constant MII_IS_UPLINK_ONLY  : hub_mii_config_t := (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0);
+
+------------------------------------------------------------------------------
+--Select settings by configuration 
+------------------------------------------------------------------------------
+    type intlist_t is array(0 to 7) of integer;
+    type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+    constant HW_INFO_BASE            : unsigned(31 downto 0) := x"95000000";
+    
+    constant CLOCK_FREQUENCY_ARR  : intlist_t := (100,120, others => 0);
+    constant MEDIA_FREQUENCY_ARR  : intlist_t := (200,240, others => 0);
+                          
+  --declare constants, filled in body                          
+    constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
+    constant CLOCK_FREQUENCY      : integer;
+    constant MEDIA_FREQUENCY      : integer;
+    constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    
+    
+end;
+
+package body config is
+--compute correct configuration mode
+  
+  constant HARDWARE_INFO        : std_logic_vector(31 downto 0) := std_logic_vector(
+                                      HW_INFO_BASE );
+  constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+  constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+  
+  
+function generateIncludedFeatures return std_logic_vector is
+  variable t : std_logic_vector(63 downto 0);
+begin
+  t               := (others => '0');
+  t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
+  t(7 downto 0)   := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
+  t(11 downto 8)  := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
+  t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
+  t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
+  t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
+  t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+  t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+  t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+  return t;
+end function;  
+
+  constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
+
+end package body;
diff --git a/backplanemaster/config_compile_frankfurt.pl b/backplanemaster/config_compile_frankfurt.pl
new file mode 100644 (file)
index 0000000..6f2c88f
--- /dev/null
@@ -0,0 +1,20 @@
+TOPNAME                      => "trb3sc_master",
+lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.5_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
+synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file                => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
+include_TDC                  => 0,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+
diff --git a/backplanemaster/par.p2t b/backplanemaster/par.p2t
new file mode 100644 (file)
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--- /dev/null
@@ -0,0 +1,21 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 24
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf
new file mode 100644 (file)
index 0000000..689370f
--- /dev/null
@@ -0,0 +1,55 @@
+LOCATE COMP          "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION               "MEDIA_DOWN1" "R102C40D" 13 100;
+LOCATE UGROUP        "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ;
+
+
+MULTICYCLE TO CELL   "THE_MEDIA_4_DOWN/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_4_DOWN/sci*" 20 ns;
+MULTICYCLE TO CELL   "THE_MEDIA_4_DOWN/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO   CLKNET "THE_MEDIA_4_DOWN/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_write_i";
+BLOCK PATH TO   CLKNET "THE_MEDIA_4_DOWN/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_read_i";
+MULTICYCLE TO CLKNET    "THE_MEDIA_4_DOWN/sci_read_i" 15 ns; 
+MULTICYCLE FROM CLKNET  "THE_MEDIA_4_DOWN/sci_read_i" 15 ns; 
+MULTICYCLE TO CLKNET    "THE_MEDIA_4_DOWN/sci_write_i" 15 ns; 
+MULTICYCLE FROM CLKNET  "THE_MEDIA_4_DOWN/sci_write_i" 15 ns; 
+
+
+
+MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
+MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
+BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+MULTICYCLE TO CLKNET    "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; 
+MULTICYCLE FROM CLKNET  "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; 
+MULTICYCLE TO CLKNET    "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; 
+MULTICYCLE FROM CLKNET  "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; 
+
+MULTICYCLE TO ASIC  THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
+MAXDELAY   TO ASIC  THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
+
+
+# PROHIBIT PRIMARY   NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
+# PROHIBIT PRIMARY   NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
+# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps 
\ No newline at end of file
diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj
new file mode 100644 (file)
index 0000000..fde59c5
--- /dev/null
@@ -0,0 +1,260 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3sc_master"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3sc_master.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+#Hub
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
+
+
+#GbE
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd"
+
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+
+
+
+add_file -vhdl -lib work "./trb3sc_master.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
new file mode 100644 (file)
index 0000000..06c817e
--- /dev/null
@@ -0,0 +1,507 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define.all;
+
+entity trb3sc_master is
+  port(
+    CLK_SUPPL_PCLK       : in    std_logic; --125 MHz for GbE
+    CLK_CORE_PCLK        : in    std_logic; --Main Oscillator
+    CLK_EXT_PLL_LEFT     : in    std_logic; --External Clock
+
+    --Additional IO
+    HDR_IO               : inout std_logic_vector(10 downto 1);
+--     RJ_IO                : inout std_logic_vector( 3 downto 0);
+--     SPARE_IN             : in    std_logic_vector( 1 downto 0);  
+    BACK_GPIO            : inout std_logic_vector(15 downto 0);
+    BACK_LVDS            : inout std_logic_vector( 1 downto 0);
+    BACK_3V3             : inout std_logic_vector( 3 downto 0);
+    
+    --LED
+    LED_GREEN            : out   std_logic;
+    LED_YELLOW           : out   std_logic;
+    LED_ORANGE           : out   std_logic;
+    LED_RED              : out   std_logic;
+    LED_RJ_GREEN         : out   std_logic_vector( 1 downto 0);
+    LED_RJ_RED           : out   std_logic_vector( 1 downto 0);
+    LED_WHITE            : out   std_logic_vector( 1 downto 0);
+    LED_SFP_GREEN        : out   std_logic_vector( 1 downto 0);
+    LED_SFP_RED          : out   std_logic_vector( 1 downto 0);
+    
+    --SFP
+    SFP_LOS              : in    std_logic_vector( 1 downto 0);
+    SFP_MOD0             : in    std_logic_vector( 1 downto 0);  
+    SFP_MOD1             : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+    SFP_MOD2             : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+    SFP_TX_DIS           : out   std_logic_vector( 1 downto 0) := (others => '0');  
+    
+    SERDES_TX            : out   std_logic_vector(13 downto 0);
+    SERDES_RX            : in    std_logic_vector(13 downto 0);
+    
+--     LED_HUB_LINKOK       : out   std_logic_vector(6 downto 1);
+--     LED_HUB_RX           : out   std_logic_vector(6 downto 1);
+--     LED_HUB_TX           : out   std_logic_vector(6 downto 1);
+--     HUB_MOD0             : in    std_logic_vector(6 downto 1);
+--     HUB_MOD1             : inout std_logic_vector(6 downto 1);
+--     HUB_MOD2             : inout std_logic_vector(6 downto 1);
+--     HUB_TXDIS            : out   std_logic_vector(6 downto 1);
+--     HUB_LOS              : in    std_logic_vector(6 downto 1);
+    
+    --Serdes switch
+    PCSSW_ENSMB          : out   std_logic;
+    PCSSW_EQ             : out   std_logic_vector( 3 downto 0);
+    PCSSW_PE             : out   std_logic_vector( 3 downto 0);
+    PCSSW                : out   std_logic_vector( 7 downto 0);
+   
+    --ADC
+    ADC_CLK              : out   std_logic;
+    ADC_CS               : out   std_logic;
+    ADC_DIN              : out   std_logic;
+    ADC_DOUT             : in    std_logic;
+
+    --Flash, 1-wire, Reload
+    FLASH_CLK            : out   std_logic;
+    FLASH_CS             : out   std_logic;
+    FLASH_IN             : out   std_logic;
+    FLASH_OUT            : in    std_logic;
+    PROGRAMN             : out   std_logic;
+    ENPIRION_CLOCK       : out   std_logic;
+    TEMPSENS             : inout std_logic;
+    
+    --Test Connectors
+    TEST_LINE            : out std_logic_vector(15 downto 0)
+    );
+
+
+  attribute syn_useioff                  : boolean;
+  attribute syn_useioff of FLASH_CLK  : signal is true;
+  attribute syn_useioff of FLASH_CS   : signal is true;
+  attribute syn_useioff of FLASH_IN   : signal is true;
+  attribute syn_useioff of FLASH_OUT  : signal is true;
+
+  
+  --Serdes:                                Backplane
+  --Backplane A2,A3,A0,A1                  Slave 3,4,1,2,             A0: TrbNet from backplane
+  --AddOn     C2,C3,C0,C1,B0,B1,B2,D1(B3)  Slave --,--,5,9,8,7,6,--
+  --SFP       D0,B3(D1)                                               D0: GbE, B3: TrbNet
+  
+  
+end entity;
+
+architecture trb3sc_arch of trb3sc_master is
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+  
+  signal clk_sys, clk_full, clk_full_osc   : std_logic;
+  signal GSR_N       : std_logic;
+  signal reset_i     : std_logic;
+  signal clear_i     : std_logic;
+  
+  signal time_counter      : unsigned(31 downto 0) := (others => '0');
+  signal led               : std_logic_vector(1 downto 0);
+  signal debug_clock_reset : std_logic_vector(31 downto 0);
+
+  --Media Interface
+  signal med2int           : med2int_array_t(0 to 4);
+  signal int2med           : int2med_array_t(0 to 4);
+  signal med_stat_debug    : std_logic_vector (1*64-1  downto 0);
+  
+  signal ctrlbus_rx, bussci_rx, bussci2_rx, bustools_rx, bustc_rx  : CTRLBUS_RX;
+  signal ctrlbus_tx, bussci_tx, bussci2_tx, bustools_tx, bustc_tx  : CTRLBUS_TX;
+  
+  signal common_stat_reg         : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+  signal common_ctrl_reg         : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  
+  signal sed_error_i    : std_logic;
+  
+  signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+  signal uart_tx, uart_rx : std_logic;
+
+  signal timer          : TIMERS;
+  signal lcd_data       : std_logic_vector(511 downto 0);
+  
+  signal cts_number                   : std_logic_vector(15 downto 0);
+  signal cts_code                     : std_logic_vector(7 downto 0);
+  signal cts_information              : std_logic_vector(7 downto 0);
+  signal cts_start_readout            : std_logic;
+  signal cts_readout_type             : std_logic_vector(3 downto 0);
+  signal cts_data                     : std_logic_vector(31 downto 0);
+  signal cts_dataready                : std_logic;
+  signal cts_readout_finished         : std_logic;
+  signal cts_read                     : std_logic;
+  signal cts_length                   : std_logic_vector(15 downto 0);
+  signal cts_status_bits              : std_logic_vector(31 downto 0);
+  signal fee_data                     : std_logic_vector(15 downto 0);
+  signal fee_dataready                : std_logic;
+  signal fee_read                     : std_logic;
+  signal fee_status_bits              : std_logic_vector(31 downto 0);
+  signal fee_busy                     : std_logic;
+  signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
+  signal gsc_init_read, gsc_reply_read : std_logic;
+  signal gsc_init_dataready, gsc_reply_dataready : std_logic;
+  signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
+  signal gsc_busy : std_logic;
+  signal my_address   : std_logic_vector(15 downto 0);
+  signal mc_unique_id : std_logic_vector(63 downto 0);
+  signal reset_via_gbe : std_logic;
+  
+  signal backplane_rx_present, backplane_tx_present : std_logic_vector(8 downto 0);
+  
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;  
+  attribute syn_keep of bussci_rx     : signal is true;
+  attribute syn_preserve of bussci_rx : signal is true;  
+  attribute syn_keep of bustools_rx     : signal is true;
+  attribute syn_preserve of bustools_rx : signal is true;    
+  attribute syn_keep of bustc_rx     : signal is true;
+  attribute syn_preserve of bustc_rx : signal is true;   
+  
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+THE_CLOCK_RESET :  entity work.clock_reset_handler
+  port map(
+    INT_CLK_IN      => CLK_CORE_PCLK,
+    EXT_CLK_IN      => CLK_EXT_PLL_LEFT,
+    NET_CLK_FULL_IN => med2int(4).clk_full,
+    NET_CLK_HALF_IN => med2int(4).clk_half,
+    RESET_FROM_NET  => med2int(4).stat_op(13),
+    
+    BUS_RX          => bustc_rx,
+    BUS_TX          => bustc_tx,
+
+    RESET_OUT       => reset_i,
+    CLEAR_OUT       => clear_i,
+    GSR_OUT         => GSR_N,
+    
+    FULL_CLK_OUT    => clk_full,
+    SYS_CLK_OUT     => clk_sys,
+    REF_CLK_OUT     => clk_full_osc,
+    
+    ENPIRION_CLOCK  => ENPIRION_CLOCK,    
+    LED_RED_OUT     => LED_RJ_RED,
+    LED_GREEN_OUT   => LED_RJ_GREEN,
+    DEBUG_OUT       => debug_clock_reset
+    );
+
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+  generic map(
+    SERDES_NUM  => 3,
+    IS_SYNC_SLAVE   => c_YES
+    )
+  port map(
+    CLK                => clk_full_osc,
+    SYSCLK             => clk_sys,
+    RESET              => reset_i,
+    CLEAR              => clear_i,
+    --Internal Connection
+    MEDIA_MED2INT      => med2int(4),
+    MEDIA_INT2MED      => int2med(4),
+
+    --Sync operation
+    RX_DLM             => open,
+    RX_DLM_WORD        => open,
+    TX_DLM             => open,
+    TX_DLM_WORD        => open,
+    
+    --SFP Connection
+    SD_RXD_P_IN        => SERDES_RX(0),
+    SD_RXD_N_IN        => SERDES_RX(1),
+    SD_TXD_P_OUT       => SERDES_TX(0),
+    SD_TXD_N_OUT       => SERDES_TX(1),
+    SD_REFCLK_P_IN     => '0',
+    SD_REFCLK_N_IN     => '0',
+    SD_PRSNT_N_IN      => SFP_MOD0(1),
+    SD_LOS_IN          => SFP_LOS(1),
+    SD_TXDIS_OUT       => SFP_TX_DIS(1),
+    --Control Interface
+    BUS_RX             => bussci_rx,
+    BUS_TX             => bussci_tx,
+    -- Status and control port
+    STAT_DEBUG         => open,
+    CTRL_DEBUG         => open
+  );
+
+SFP_TX_DIS(0) <= '1';
+
+---------------------------------------------------------------------------
+-- TrbNet Downlink
+---------------------------------------------------------------------------
+THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
+  generic map(
+    IS_SYNC_SLAVE   => (c_NO, c_NO, c_NO, c_NO),
+    IS_USED         => (c_YES,c_YES ,c_YES ,c_YES)
+    )
+  port map(
+    CLK                => clk_full_osc,
+    SYSCLK             => clk_sys,
+    RESET              => reset_i,
+    CLEAR              => clear_i,
+    
+    --Internal Connection
+    MEDIA_MED2INT(0 to 3) => med2int(0 to 3),
+    MEDIA_INT2MED(0 to 3) => int2med(0 to 3),
+
+    --Sync operation
+    RX_DLM             => open,
+    RX_DLM_WORD        => open,
+    TX_DLM             => open,
+    TX_DLM_WORD        => open,
+    
+    --SFP Connection
+    --SFP Connection
+    SD_RXD_P_IN        => SERDES_RX(5 downto 2),
+    SD_RXD_N_IN        => SERDES_RX(9 downto 6),
+    SD_TXD_P_OUT       => SERDES_TX(5 downto 2),
+    SD_TXD_N_OUT       => SERDES_TX(9 downto 6),
+    
+    SD_PRSNT_N_IN      => backplane_rx_present(3 downto 0),
+    SD_LOS_IN          => backplane_rx_present(3 downto 0),
+    SD_TXDIS_OUT       => backplane_tx_present(3 downto 0),
+    
+    --Control Interface
+    BUS_RX             => bussci2_rx,
+    BUS_TX             => bussci2_tx,
+
+    -- Status and control port
+    STAT_DEBUG         => med_stat_debug(63 downto 0),
+    CTRL_DEBUG         => open
+   );
+
+gen_ready_signals : for i in 0 to 1 generate
+   backplane_rx_present(i) <= BACK_GPIO(i*4);
+   BACK_GPIO(i*4+1) <= backplane_tx_present(i);
+end generate;   
+
+---------------------------------------------------------------------------
+-- GbE
+---------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------
+-- Hub
+---------------------------------------------------------------------------
+
+  THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
+  generic map( 
+    HUB_USED_CHANNELS   => (1,1,0,1),
+    INIT_ADDRESS        => INIT_ADDRESS,
+    MII_NUMBER          => INTERFACE_NUM,
+    MII_IS_UPLINK       => MII_IS_UPLINK,
+    MII_IS_DOWNLINK     => MII_IS_DOWNLINK,
+    MII_IS_UPLINK_ONLY  => MII_IS_UPLINK_ONLY,
+    USE_ONEWIRE         => c_YES,
+    HARDWARE_VERSION    => HARDWARE_INFO,
+    INCLUDED_FEATURES   => INCLUDED_FEATURES,
+    INIT_ENDPOINT_ID    => x"0001",
+    CLOCK_FREQUENCY     => CLOCK_FREQUENCY,
+    BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+    )
+  port map( 
+    CLK                     => clk_sys,
+    RESET                   => reset_i,
+    CLK_EN                  => '1',
+
+    --Media interfacces
+    MEDIA_MED2INT           => med2int,
+    MEDIA_INT2MED           => int2med,
+    
+    --Event information coming from CTSCTS_READOUT_TYPE_OUT
+    CTS_NUMBER_OUT          => cts_number,
+    CTS_CODE_OUT            => cts_code,
+    CTS_INFORMATION_OUT     => cts_information,
+    CTS_READOUT_TYPE_OUT    => cts_readout_type,
+    CTS_START_READOUT_OUT   => cts_start_readout,
+    --Information   sent to CTS
+    --status data, equipped with DHDR
+    CTS_DATA_IN             => cts_data,
+    CTS_DATAREADY_IN        => cts_dataready,
+    CTS_READOUT_FINISHED_IN => cts_readout_finished,
+    CTS_READ_OUT            => cts_read,
+    CTS_LENGTH_IN           => cts_length,
+    CTS_STATUS_BITS_IN      => cts_status_bits,
+    -- Data from Frontends
+    FEE_DATA_OUT            => fee_data,
+    FEE_DATAREADY_OUT       => fee_dataready,
+    FEE_READ_IN             => fee_read,
+    FEE_STATUS_BITS_OUT     => fee_status_bits,
+    FEE_BUSY_OUT            => fee_busy,
+    MY_ADDRESS_IN           => my_address,
+    COMMON_STAT_REGS        => common_stat_reg, --open,
+    COMMON_CTRL_REGS        => common_ctrl_reg, --open,
+    ONEWIRE                 => TEMPSENS,
+    MY_ADDRESS_OUT          => my_address,
+    UNIQUE_ID_OUT           => mc_unique_id,
+    EXTERNAL_SEND_RESET     => reset_via_gbe,
+    
+    BUS_RX                  => ctrlbus_rx,
+    BUS_TX                  => ctrlbus_tx,
+    TIMER                   => timer,
+
+    --Gbe Sctrl Input
+    GSC_INIT_DATAREADY_IN        => gsc_init_dataready,
+    GSC_INIT_DATA_IN             => gsc_init_data,
+    GSC_INIT_PACKET_NUM_IN       => gsc_init_packet_num,
+    GSC_INIT_READ_OUT            => gsc_init_read,
+    GSC_REPLY_DATAREADY_OUT      => gsc_reply_dataready,
+    GSC_REPLY_DATA_OUT           => gsc_reply_data,
+    GSC_REPLY_PACKET_NUM_OUT     => gsc_reply_packet_num,
+    GSC_REPLY_READ_IN            => '1', --gsc_reply_read,
+    GSC_BUSY_OUT                 => gsc_busy,
+
+  --status and control ports
+    HUB_STAT_CHANNEL             => open,
+    HUB_STAT_GEN                 => open,
+    MPLEX_CTRL                   => (others => '0'),
+    MPLEX_STAT                   => open,
+    STAT_REGS                    => open,
+    STAT_CTRL_REGS               => open,
+
+    --Fixed status and control ports
+    STAT_DEBUG              => open,
+    CTRL_DEBUG              => (others => '0')
+  );
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+    generic map(
+      PORT_NUMBER      => 4,
+      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"b200", others => x"0000"),
+      PORT_ADDR_MASK   => (0 => 12,      1 => 9,       2 => 1,       3 => 9,       others => 0),
+      PORT_MASK_ENABLE => 1
+      )
+    port map(
+      CLK   => clk_sys,
+      RESET => reset_i,
+
+      REGIO_RX  => ctrlbus_rx,
+      REGIO_TX  => ctrlbus_tx,
+      
+      BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+      BUS_RX(1) => bussci_rx,   --SCI Serdes
+      BUS_RX(2) => bustc_rx,    --Clock switch
+      BUS_RX(3) => bussci2_rx,
+      BUS_TX(0) => bustools_tx,
+      BUS_TX(1) => bussci_tx,
+      BUS_TX(2) => bustc_tx,
+      BUS_TX(3) => bussci2_tx,
+      STAT_DEBUG => open
+      );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+  THE_TOOLS: entity work.trb3sc_tools 
+    port map(
+      CLK         => clk_sys,
+      RESET       => reset_i,
+      
+      --Flash & Reload
+      FLASH_CS    => FLASH_CS,
+      FLASH_CLK   => FLASH_CLK,
+      FLASH_IN    => FLASH_OUT,
+      FLASH_OUT   => FLASH_IN,
+      PROGRAMN    => PROGRAMN,
+      REBOOT_IN   => common_ctrl_reg(15),
+      --SPI
+      SPI_CS_OUT  => spi_cs,  
+      SPI_MOSI_OUT=> spi_mosi,
+      SPI_MISO_IN => spi_miso,
+      SPI_CLK_OUT => spi_clk,
+      --Header
+      HEADER_IO   => HDR_IO,
+      --LCD
+      LCD_DATA_IN => lcd_data,
+      --ADC
+      ADC_CS      => ADC_CS,
+      ADC_MOSI    => ADC_DIN,
+      ADC_MISO    => ADC_DOUT,
+      ADC_CLK     => ADC_CLK,
+      --SED
+      SED_ERROR_OUT => sed_error_i,
+      --Slowcontrol
+      BUS_RX     => bustools_rx,
+      BUS_TX     => bustools_tx,
+      
+      DEBUG_OUT  => open
+      );      
+      
+      
+---------------------------------------------------------------------------
+-- Switches
+---------------------------------------------------------------------------
+--Serdes Select
+  PCSSW_ENSMB <= '0';
+  PCSSW_EQ    <= x"0";
+  PCSSW_PE    <= x"F";
+  PCSSW       <= "01001110"; --SFP2 on B3, AddOn on D1
+
+  
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+  LED_GREEN            <= debug_clock_reset(0);   
+  LED_ORANGE           <= debug_clock_reset(1);
+  LED_RED              <= not sed_error_i;
+  LED_YELLOW           <= debug_clock_reset(2);
+  LED_WHITE            <= led;  
+  LED_SFP_GREEN        <= not med2int(4).stat_op(9) & '1';  --SFP Link Status
+  LED_SFP_RED          <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)) & '1';  --SFP RX/TX
+  
+
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------  
+  lcd_data(15 downto 0)    <= timer.network_address;
+  lcd_data(47 downto 16)   <= timer.microsecond;
+  lcd_data(79 downto 48)   <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
+  lcd_data(511 downto 80)  <= (others => '0');   
+  
+---------------------------------------------------------------------------
+-- Backplane
+---------------------------------------------------------------------------  
+  BACK_LVDS(0) <= clk_full;
+  BACK_LVDS(1) <= clk_sys;
+  
+  
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+  process begin
+    wait until rising_edge(clk_sys);
+    time_counter <= time_counter + 1; 
+    if reset_i = '1' then
+      time_counter <= (others => '0');
+    end if;
+  end process;  
+
+  led(0) <= time_counter(26) and time_counter(16);
+  led(1) <= not reset_i;
+  
+  
+--   TEST_LINE <= med_stat_debug(15 downto 0);
+  
+end architecture;
+
+
+
diff --git a/pinout/trb3sc_master.lpf b/pinout/trb3sc_master.lpf
new file mode 100644 (file)
index 0000000..fce5299
--- /dev/null
@@ -0,0 +1,290 @@
+#################################################################\r
+# Clock I/O\r
+#################################################################\r
+LOCATE COMP "CLK_SUPPL_PCLK"                 SITE "V9";            #was SUPPL_CLOCK3_P\r
+LOCATE COMP "CLK_CORE_PCLK"                  SITE "U9";            #was "CORE_CLOCK0_P"\r
+LOCATE COMP "CLK_EXT_PLL_LEFT"               SITE "N7";            #was "EXT_CLOCK2_P"\r
+DEFINE PORT GROUP "CLK_group" "CLK*" ;\r
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25  DIFFRESISTOR=100;\r
+\r
+\r
+#################################################################\r
+# Backplane I/O\r
+#################################################################\r
+LOCATE COMP "BACK_GPIO_0"                    SITE "C26";\r
+LOCATE COMP "BACK_GPIO_1"                    SITE "D26";\r
+LOCATE COMP "BACK_GPIO_2"                    SITE "B27";\r
+LOCATE COMP "BACK_GPIO_3"                    SITE "C27";\r
+LOCATE COMP "BACK_GPIO_4"                    SITE "D27";\r
+LOCATE COMP "BACK_GPIO_5"                    SITE "E27";\r
+LOCATE COMP "BACK_GPIO_6"                    SITE "B28";\r
+LOCATE COMP "BACK_GPIO_7"                    SITE "A28";\r
+LOCATE COMP "BACK_GPIO_8"                    SITE "A26";\r
+LOCATE COMP "BACK_GPIO_9"                    SITE "A27";\r
+LOCATE COMP "BACK_GPIO_10"                   SITE "A29";\r
+LOCATE COMP "BACK_GPIO_11"                   SITE "A30";\r
+LOCATE COMP "BACK_GPIO_12"                   SITE "H26";\r
+LOCATE COMP "BACK_GPIO_13"                   SITE "H25";\r
+LOCATE COMP "BACK_GPIO_14"                   SITE "A31";\r
+LOCATE COMP "BACK_GPIO_15"                   SITE "B31";\r
+DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ;\r
+\r
+IOBUF  PORT "BACK_GPIO_0"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_1"    IO_TYPE=LVCMOS25 PULLMODE=NONE;\r
+IOBUF  PORT "BACK_GPIO_2"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_3"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_4"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_5"    IO_TYPE=LVCMOS25 PULLMODE=NONE;\r
+IOBUF  PORT "BACK_GPIO_6"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_7"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_8"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_9"    IO_TYPE=LVCMOS25 PULLMODE=NONE;\r
+IOBUF  PORT "BACK_GPIO_10"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_11"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_12"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_13"    IO_TYPE=LVCMOS25 PULLMODE=NONE;\r
+IOBUF  PORT "BACK_GPIO_14"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+IOBUF  PORT "BACK_GPIO_15"    IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+\r
+LOCATE COMP "BACK_LVDS_0"                   SITE "V2";\r
+LOCATE COMP "BACK_LVDS_1"                   SITE "T4";\r
+# LOCATE COMP "BACK_LVDS_0_N"                   SITE "V1";\r
+# LOCATE COMP "BACK_LVDS_1_N"                   SITE "T3";\r
+DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ;\r
+IOBUF GROUP  "BACK_LVDS_group" IO_TYPE=LVDS25;\r
+\r
+LOCATE COMP "BACK_3V3_0"                    SITE "E11";\r
+LOCATE COMP "BACK_3V3_1"                    SITE "F12";\r
+LOCATE COMP "BACK_3V3_2"                    SITE "F10";\r
+LOCATE COMP "BACK_3V3_3"                    SITE "E10";\r
+DEFINE PORT GROUP "BACK_3V3_group" "BACK_3V3*" ;\r
+IOBUF GROUP  "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN;\r
+\r
+\r
+\r
+#################################################################\r
+# AddOn Connector\r
+#################################################################\r
+\r
+LOCATE COMP "LED_HUB_LINKOK_1"      SITE "AA2";    #was "DQLL0_0_P" 1\r
+LOCATE COMP "LED_HUB_RX_1"          SITE "AA1";\r
+LOCATE COMP "LED_HUB_TX_1"          SITE "AB2";    #was "DQLL0_1_P" 5\r
+LOCATE COMP "HUB_MOD0_1"        SITE "AB1";\r
+LOCATE COMP "HUB_MOD1_1"        SITE "AA4";    #was "DQLL0_2_P" 9\r
+LOCATE COMP "HUB_MOD2_1"        SITE "AA3";\r
+# LOCATE COMP "HUB_RATESEL_1"     SITE "AA10";   #was "DQSLL0_T"  13\r
+LOCATE COMP "HUB_TXDIS_1"       SITE "AB9";\r
+LOCATE COMP "HUB_LOS_1"         SITE "AA5";    #was "DQLL0_3_P" 17\r
+# LOCATE COMP "HUB_TXFAULT_1"     SITE "AB5";\r
+\r
+LOCATE COMP "LED_HUB_LINKOK_2"      SITE "Y7";     #was "DQLL0_4_P" 21\r
+LOCATE COMP "LED_HUB_RX_2"          SITE "AA7";\r
+LOCATE COMP "LED_HUB_TX_2"          SITE "AC5";    #was "DQLL2_0_P" 25\r
+LOCATE COMP "HUB_MOD0_2"        SITE "AC4";\r
+LOCATE COMP "HUB_MOD1_2"        SITE "AC2";    #was "DQLL2_1_P" 29\r
+LOCATE COMP "HUB_MOD2_2"        SITE "AC1";\r
+# LOCATE COMP "HUB_RATESEL_2"     SITE "AB4";    #was "DQLL2_2_P" 33\r
+LOCATE COMP "HUB_TXDIS_2"       SITE "AB3";\r
+LOCATE COMP "HUB_LOS_2"         SITE "AD5";    #was "DQSLL2_T"  37\r
+# LOCATE COMP "HUB_TXFAULT_2"     SITE "AE5";\r
\r
+LOCATE COMP "LED_HUB_LINKOK_3"      SITE "AE4";    #was "DQLL3_0_P" 2\r
+LOCATE COMP "LED_HUB_RX_3"          SITE "AE3";\r
+LOCATE COMP "LED_HUB_TX_3"          SITE "AB10";   #was "DQLL3_1_P" 6\r
+LOCATE COMP "HUB_MOD0_3"        SITE "AC10";\r
+LOCATE COMP "HUB_MOD1_3"        SITE "AE2";    #was "DQLL3_2_P" 10\r
+LOCATE COMP "HUB_MOD2_3"        SITE "AE1";\r
+# LOCATE COMP "HUB_RATESEL_3"     SITE "AJ1";    #was "DQSLL3_T"  14\r
+LOCATE COMP "HUB_TXDIS_3"       SITE "AK1";\r
+LOCATE COMP "HUB_LOS_3"         SITE "AD4";    #was "DQLL3_3_P" 18\r
+# LOCATE COMP "HUB_TXFAULT_3"     SITE "AD3";\r
+\r
+LOCATE COMP "LED_HUB_LINKOK_4"      SITE "AC9";    #was "DQLL3_4_P" 22\r
+LOCATE COMP "LED_HUB_RX_4"          SITE "AC8";\r
+LOCATE COMP "LED_HUB_TX_4"          SITE "Y2";     #was "DQLL1_0_P" 26\r
+LOCATE COMP "HUB_MOD0_4"        SITE "Y1";\r
+LOCATE COMP "HUB_MOD1_4"        SITE "W4";     #was "DQLL1_1_P" 30\r
+LOCATE COMP "HUB_MOD2_4"        SITE "W3";\r
+# LOCATE COMP "HUB_RATESEL_4"     SITE "W2";     #was "DQLL1_2_P" 34\r
+LOCATE COMP "HUB_TXDIS_4"       SITE "W1";\r
+LOCATE COMP "HUB_LOS_4"         SITE "W6";     #was "DQSLL1_T"  38\r
+# LOCATE COMP "HUB_TXFAULT_4"     SITE "Y6";\r
+\r
+LOCATE COMP "LED_HUB_LINKOK_5"      SITE "AD31";   #was "DQLR1_0_P" 169\r
+LOCATE COMP "LED_HUB_RX_5"          SITE "AD30";\r
+LOCATE COMP "LED_HUB_TX_5"          SITE "AB32";   #was "DQLR1_1_P" 173\r
+LOCATE COMP "HUB_MOD0_5"        SITE "AB31";\r
+LOCATE COMP "HUB_MOD1_5"        SITE "AE34";   #was "DQLR1_2_P" 177\r
+LOCATE COMP "HUB_MOD2_5"        SITE "AE33";\r
+# LOCATE COMP "HUB_RATESEL_5"     SITE "AB26";   #was "DQSLR1_T"  181\r
+LOCATE COMP "HUB_TXDIS_5"       SITE "AB25";\r
+LOCATE COMP "HUB_LOS_5"         SITE "AD33";   #was "DQLR1_3_P" 185\r
+# LOCATE COMP "HUB_TXFAULT_5"     SITE "AD34"\r
+\r
+LOCATE COMP "LED_HUB_LINKOK_6"      SITE "W30";    #was "DQLR2_0_P" 170\r
+LOCATE COMP "LED_HUB_RX_6"          SITE "W29";\r
+LOCATE COMP "LED_HUB_TX_6"          SITE "W27";    #was "DQLR2_1_P" 174\r
+LOCATE COMP "HUB_MOD0_6"        SITE "W26";\r
+LOCATE COMP "HUB_MOD1_6"        SITE "W34";    #was "DQLR2_2_P" 178\r
+LOCATE COMP "HUB_MOD2_6"        SITE "W33";\r
+# LOCATE COMP "HUB_RATESEL_6"     SITE "Y30";    #was "DQSLR2_T"  182\r
+LOCATE COMP "HUB_TXDIS_6"       SITE "AA29";\r
+LOCATE COMP "HUB_LOS_6"         SITE "Y34";    #was "DQLR2_3_P" 186\r
+# LOCATE COMP "HUB_TXFAULT_6"     SITE "Y33";\r
+\r
+\r
+DEFINE PORT GROUP "HUB_group" "HUB*" ;\r
+IOBUF GROUP "HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+DEFINE PORT GROUP "LED_HUB_group" "LED_HUB*" ;\r
+IOBUF GROUP "LED_HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+\r
+\r
+#################################################################\r
+# Pin-header IO\r
+#################################################################\r
+LOCATE COMP "HDR_IO_1"                     SITE "AP28";\r
+LOCATE COMP "HDR_IO_2"                     SITE "AN28";\r
+LOCATE COMP "HDR_IO_3"                     SITE "AP27";\r
+LOCATE COMP "HDR_IO_4"                     SITE "AN27";\r
+LOCATE COMP "HDR_IO_5"                     SITE "AM27";\r
+LOCATE COMP "HDR_IO_6"                     SITE "AL27";\r
+LOCATE COMP "HDR_IO_7"                     SITE "AH26";\r
+LOCATE COMP "HDR_IO_8"                     SITE "AG26";\r
+LOCATE COMP "HDR_IO_9"                     SITE "AM28";\r
+LOCATE COMP "HDR_IO_10"                    SITE "AL28";\r
+DEFINE PORT GROUP "HDR_group" "HDR*" ;\r
+IOBUF GROUP  "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;\r
+\r
+#################################################################\r
+# Many LED\r
+#################################################################\r
+LOCATE COMP "LED_RJ_GREEN_0"                 SITE "C25";\r
+LOCATE COMP "LED_RJ_RED_0"                   SITE "D25";\r
+LOCATE COMP "LED_GREEN"                      SITE "D24";\r
+LOCATE COMP "LED_ORANGE"                     SITE "E24";\r
+LOCATE COMP "LED_RED"                        SITE "K23";\r
+LOCATE COMP "LED_RJ_GREEN_1"                 SITE "G26";\r
+LOCATE COMP "LED_RJ_RED_1"                   SITE "G25";\r
+LOCATE COMP "LED_YELLOW"                     SITE "K24";\r
+IOBUF  PORT "LED_RJ_GREEN_0"    IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_RJ_RED_0"      IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_GREEN"         IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_ORANGE"        IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_RED"           IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_RJ_GREEN_1"    IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_RJ_RED_1"      IO_TYPE=LVCMOS25 ;\r
+IOBUF  PORT "LED_YELLOW"        IO_TYPE=LVCMOS25 ;\r
+\r
+LOCATE COMP "LED_SFP_GREEN_0"                SITE "B4";\r
+LOCATE COMP "LED_SFP_GREEN_1"                SITE "A6";\r
+LOCATE COMP "LED_SFP_RED_0"                  SITE "A3";\r
+LOCATE COMP "LED_SFP_RED_1"                  SITE "A8";\r
+DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ;\r
+IOBUF GROUP  "LED_SFP_group" IO_TYPE=LVTTL33 ;\r
+\r
+LOCATE COMP "LED_WHITE_0"                    SITE "A32";\r
+LOCATE COMP "LED_WHITE_1"                    SITE "A33";\r
+DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ;\r
+IOBUF GROUP  "LED_WHITE_group" IO_TYPE=LVTTL33 ;\r
+\r
+#################################################################\r
+# SFP Control Signals\r
+#################################################################\r
+LOCATE COMP "SFP_LOS_0"                      SITE "B6";\r
+LOCATE COMP "SFP_LOS_1"                      SITE "C9";\r
+LOCATE COMP "SFP_MOD0_0"                     SITE "A5";\r
+LOCATE COMP "SFP_MOD0_1"                     SITE "K11";\r
+LOCATE COMP "SFP_MOD1_0"                     SITE "B7";\r
+LOCATE COMP "SFP_MOD1_1"                     SITE "J11";\r
+LOCATE COMP "SFP_MOD2_0"                     SITE "A7";\r
+LOCATE COMP "SFP_MOD2_1"                     SITE "D9";\r
+LOCATE COMP "SFP_TX_DIS_0"                   SITE "D6";\r
+LOCATE COMP "SFP_TX_DIS_1"                   SITE "A9";\r
+\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
+IOBUF GROUP  "SFP_group" IO_TYPE=LVTTL33 ;\r
+\r
+\r
+\r
+#################################################################\r
+# Serdes Output Switch\r
+#################################################################\r
+LOCATE COMP "PCSSW_ENSMB"                  SITE "B3";\r
+LOCATE COMP "PCSSW_EQ_0"                   SITE "B1";\r
+LOCATE COMP "PCSSW_EQ_1"                   SITE "B2";\r
+LOCATE COMP "PCSSW_EQ_2"                   SITE "E4";\r
+LOCATE COMP "PCSSW_EQ_3"                   SITE "D4";\r
+LOCATE COMP "PCSSW_PE_0"                   SITE "C3";\r
+LOCATE COMP "PCSSW_PE_1"                   SITE "C4";\r
+LOCATE COMP "PCSSW_PE_2"                   SITE "D3";\r
+LOCATE COMP "PCSSW_PE_3"                   SITE "C2";\r
+LOCATE COMP "PCSSW_1"                      SITE "D5";\r
+LOCATE COMP "PCSSW_0"                      SITE "A2";\r
+LOCATE COMP "PCSSW_2"                      SITE "E13";\r
+LOCATE COMP "PCSSW_3"                      SITE "F13";\r
+LOCATE COMP "PCSSW_4"                      SITE "G13";\r
+LOCATE COMP "PCSSW_5"                      SITE "H14";\r
+LOCATE COMP "PCSSW_6"                      SITE "A13";\r
+LOCATE COMP "PCSSW_7"                      SITE "B13";\r
+DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ;\r
+IOBUF GROUP  "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
+\r
+\r
+#################################################################\r
+# ADC\r
+#################################################################\r
+LOCATE COMP "ADC_CLK"                        SITE "A14";    \r
+LOCATE COMP "ADC_CS"                         SITE "B14";    \r
+LOCATE COMP "ADC_DIN"                        SITE "G17";    \r
+LOCATE COMP "ADC_DOUT"                       SITE "G16";    \r
+IOBUF  PORT "ADC_CLK"  IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF  PORT "ADC_CS"   IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF  PORT "ADC_DIN"  IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF  PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+\r
+#################################################################\r
+# Flash ROM and Reboot\r
+#################################################################\r
+LOCATE COMP "FLASH_CLK"                        SITE "F34";         #was "SPI_CLK"\r
+LOCATE COMP "FLASH_CS"                         SITE "D34";         #was "SPI_CS" \r
+LOCATE COMP "FLASH_IN"                         SITE "F33";         #was "SPI_IN" \r
+LOCATE COMP "FLASH_OUT"                        SITE "F32";         #was "SPI_OUT"\r
+LOCATE COMP "PROGRAMN"                         SITE "C31";\r
+\r
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE;\r
+IOBUF  PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8  ;\r
+\r
+LOCATE COMP "ENPIRION_CLOCK"                 SITE "H23";\r
+IOBUF  PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;\r
+\r
+\r
+#################################################################\r
+# Misc\r
+#################################################################\r
+LOCATE COMP  "TEMPSENS"    SITE "J13";                             #was TEMP_OWB\r
+IOBUF  PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8  ;\r
+\r
+\r
+#################################################################\r
+# Trigger I/O\r
+#################################################################\r
+LOCATE COMP "TEST_LINE_0"                     SITE "A19";\r
+LOCATE COMP "TEST_LINE_1"                     SITE "B19";\r
+LOCATE COMP "TEST_LINE_2"                     SITE "K20";\r
+LOCATE COMP "TEST_LINE_3"                     SITE "L19";\r
+LOCATE COMP "TEST_LINE_4"                     SITE "C19";\r
+LOCATE COMP "TEST_LINE_5"                     SITE "D19";\r
+LOCATE COMP "TEST_LINE_6"                     SITE "J19";\r
+LOCATE COMP "TEST_LINE_7"                     SITE "K19";\r
+LOCATE COMP "TEST_LINE_8"                     SITE "A20";\r
+LOCATE COMP "TEST_LINE_9"                     SITE "B20";\r
+LOCATE COMP "TEST_LINE_10"                    SITE "G20";\r
+LOCATE COMP "TEST_LINE_11"                    SITE "G21";\r
+LOCATE COMP "TEST_LINE_12"                    SITE "C20";\r
+LOCATE COMP "TEST_LINE_13"                    SITE "D20";\r
+LOCATE COMP "TEST_LINE_14"                    SITE "F21";\r
+LOCATE COMP "TEST_LINE_15"                    SITE "F22";\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
\ No newline at end of file
index 049ac4370e59c40084079e6b7b7407052c412f80..2f23b8df1432584c60a8bb41685aa2b36a531426 100644 (file)
@@ -142,7 +142,6 @@ architecture trb3sc_arch of trb3sc_basic is
   signal clock_select : std_logic;
 
   signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
-  signal uart_tx, uart_rx                    : std_logic;
 
   signal timer    : TIMERS;
   signal lcd_data : std_logic_vector(511 downto 0);