tdc control registers table is updated

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index bf30bf6af5aa043bd78b60ffa7882572013ff586..0bebb065c9d1ce88f4fd2d790c33a41c4e745547 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -16,18 +16,23 @@ with logic analyser (For more details see Table
 \ref{tab:tdcControlRegBasicLA}).\\
       & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug 
 words are sent after every trigger (see \ref{sec:tdcDebug}).\\
-      & & 7-5 & reserved.\\
+      & & 5 & Enables the \textit{Light Mode}. No header and reference channel 
+information is sent if there are no recorded hits. Works only in the free 
+streaming mode (trigger window off)\\
+      & & 7-6 & reserved.\\
       & & 8 & Resets the internal counters (active high).\\
       & & 11-9 & reserved.\\
       & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; 
-\textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
+\textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). 
+This feature is disabled after tdc\_v2.0.\\
       & & 13 & Used to reset the coarse counters. Setting this bit signals for 
 the coarse counter reset but the action will take place with the arrival of the 
 next valid trigger in order to synchronise the coarse counters in a large 
 system.\\
       & & 27-14 & reserved.\\
       & & 31-28 & Used to divide the calibration hit frequency.\\
-      & & & $Freq_{hit}=2.5~MHz/2^n$\\
+      & & & $Freq_{hit}=2.5~MHz/2^n$ (Oscillator frequency is increased to 
+20~MHz after tdc\_v2.0.1\\
 
       \hline
       \multirow{10}{*}{0xc801} & \multirow{10}{*}{Trigger window}