add downsampling option to PWM module

diff --git a/io/pwm.vhd b/io/pwm.vhd
index a0045bfef722ad8c51aa94c303242f733b78fde6..805a8ba2aef8443b291b66a01b70040a79b34171 100644 (file)
--- a/io/pwm.vhd
+++ b/io/pwm.vhd
@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
 
 entity pwm_generator is
   generic(
-    CHANNELS : integer := 32
+    CHANNELS : integer := 32;
+    DOWNSAMPLE : integer range 0 to 15 := 15
     );
   port(
     CLK        : in std_logic;
@@ -39,7 +40,7 @@ signal flag      : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
 signal pwm_i     : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
 
 signal i         : integer range 0 to CHANNELS-1 := 0;
-signal clock_enable : std_logic_vector(15 downto 0) := x"0001";
+signal clock_enable : std_logic_vector(DOWNSAMPLE downto 0) := (0 => '1', others => '0');
 begin
 
 PROC_MEM : process begin
@@ -57,17 +58,23 @@ GEN_REAL_VALUES : process begin
   i <= i + 1;
 end process;
 
-process begin
-  wait until rising_edge(CLK);
-  clock_enable <= clock_enable(14 downto 0) & clock_enable(15);
-end process;
+
+gen_clock_enable : if DOWNSAMPLE /= 0 generate
+  process begin
+    wait until rising_edge(CLK);
+    clock_enable <= clock_enable(DOWNSAMPLE-1 downto 0) & clock_enable(DOWNSAMPLE);
+  end process;
+end generate;
+gen_no_clock_enable : if DOWNSAMPLE = 0 generate
+  clock_enable(0) <= '1';
+end generate;
 
 gen_channels : for i in 0 to CHANNELS-1 generate
   flag(i)      <= cnt(i)(16);
   
   process begin
     wait until rising_edge(CLK);
-    if clock_enable(i mod 16) = '1' then
+    if clock_enable(i mod (DOWNSAMPLE+1)) = '1' then
       last_flag(i) <= flag(i);
       pwm_i(i)     <= (last_flag(i) xor flag(i));
       cnt(i)       <= cnt(i) + resize(set_tmp(i),17);