spi_din : out std_logic; --serial data out
spi_ld_tmp_dac : out std_logic; --load temperature dac
spi_ld_thres : out std_logic; --load threshold and injection dac
- spi_cs_adc : out std_logic; --load adc
+ spi_cs_adc : out std_logic; --load adc
+ injection_pulse : out std_logic; --injection pulse to board
--TRB slow control
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
spi_ld_tmp_dac => spi_ld_tmp_dac,
spi_ld_thres => spi_ld_thres,
spi_ld_adc => spi_ld_adc,
+ injection_pulse => testpulse,
SLV_READ_IN => slv_read(2),
SLV_WRITE_IN => slv_write(2),
SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32),
spi_ld_tmp_dac : out std_logic; --load temperature dac
spi_ld_thres : out std_logic; --load threshold and injection dac
spi_cs_adc : out std_logic; --load adc
+ injection_pulse : out std_logic; --injection pulse to board
--TRB slow control
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
);
end component ADS1018SPI;
+ component injection_generator
+ port(
+ rst : in std_logic;
+ clk : in std_logic;
+ pulse_length : in std_logic_vector(15 downto 0);
+ pulse_start : in std_logic;
+ pulse_o : out std_logic
+ );
+ end component injection_generator;
+
constant c_bits_threshold_dacs : integer := 64;--4*16 bit of the four DACs
- signal start_write_threshold : std_logic;
+ signal start_write_threshold : std_logic := '0';
signal spi_data_in_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
signal spi_data_to_chip_threshold : std_logic;
signal spi_data_out_threshold : std_logic_vector(c_bits_threshold_dacs - 1 downto 0);
signal spi_clk_threshold : std_logic;
constant c_bits_temperature_dac : integer := 16;
- signal start_write_temperature : std_logic;
+ signal start_write_temperature : std_logic := '0';
signal spi_data_in_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
signal spi_data_to_chip_temperature : std_logic;
signal spi_data_out_temperature : std_logic_vector(c_bits_temperature_dac - 1 downto 0);
signal spi_clk_temperature_temperature : std_logic;
- signal start_write_adc : std_logic;
+ signal start_write_adc : std_logic := '0';
signal config_adc : std_logic_vector(15 downto 0);
signal spi_data_to_chip_adc : std_logic;
signal spi_data_out_adc : std_logic_vector(31 downto 0);
signal spi_clk_adc : std_logic;
-
+ signal pulse_start_i : std_logic := '0';
+ signal pulse_length_i : std_logic_vector(15 downto 0) := (others => '0');
begin
spi_clk => spi_clk_adc,
spi_cs => spi_cs_adc
);
+
+ injection_gen_1 : component injection_generator
+ port map(
+ rst => reset,
+ clk => clk,
+ pulse_length => pulse_length_i,
+ pulse_start => pulse_start_i,
+ pulse_o => injection_pulse
+ );
-----------------------------------------------------------------------------
--TRB Slave Bus
--0x0090: threshold high and low dacs, 31:16 threshold high, 15:0 threshold low
--0x0096: start write threshold and injection dacs bit
--0x0097: write config adc
--0x0098: read adc data
+ --0x0099: injection length
-----------------------------------------------------------------------------
SLV_BUS_HANDLER : process(clk)
begin -- process SLV_BUS_HANDLER
start_write_threshold <= '0';
start_write_temperature <= '0';
start_write_adc <= '0';
+ pulse_start_i <= '0';
if SLV_READ_IN = '1' then
case SLV_ADDR_IN is
when x"0098" =>
SLV_DATA_OUT <= spi_data_out_adc;
SLV_ACK_OUT <= '1';
+ when x"0099" =>
+ SLV_DATA_OUT(15 downto 0) <= pulse_length_i;
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
config_adc <= SLV_DATA_IN(15 downto 0);
start_write_adc <= '1';
SLV_ACK_OUT <= '1';
+ when x"0099" =>
+ pulse_start_i <= '1';
+ pulse_length_i <= SLV_DATA_IN(15 downto 0);
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
-----------------------------------------------------------------------------
--- MUPIX3 injection generator
---
--- Niklaus Berger, Heidelberg University
--- nberger@physi.uni-heidelberg.de
---
--- Adepted to TRBv3 Readout: Tobias Weber, University Mainz
+-- Mupix 8 injection generator
+-- Tobias Weber
+-- Ruhr Unversitaet Bochum
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity injection_generator is
port (
- rst : in std_logic;
- clk : in std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- testpulse1 : out std_logic;
- testpulse2 : out std_logic
+ rst : in std_logic;--! reset input
+ clk : in std_logic;--! clock input
+ pulse_length : in std_logic_vector(15 downto 0); --! length of injection pulse
+ pulse_start : in std_logic;--! start generation of pulse
+ pulse_o : out std_logic --! output signal to mupix board
);
end injection_generator;
architecture rtl of injection_generator is
- signal counter1 : unsigned(15 downto 0) := (others => '0');
- signal counter2 : unsigned(15 downto 0) := (others => '0');
-
- signal counter_from_slv : unsigned(31 downto 0);
- signal slv_written : std_logic_vector(1 downto 0);
-
-
- signal testpulse1_i : std_logic;
- signal testpulse2_i : std_logic;
- signal testpulse_busy : std_logic := '0';
-
-
+ type injection_generator_type is (idle, gen);
+ signal injection_generator_fsm : injection_generator_type := idle;
+ signal counter : unsigned(15 downto 0) := (others => '0');
+
begin
- process(clk, rst)
- begin
- if(rst = '1') then
-
- testpulse1_i <= '0';
- testpulse2_i <= '0';
-
- elsif rising_edge(clk) then
- if slv_written = "10" then
- counter1 <= counter_from_slv(15 downto 0);
- counter2 <= counter_from_slv(31 downto 16);
- end if;
-
- if(counter1 > x"0000") then
- testpulse1_i <= '1';
- counter1 <= counter1 - 1;
- else
- testpulse1_i <= '0';
- end if;
-
- if(counter2 > x"0000") then
- testpulse2_i <= '1';
- counter2 <= counter2 - 1;
- else
- testpulse2_i <= '0';
- end if;
-
- end if;
- end process;
-
- testpulse_busy <= '1' when testpulse2_i = '1' or testpulse1_i = '1' else '0';
-
- SLV_HANDLER : process(clk)
- begin
- if rising_edge(clk) then
- SLV_DATA_OUT <= (others => '0');
- SLV_UNKNOWN_ADDR_OUT <= '0';
- SLV_NO_MORE_DATA_OUT <= '0';
- SLV_ACK_OUT <= '0';
- slv_written <= slv_written(0) & SLV_WRITE_IN;
-
- if SLV_READ_IN = '1' then
- if SLV_ADDR_IN = x"0060" then
- SLV_DATA_OUT(31 downto 16) <= std_logic_vector(counter2);
- SLV_DATA_OUT(15 downto 0) <= std_logic_vector(counter1);
- SLV_ACK_OUT <= '1';
- else
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end if;
- end if;
-
- if SLV_WRITE_IN = '1' then
- if SLV_ADDR_IN = x"0060" then
- if testpulse_busy = '0' then
- counter_from_slv <= unsigned(SLV_DATA_IN);
- SLV_ACK_OUT <= '1';
- else
- SLV_ACK_OUT <= '1';
- end if;
-
- else
- SLV_UNKNOWN_ADDR_OUT <= '1';
- end if;
- end if;
- end if;
- end process SLV_HANDLER;
-
---Output Signals
- testpulse2 <= testpulse2_i;
- testpulse1 <= testpulse1_i;
+ injection_gen : process(clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ counter <= (others => '0');
+ injection_generator_fsm <= idle;
+ pulse_o <= '0';
+ else
+ case injection_generator_fsm is
+ when idle =>
+ pulse_o <= '0';
+ counter <= (others => '0');
+ if pulse_start = '1' then
+ injection_generator_fsm <= gen;
+ else
+ injection_generator_fsm <= idle;
+ end if;
+ when gen =>
+ pulse_o <= '1';
+ counter <= counter + 1;
+ if counter = unsigned(pulse_length) then
+ injection_generator_fsm <= idle;
+ else
+ injection_generator_fsm <= gen;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process injection_gen;
+
end rtl;
jspc29 / trb3.git / commitdiff