my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
#my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
#my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+#my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf");
system("cat ../tdc_releases/tdc_v1.1.1/tdc_constraints.lpf >> workdir/$TOPNAME.lpf");
system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' workdir/$TOPNAME.lpf");
+if($ENV{'LPF_ONLY'} == 1) {exit;}
#set -e
#set -o errexit
$c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|;
execute($c);
# IOR IO Timing Report
$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
+#execute($c);
# TWR Timing Report
$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of configuration
+------------------------------------------------------------------------------
+
+--include TDC for all four trigger input lines
+ constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
+
+--use all four SFP (1-4) as downlink to other boards.
+ constant USE_4_SFP : integer range c_NO to c_YES := c_NO;
+
+
+--Run wih 125 MHz instead of 100 MHz
+ constant USE_125_MHZ : integer range c_NO to c_YES := c_YES;
+
+------------------------------------------------------------------------------
+--End of configuration
+------------------------------------------------------------------------------
+
+
+
+
+
+
+
+------------------------------------------------------------------------------
+--Hub configuration
+------------------------------------------------------------------------------
+ type hub_mii_t is array(0 to 1) of integer;
+ type hub_ct is array(0 to 16) of integer;
+ type hub_cfg_t is array(0 to 1) of hub_ct;
+
+ --this is used to select the proper configuration in the main code
+ constant CFG_MODE : integer;
+
+
+ --first entry is normal CTS with one optical output, second one is with four optical outputs
+ --slow-control is accepted on SFP1 only, triggers are sent to all used SFP
+ constant INTERNAL_NUM_ARR : hub_mii_t := (5,5);
+ constant INTERFACE_NUM_ARR : hub_mii_t := (5,8);
+ constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0));
+ constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
+ (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0));
+ constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0));
+
+
+ constant INTERNAL_NUM : integer;
+ constant INTERFACE_NUM : integer;
+ constant IS_UPLINK : hub_ct;
+ constant IS_DOWNLINK : hub_ct;
+ constant IS_UPLINK_ONLY : hub_ct;
+
+
+ -- MII_NUMBER => 5, --(8)
+ -- INT_NUMBER => 5,
+ -- INT_CHANNELS => (0,1,0,1,3),
+
+ -- No trigger / sctrl sent to optical link, slow control receiving possible
+ -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+ -- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0);
+ -- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+
+ -- Trigger / sctrl sent to optical link, slow control receiving possible
+ -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
+ -- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0);
+ -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0);
+ -- & disable port 4 in c0 and c1 -- no triggers from/to optical link
+
+ -- Trigger / sctrl sent to 4 optical links
+ -- MII_IS_UPLINK => (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0);
+ -- MII_IS_DOWNLINK => (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0);
+ -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0);
+ -- & disable port 4 in c0 and c1 -- no triggers from/to optical link
+
+------------------------------------------------------------------------------
+--CTS configuration
+------------------------------------------------------------------------------
+ constant cts_rdo_additional_ports : integer;
+
+end;
+
+package body config is
+--compute correct configuration mode
+ constant CFG_MODE : integer := USE_4_SFP;
+ constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC;
+
+ constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE);
+ constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
+ constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
+ constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
+ constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
+
+
+end package body;
\ No newline at end of file
--- /dev/null
+
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /local/trb/cvs/trb3/cts/cts.fdc
+# Written on Mon Feb 25 14:14:25 2013
+# by Synplify Pro, G-2012.09-SP1 FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+define_compile_point {v:work.trb_net16_med_ecp3_sfp_work_trb3_central_trb3_central_arch_11layer0} -type {locked,partition}
+define_compile_point {v:work.trb_net16_med_ecp3_sfp_4_onboard_work_trb3_central_trb3_central_arch_16layer0} -type {locked,partition}
+define_compile_point {v:work.trb_net16_hub_streaming_port_sctrl_cts_work_trb3_central_trb3_central_arch_36layer0} -type {locked,partition}
+define_compile_point {v:work.trb_net16_gbe_buf_0_0} -type {locked,partition}
+define_compile_point {v:work.TDC_5_0_2} -type {locked,partition}
+define_compile_point {v:work.CTS_work_trb3_central_trb3_central_arch_6layer0} -type {locked,partition}
+define_compile_point {v:work.trb_net16_regIO_work_trb3_central_trb3_central_arch_29layer0} -type {locked,partition}
+###==== END "Compile Points"
+
+
<Options/>
</Source>
<Source name="../trb3_central.vhd" type="VHDL" type_short="VHDL">
- <Options/>
+ <Options top_module="trb3_central"/>
</Source>
<Source name="../../tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../config.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../workdir/trb3_central.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
);
end component;
+ component mbs_vulom_recv is
+ port(
+ CLK : in std_logic; -- e.g. 100 MHz
+ RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state
+
+ --Module inputs
+ MBS_IN : in std_logic; -- raw input
+ CLK_200 : in std_logic; -- internal sampling clock
+
+ --trigger outputs
+ TRG_ASYNC_OUT : out std_logic; -- asynchronous rising edge, length varying, here: approx. 110 ns
+ TRG_SYNC_OUT : out std_logic; -- sync. to CLK
+
+ --data output for read-out
+ TRIGGER_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WRITE_OUT : out std_logic;
+ STATUSBIT_OUT: out std_logic_vector(31 downto 0);
+ FINISHED_OUT : out std_logic;
+
+ --Registers / Debug
+ CONTROL_REG_IN : in std_logic_vector(31 downto 0);
+ STATUS_REG_OUT : out std_logic_vector(31 downto 0);
+ DEBUG : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
component CTS_TRIGGER is
generic (
TRIGGER_INPUT_COUNT : integer range 1 to 8 := 4;
-w
-i 15
-l 5
--n 1
+-n 5
-y
-s 12
--t 14
+-t 20
-c 1
-e 2
#-g guidefile.ncd
set_option -fixgeneratedclocks 3
set_option -compiler_compatible true
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
# simulation options
set_option -write_verilog 0
#add_file options
-add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "config.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
add_file -vhdl -lib work "./trb3_central.vhd"
-
-
+#add_file -fpga_constraint "./cts.fdc"
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.std_logic_unsigned.all;
library work;
use work.trb_net_std.all;
use work.trb_net_gbe_components.all;
use work.cts_pkg.all;
-
+
+--Configuration is done in this file:
+ use work.config.all;
+-- The description of hub ports is also there!
+
+
--Ports:
-- LVL1/IPU SCtrl
-- 0 FPGA 1 FPGA 1
-- 2 FPGA 3 FPGA 3
-- 3 FPGA 4 FPGA 4
-- 4 opt. link opt. link
--- 5 CTS read-out internal 0 1 - X X O --downlink only
--- 6 CTS TRG Sctrl GbE 2 3 4 X X X --uplink only
+-- 5-7 SFP 2-4
+-- 5(8) CTS read-out internal 0 1 - X X O --downlink only
+-- 6(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only
--- MII_NUMBER => 5,
--- INT_NUMBER => 5,
--- INT_CHANNELS => (0,1,0,1,3),
-
--- No trigger / sctrl sent to optical link, slow control receiving possible
--- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
--- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0);
--- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
-
--- Trigger / sctrl sent to optical link, slow control receiving possible
--- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0);
--- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0);
--- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0);
--- & disable port 4 in c0 and c1 -- no triggers from/to optical link
--Slow Control
-- 0 - 7 Readout endpoint common status
entity trb3_central is
-
port(
--Clocks
CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible
--SFP
- SFP_RX_P : in std_logic_vector(6 downto 1);
- SFP_RX_N : in std_logic_vector(6 downto 1);
- SFP_TX_P : out std_logic_vector(6 downto 1);
- SFP_TX_N : out std_logic_vector(6 downto 1);
+ SFP_RX_P : in std_logic_vector(9 downto 1);
+ SFP_RX_N : in std_logic_vector(9 downto 1);
+ SFP_TX_P : out std_logic_vector(9 downto 1);
+ SFP_TX_N : out std_logic_vector(9 downto 1);
SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken
SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP
SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
+
+
--FPGA Test
signal time_counter, time_counter2 : unsigned(31 downto 0);
--Media Interface
- signal med_stat_op : std_logic_vector (5*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (5*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (5*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0);
- signal med_data_out : std_logic_vector (5*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (5*3-1 downto 0);
- signal med_dataready_out : std_logic_vector (5*1-1 downto 0);
- signal med_read_out : std_logic_vector (5*1-1 downto 0);
- signal med_data_in : std_logic_vector (5*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (5*3-1 downto 0);
- signal med_dataready_in : std_logic_vector (5*1-1 downto 0);
- signal med_read_in : std_logic_vector (5*1-1 downto 0);
+ signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (INTERFACE_NUM*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (INTERFACE_NUM*64-1 downto 0);
+ signal med_data_out : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (INTERFACE_NUM*1-1 downto 0);
+ signal med_read_out : std_logic_vector (INTERFACE_NUM*1-1 downto 0);
+ signal med_data_in : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (INTERFACE_NUM*1-1 downto 0);
+ signal med_read_in : std_logic_vector (INTERFACE_NUM*1-1 downto 0);
--Hub
signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0);
signal cts_ext_control : std_logic_vector(31 downto 0);
signal cts_ext_debug : std_logic_vector(31 downto 0);
- signal cts_rdo_additional_data : std_logic_vector(63 downto 0);
- signal cts_rdo_additional_write : std_logic_vector(1 downto 0) := "00";
- signal cts_rdo_additional_finished : std_logic_vector(1 downto 0) := "00";
- signal cts_rdo_trg_status_bits_additional : std_logic_vector(63 downto 0) := (others => '0');
+ signal cts_rdo_additional_data : std_logic_vector(31+INCLUDE_TDC*32 downto 0);
+ signal cts_rdo_additional_write : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0');
+ signal cts_rdo_additional_finished : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0');
+ signal cts_rdo_trg_status_bits_additional : std_logic_vector(31+INCLUDE_TDC*32 downto 0) := (others => '0');
signal cts_rdo_trg_type : std_logic_vector(3 downto 0);
signal cts_rdo_trg_code : std_logic_vector(7 downto 0);
signal cts_rdo_trg_information : std_logic_vector(23 downto 0);
signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
signal tdc_ctrl_reg : std_logic_vector(4*32-1 downto 0);
signal tdc_debug : std_logic_vector(15 downto 0);
-
- component mbs_vulom_recv is
- port(
- CLK : in std_logic; -- e.g. 100 MHz
- RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state
-
- --Module inputs
- MBS_IN : in std_logic; -- raw input
- CLK_200 : in std_logic; -- internal sampling clock
-
- --trigger outputs
- TRG_ASYNC_OUT : out std_logic; -- asynchronous rising edge, length varying, here: approx. 110 ns
- TRG_SYNC_OUT : out std_logic; -- sync. to CLK
-
- --data output for read-out
- TRIGGER_IN : in std_logic;
- DATA_OUT : out std_logic_vector(31 downto 0);
- WRITE_OUT : out std_logic;
- STATUSBIT_OUT: out std_logic_vector(31 downto 0);
- FINISHED_OUT : out std_logic;
-
- --Registers / Debug
- CONTROL_REG_IN : in std_logic_vector(31 downto 0);
- STATUS_REG_OUT : out std_logic_vector(31 downto 0);
- DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
+
begin
-- MBS Module
- THE_MBS: mbs_vulom_recv
+ THE_MBS: entity work.mbs_vulom_recv
port map (
CLK => clk_100_i,
RESET_IN => reset_i,
---------------------------------------------------------------------------
--- The TrbNet media interface (Uplink)
+-- The TrbNet media interface (SFP)
---------------------------------------------------------------------------
+
+gen_single_sfp : if USE_4_SFP = c_NO generate
THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
generic map(
SERDES_NUM => 0, --number of serdes in quad
MED_READ_IN => med_read_out(4),
REFCLK2CORE_OUT => open,
--SFP Connection
- SD_RXD_P_IN => SFP_RX_P(1),
- SD_RXD_N_IN => SFP_RX_N(1),
- SD_TXD_P_OUT => SFP_TX_P(1),
- SD_TXD_N_OUT => SFP_TX_N(1),
+ SD_RXD_P_IN => SFP_RX_P(5),
+ SD_RXD_N_IN => SFP_RX_N(5),
+ SD_TXD_P_OUT => SFP_TX_P(5),
+ SD_TXD_N_OUT => SFP_TX_N(5),
SD_REFCLK_P_IN => open,
SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => SFP_MOD0(1),
STAT_DEBUG => med_stat_debug(4*64+63 downto 4*64),
CTRL_DEBUG => (others => '0')
);
-
-
SFP_TXDIS(7 downto 2) <= (others => '1');
+end generate;
+
+gen_four_sfp : if USE_4_SFP = c_YES generate
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
+ generic map(
+ REVERSE_ORDER => c_NO, --order of ports
+ FREQUENCY => 200 --run on 200 MHz clock
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(127 downto 64),
+ MED_PACKET_NUM_IN => med_packet_num_out(23 downto 12),
+ MED_DATAREADY_IN => med_dataready_out(7 downto 4),
+ MED_READ_OUT => med_read_in(7 downto 4),
+ MED_DATA_OUT => med_data_in(127 downto 64),
+ MED_PACKET_NUM_OUT => med_packet_num_in(23 downto 12),
+ MED_DATAREADY_OUT => med_dataready_in(7 downto 4),
+ MED_READ_IN => med_read_out(7 downto 4),
+
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SFP_RX_P(8 downto 5),
+ SD_RXD_N_IN => SFP_RX_N(8 downto 5),
+ SD_TXD_P_OUT => SFP_TX_P(8 downto 5),
+ SD_TXD_N_OUT => SFP_TX_N(8 downto 5),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => SFP_MOD0(4 downto 1),
+ SD_LOS_IN => SFP_LOS(4 downto 1),
+ SD_TXDIS_OUT => SFP_TXDIS(4 downto 1),
+
+-- SCI_DATA_IN => sci1_data_in,
+-- SCI_DATA_OUT => sci1_data_out,
+-- SCI_ADDR => sci1_addr,
+-- SCI_READ => sci1_read,
+-- SCI_WRITE => sci1_write,
+-- SCI_ACK => sci1_ack,
+ -- Status and control port
+
+ STAT_OP => med_stat_op(7*16+15 downto 4*16),
+ CTRL_OP => med_ctrl_op(7*16+15 downto 4*16),
+
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+SFP_TXDIS(7 downto 5) <= (others => '1');
+end generate;
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
MED_READ_IN => med_read_out(3 downto 0),
REFCLK2CORE_OUT => open,
--SFP Connection
- SD_RXD_P_IN => SFP_RX_P(5 downto 2),
- SD_RXD_N_IN => SFP_RX_N(5 downto 2),
- SD_TXD_P_OUT => SFP_TX_P(5 downto 2),
- SD_TXD_N_OUT => SFP_TX_N(5 downto 2),
+ SD_RXD_P_IN => SFP_RX_P(4 downto 1),
+ SD_RXD_N_IN => SFP_RX_N(4 downto 1),
+ SD_TXD_P_OUT => SFP_TX_P(4 downto 1),
+ SD_TXD_N_OUT => SFP_TX_N(4 downto 1),
SD_REFCLK_P_IN => open,
SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN(0) => FPGA1_COMM(2),
THE_HUB: trb_net16_hub_streaming_port_sctrl_cts
generic map(
INIT_ADDRESS => x"F3C0",
- MII_NUMBER => 5,
--- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
--- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0),
--- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0),
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => IS_UPLINK,
+ MII_IS_DOWNLINK => IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,
COMPILE_VERSION => x"0001",
HARDWARE_VERSION => x"9000CEE0",
INIT_ENDPOINT_ID => x"0005",
CLOCK_FREQUENCY => 100,
USE_ONEWIRE => c_YES,
BROADCAST_SPECIAL_ADDR => x"35",
- RDO_ADDITIONAL_PORT => 2,
+ RDO_ADDITIONAL_PORT => cts_rdo_additional_ports,
RDO_DATA_BUFFER_DEPTH => 9,
RDO_DATA_BUFFER_FULL_THRESH => 2**9-128,
RDO_HEADER_BUFFER_DEPTH => 9,
CLK_EN => '1',
-- Media interfacces ---------------------------------------------------------------
- MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(5*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(5*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(5*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(5*1-1 downto 0) => med_read_out,
- MED_STAT_OP(5*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op,
+ MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out,
+ MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out,
+ MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out,
+ MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in,
+ MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in,
+ MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in,
+ MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in,
+ MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out,
+ MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op,
+ MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op,
-- Gbe Read-out Path ---------------------------------------------------------------
--Event information coming from CTS for GbE
FEE_STATUS_BITS_IN => gbe_fee_status_bits,
FEE_BUSY_IN => gbe_fee_busy,
--SFP Connection
- SFP_RXD_P_IN => SFP_RX_P(6), --these ports are don't care
- SFP_RXD_N_IN => SFP_RX_N(6),
- SFP_TXD_P_OUT => SFP_TX_P(6),
- SFP_TXD_N_OUT => SFP_TX_N(6),
+ SFP_RXD_P_IN => SFP_RX_P(9), --these ports are don't care
+ SFP_RXD_N_IN => SFP_RX_N(9),
+ SFP_TXD_P_OUT => SFP_TX_P(9),
+ SFP_TXD_N_OUT => SFP_TX_N(9),
SFP_REFCLK_P_IN => open, --SFP_REFCLKP(2),
SFP_REFCLK_N_IN => open, --SFP_REFCLKN(2),
SFP_PRSNT_N_IN => SFP_MOD0(8), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
+gen_TDC : if INCLUDE_TDC = c_YES generate
THE_TDC : TDC
generic map (
CHANNEL_NUMBER => 5, -- Number of TDC channels
LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
--
LOGIC_ANALYSER_OUT => tdc_debug,
- CONTROL_REG_IN => tdc_ctrl_reg);
-
-
+ CONTROL_REG_IN => tdc_ctrl_reg
+ );
+end generate;
+
+gen_no_TDC : if INCLUDE_TDC = c_NO generate
+
+ srb_invalid <= '1';
+ esb_invalid <= '1';
+ fwb_invalid <= '1';
+ hitreg_invalid <= '1';
+end generate;
+
+
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
---------------------------------------------------------------------------
# Locate Serdes and media interfaces\r
#################################################################\r
LOCATE COMP "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB";\r
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+ \r
LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ;\r
LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ;\r
\r
MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30 ns;\r
\r
\r
-REGION "MEDIA_UPLINK" "R98C95" 17 27;\r
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;\r
+REGION "MEDIA_UPLINK" "R92C90" 22 76;\r
+LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;\r
+LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;\r
+LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ;\r
\r
-REGION "MEDIA_ONBOARD" "R90C122" 20 40;\r
-LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ;\r
+#REGION "MEDIA_ONBOARD" "R90C122" 20 40;\r
\r
MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;\r
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
\r
#SPI Interface\r
REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
MULTICYCLE TO CELL "THE_MBS/error_reg" 20 ns;\r
\r
#TrbNet Hub \r
-REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE;\r
+REGION "REGION_IOBUF" "R40C90D" 55 75 DEVSIZE;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
\r
-\r
-\r
+# THE_HUB.THE_HUB.gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.3_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.4_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
+# \r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
+# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";\r
\r
#GbE Part\r
\r
BLKNAME GBE/FRAME_CONSTRUCTOR\r
BLKNAME GBE/MB_IP_CONFIG\r
BLKNAME GBE/THE_IP_CONFIGURATOR\r
- #BLKNAME GBE/PACKET_CONSTRUCTOR\r
- #BLKNAME GBE/THE_IPU_INTERFACE\r
+# BLKNAME GBE/PACKET_CONSTRUCTOR\r
+# BLKNAME GBE/THE_IPU_INTERFACE\r
BLKNAME GBE/setup_imp_gen_SETUP;\r
\r
\r
-REGION "GBE_REGION" "R50C12D" 25 35 DEVSIZE;\r
+REGION "GBE_REGION" "R44C45D" 36 42 DEVSIZE;\r
REGION "MED0" "R81C10D" 34 40 DEVSIZE;\r
LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
PRIORITIZE NET "GBE/pcs_rxd_q_7" 100;\r
PRIORITIZE NET "GBE/pcs_rxd_q_0" 100;\r
PRIORITIZE NET "GBE/serdes_rx_clk_c" 80;\r
-\r
-BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;\r
-BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;\r
-\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
-MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
-MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
-MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
+# \r
+# BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;\r
+# BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;\r
+# \r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
+# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;\r
+# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
+# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;\r
\r
#BLOCK INTERCLOCKDOMAIN PATHS ;
\ No newline at end of file
jspc29 / trb3.git / commitdiff