--- /dev/null
+#+TITLE: TRB/Padiwa/ DiRICH FEE electronics with ~10ps precision FPGA-TDCs for MA-PMT/MCP-PMT readout
+#+SUBTITLE: Results, Experiences and Problems
+#+AUTHOR: Michael Traxler, GSI
+#+EMAIL: M.Traxler@gsi.de
+#+DATE: 2016-09-17
+#+DESCRIPTION:
+#+KEYWORDS:
+#+LANGUAGE: en
+#+OPTIONS: H:2 num:t toc:t \n:nil @:t ::t |:t ^:t -:t f:t *:t <:t
+#+OPTIONS: TeX:t LaTeX:t skip:nil d:nil todo:t pri:nil tags:not-in-toc
+#+INFOJS_OPT: view:nil toc:nil ltoc:t mouse:underline buttons:0 path:http://orgmode.org/org-info.js
+#+EXPORT_SELECT_TAGS: export
+#+EXPORT_EXCLUDE_TAGS: noexport
+#+LINK_UP:
+#+LINK_HOME:
+
+#+startup: beamer
+#+LaTeX_CLASS: beamer
+#+LaTeX_CLASS_OPTIONS: [presentation]
+#+%LaTeX_CLASS_OPTIONS: [t]
+
+#+latex_header: \mode<beamer>{\usetheme{PaloAlto}}
+#+%latex_header: \mode<beamer>{\usetheme{Madrid}}
+
+#+COLUMNS: %45ITEM %10BEAMER_ENV(Env) %10BEAMER_ACT(Act) %4BEAMER_COL(Col) %8BEAMER_OPT(Opt)
+
+
+* TRB Platform
+** TRB: FPGA TDC
+*** possibilities :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.6
+ :END:
+- FPGA TDCs can be very precise
+ - tradeoff between timing precision and resources
+- FPGA TDCs are flexible
+ - implemented features can change (trigger, windows, scalers, etc.)
+ - new ideas pop up quite often
+*** measurement :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.4
+ :END:
+ #+ATTR_LaTeX: :height 7cm :options angle=0
+ file:../figures/dirich/precision_FPGA_TDC_3_6ps.pdf
+** TRB: Features I
+ - Versatile and meanwhile technically *mature* platform for TDC measurements and digital readout
+ - consists of FPGA-firmware, DAQ- and calibration-software and hardware
+ - most important ingredient: the TRB team (even a collaboration) behind all
+ of it for (necessary) support [trb.gsi.de]
+
+ - many channels (256) on one board and as cheap as possible
+ - leading edge time precision: 8-12ps RMS
+ - hitrates <50MHz (burst)
+ - DAQ: 140MBytes/s via two 1GbE links
+
+** TRB: Features II
+*** Hardware :B_block:
+ :PROPERTIES:
+ :BEAMER_env: block
+ :END:
+ - motivated to be independent from not easy to acquire ASICs from
+ the community
+ - based on FPGAs (TDC, DAQ, FEE-Discriminator) and other parts with
+ a second source
+ - We misuse digital FPGAs in the asynchronous and analoge domain
+** TRB Platform: TRB3 module
+*** TRB3 pic :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :END:
+ #+ATTR_LaTeX: :height \textheight :options angle=0
+ file:../figures/dirich/trb3_tiltet.jpg
+
+*** TRB3 comments :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :END:
+ - 4 times high speed 208-pin connector for various AddONs
+ - Addons available:
+ - 6 port Hubs
+ - NIM/ECL-Input
+ - ADC
+ - standard 100mil pins
+ - Padiwa-Adapter
+ - etc.
+
+** TRB Platform: Some Hardware II
+*** Padiwa :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/padiwa.jpg
+ # file:../figures/dirich/padiwa_transparent.png
+
+*** CBM-TOF-FEE :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :height 3cm :options angle=0
+ file:../figures/dirich/CBM_TOF_32_channel_TDC_DAQ.jpg
+
+*** description :B_ignoreheading:
+ :PROPERTIES:
+ :BEAMER_env: ignoreheading
+ :END:
+ - Padiwa used for CBM-RICH-beamtests
+ - Padiwa used for Panda-Barrel-DIRC-beamtests Summer 2015 at CERN
+ - CBM-TOF-FEE used for CBM-TOF beamtime November 2014 at CERN
+
+
+** TRB Platform: Some Hardware III
+*** TRBsc :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/Trb3sc.jpg
+
+*** TRB3sc Crate :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/trb3sc_crate.jpg
+
+*** description :B_ignoreheading:
+ :PROPERTIES:
+ :BEAMER_env: ignoreheading
+ :END:
+ - 1/4 of TRB3 on a single card
+ - fits in 19" standard crate system with FPGA-connectivity in backplane
+ - better DC/DC converters for better time precision
+ - higher DAQ speed
+
+** New Features and Performance
+ The TDC can now stretch the falling edge of a pulse and reuse the channel to
+ measure the Time over Threshold of an input pulse. The performance is still good.
+*** ToT: alternating channels :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/tot_alternating_10psRMS.pdf
+
+*** ToT: new stretcher :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_env: block
+ :BEAMER_col: 0.5
+ :END:
+ #+ATTR_LaTeX: :height 3.8cm :options angle=0
+ file:../figures/dirich/tot_stretcher_12psRMS.pdf
+
+* Experiences and Limits
+** Experiences and Limits
+*** What did we learn?
+ - TRB DAQ-Systems work very well and stable also for large systems
+ - FPGA-TDC working horse of the whole DAQ/FEE-system
+ - Padiwa-FEE works for many users very well
+ - but....
+
+** Padiwa Timing Results
+ #+ATTR_LaTeX: :height 5.5cm :options angle=0
+ file:../figures/dirich/padiwa_results.pdf
+ - timing measurements in the lab are very good
+ - "trivial": signal to noise determines timing precision
+
+** Feature and Problem at the same Time
+ - The TRB platform is a stable and flexible
+ - Flexibility has a (high) price
+ - Cables everywhere!
+ file:../figures/dirich/cbm_rich_padiwa_cables.png
+
+** Effects of Cables
+ - Mechanically this becomes a problem (densities)
+ - Barrel-DIRC-beam-time clearly showed that this is more than a
+ inconvenience
+ - Long cables damp the signal away
+ #+COMMENT: #+ATTR_LaTeX: :height 4cm :options angle=0
+ file:../figures/dirich/padiwa_cable_signal_rise_time.png
+
+** Solution
+ - Rethink mechanics/cables/connectors
+ - Improve on noise to the input of the FEE
+ - Improve on noise immunity of FEE
+ - Work together in a larger team!
+ - Some pressure!
+
+** Team
+ :PROPERTIES:
+ :BEAMER_OPT: t,shrink=20
+ :END:
+*** HADES-RICH :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.3
+ :BEAMER_env: block
+ :BEAMER_OPT: t
+ :END:
+ file:../figures/dirich/HADES_RICH.jpg
+ #+ATTR_LaTeX: \small
+ \small
+ - 28k channels MA-PMT
+ - existing detector
+ - beamtime in 2018
+*** CBM-RICH :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.3
+ :BEAMER_env: block
+ :BEAMER_OPT: t
+ :END:
+ file:../figures/dirich/CBM_RICH.jpg
+ \small
+ - 55k channels MA-PMT
+ - to be finished in 2020
+*** PANDA-Barrel-DIRC :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.3
+ :BEAMER_env: block
+ :BEAMER_opt: t
+ :END:
+ file:../figures/dirich/PANDA_Barrel_DIRC.jpg
+ \small
+ - 11k channels MCP-PMT
+ - smaller signals
+
+*** TRB Collaboration
+ #+ATTR_LaTeX: :height 1cm :options angle=0
+ file:../figures/dirich/trblogo.png
+ Team of ~8 developpers (hard and software)
+
+* Next Step: DiRICH
+** RICH700 Project in HADES: to be finished in 2016
+ - Exchange of the HADES RICH CsI photocathode
+ - 420 MA-PMTs (from CBM experiment)
+ - Cooperation of CBM + HADES experiments + PANDA-Barrel-DIRC
+ - How to design electronics which solves the cable hell?
+*** test1 :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.6
+ :END:
+ file:../figures/dirich/rich700_teststand1.jpg
+*** test2 :BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.6
+ :END:
+ file:../figures/dirich/rich700_teststand2.jpg
+** HAL9000: Inspiration
+ - First you need some sort of epiphany :-)
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/hal9000_cards.jpg
+** Backplane Granularity and Dimensions: Long and Tedious Optimization
+ #+ATTR_LaTeX: :height \textheight :options angle=0
+ file:../figures/dirich/HADES_RICH_DIRICH_overview2.png
+** DiRCH concept
+ #+ATTR_LaTeX: :height \textheight :options angle=0
+ file:../figures/dirich/dirich_concept_backplane.png
+** DiRICH Requirements and Design Consequences
+ - FEE module for 32 channels
+ - Amplification, Discrimination, TDC + DAQ
+ - "no" cables
+ - analog input signals and digital output signals (serial transmission)
+ over the same connector
+ - low power consumption
+ - only possible with newest FPGAs (price/performance) and very high pin-count connectors
+ - galvanically isolate PMT from FEE with transformers
+ - (hopefully) reduces issues with HV-Power-Supply GND connection
+
+** DiRICH: Amplifier Schematics
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/dirich1_amp_schematics.pdf
+ - BFU760F: fast transistor (40 GHz transition freq.)
+ - low power consumption: <9mW in simulation
+ - high gain: ~30
+ - simple (no specific higher order shaping)
+** DiRICH: Put to Reality
+ #+ATTR_LaTeX: :width \textwidth :options angle=0
+ file:../figures/dirich/dirich1_07_170816.jpg
+
+ - 47mm x 100mm area, 300\mu{}m x 600\mu{}m components, 0201 (imperial)
+ - transformer, gain 30 amps, 16bit-DAC, discriminator, high precision TDC,
+ DAQ + TrbNet (2Gbit/s SERDES), slow-control and voltage-regulation
+
+** DiRICH: Backplane
+ #+ATTR_LaTeX: :height 5cm :options angle=0
+ file:../figures/dirich/dirich_backplane_pmt_04_280716.jpg
+ - Backplane with 12 DiRICH, 6 MA-PMTs (384 channels)
+ - real challenge in layout, 14 layers with stacked microvias.
+ - needed several iterations for full mechanical design to fit both constraints
+** DiRICH: Concentrator
+ #+ATTR_LaTeX: :height 6cm :options angle=0
+ file:../figures/dirich/dirich_concentrator_06_280716.jpg
+ - Concentrator module: aggregates 12 TrbNet links to 1 TrbNet link
+
+** DiRICH: Power
+ #+ATTR_LaTeX: :height 6cm :options angle=0
+ file:../figures/dirich/dirch_power_m05_280716.jpg
+ - Power module (both, DC/DC and Linear) + HV + Clock + Trigger-Distribution
+
+** DiRICH: System
+ #+ATTR_LaTeX: :height 6cm :options angle=0
+ file:../figures/dirich/dirich_system_03_280716.jpg
+ - All fits in :-) How does it perform ?
+
+** Putting Things Together
+ #+ATTR_LaTeX: :height \textheight :options angle=0
+ file:../figures/dirich/RICH_metal.jpg
+
+** Amplifier Results
+ #+ATTR_LaTeX: :height 5cm :options angle=0
+ file:../figures/dirich/prettyshot_preamp2_act.png
+ - very good agreement to simulation
+ - Power: 12mW instead of 9mW
+** Timing Performance in the Lab
+ :PROPERTIES:
+ :BEAMER_OPT:
+ :END:
+
+*** 20mV input signal :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.4
+ :BEAMER_env: block
+ :END:
+ #+ATTR_LaTeX: :height 3cm :options angle=0
+ file:../figures/dirich/TDC_1207_chan_2_-_chan_4_30mV.pdf
+ \skip
+
+**** 1mV input signal :B_block:
+ :PROPERTIES:
+ :BEAMER_env: block
+ :END:
+ file:../figures/dirich/dirich1207_chan4-2_1_3mV_62ps.pdf
+
+*** 4mV input signal :B_block:BMCOL:
+ :PROPERTIES:
+ :BEAMER_col: 0.5
+ :BEAMER_env: block
+ :END:
+ file:../figures/dirich/dirich1207_chan4-2_5_2mV_24ps.pdf
+ \skip
+
+**** 2mV input signal :B_block:
+ :PROPERTIES:
+ :BEAMER_env: block
+ :END:
+ file:../figures/dirich/dirich1207_chan4-2_2_6mV_29ps.pdf
+
+** Next Steps
+ - very promising results
+ - work with real MA-PMTs and MCP-PMTs
+ - build larger system and check performance again
+
+* Summary
+** Summary
+ - The TRB (with its associated FPGA-TDC + DAQ) is a mature platform (hardware
+ and software) useful for many applications
+ - Collaboration takes care of constant development and maintenance
+ - based on the "come-and-kiss" principle
+ - no hard to acquire ASICs used
+ - due to modern commercial components (small, less power) now closer to
+ the ASIC domain
+ - limitations for larger systems
+ - cable-hell and noise
+ - larger application specific systems: need to optimize
+ - hard and software is "easy" to adapt to special applications
+ - MA-PMT and MCP-PMT applications are quite common and we can share the
+ achievements and effort
+
jspc29 / publication.git / commitdiff
