signal reg_ipu_number : std_logic_vector (15 downto 0);
signal reg_lvl1_error_pattern, next_lvl1_error_pattern : std_logic_vector (31 downto 0);
+ -- signal reg_ipu_error_pattern, next_ipu_error_pattern : std_logic_vector (31 downto 0);
+
signal reg_lvl1_trg_release, next_lvl1_trg_release : std_logic;
signal reg_ipu_data, next_ipu_data : std_logic_vector (31 downto 0);
signal reg_ipu_data_ready, next_ipu_data_ready : std_logic;
IPU_READOUT_FINISHED_OUT <= reg_ipu_finished;
IPU_LENGTH_OUT <= reg_first_header(51 downto 36);
- IPU_ERROR_PATTERN_OUT <= x"AAAAAAAA";
+
+--test in case no data in fifo (ok if I don't buffer many events)
+--set the 18th bit if fifo data is empty
+ IPU_ERROR_PATTERN_OUT <= x"000" & "0100" & x"0000" when (empty_flag_fee_data_fifo_i = '1') else (others => '0');--reg_ipu_error_pattern;
-- Count number of dataword per event
reg_ipu_data_ready <= '0';
reg_ipu_finished <= '0';
reg_pseudo_token <= '0';
+ -- reg_ipu_error_pattern <= (others => '0');
else
current_state_fsm_multiplexer <= next_state_fsm_multiplexer;
reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer;
reg_ipu_data_ready <= next_ipu_data_ready;
reg_ipu_finished <= next_ipu_finished;
reg_pseudo_token <= next_pseudo_token;
+ -- reg_ipu_error_pattern <= next_ipu_error_pattern;
end if;
end if;
end process;
clear_counter_word_read_from_trbnet <= '0';
push_read_fee_data_1_i <= '0';
next_pseudo_token <= '0';
-
+ -- next_ipu_error_pattern <= (others => '0');
+
case current_state_fsm_multiplexer is
when idle_state_fsm_multiplexer =>