<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_32_data" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 06 23 23:52:13.976" version="4.8" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="fifo_32_data" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 11 16 11:52:09.586" version="4.8" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="fifo_32_data.lpc" type="lpc" modified="2013 06 23 23:52:12.000"/>
- <File name="fifo_32_data.vhd" type="top_level_vhdl" modified="2013 06 23 23:52:12.000"/>
- <File name="fifo_32_data_tmpl.vhd" type="template_vhdl" modified="2013 06 23 23:52:12.000"/>
- <File name="tb_fifo_32_data_tmpl.vhd" type="testbench_vhdl" modified="2013 06 23 23:52:12.000"/>
+ <File name="fifo_32_data.lpc" type="lpc" modified="2013 11 16 11:51:58.000"/>
+ <File name="fifo_32_data.vhd" type="top_level_vhdl" modified="2013 11 16 11:51:58.000"/>
+ <File name="fifo_32_data_tmpl.vhd" type="template_vhdl" modified="2013 11 16 11:51:58.000"/>
+ <File name="tb_fifo_32_data_tmpl.vhd" type="testbench_vhdl" modified="2013 11 16 11:51:58.000"/>
</Package>
</DiamondModule>
ModuleName=fifo_32_data
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=06/23/2013
-Time=23:52:12
+Date=11/16/2013
+Time=11:51:58
[Parameters]
Verilog=0
Width=32
regout=1
CtrlByRdEn=0
-EmpFlg=1
+EmpFlg=0
PeMode=Static - Single Threshold
PeAssert=1
PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=1020
PfDeassert=506
RDataCount=1
EnECC=0
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe 1 -pf -1 -fill -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe -1 -pf 1020 -fill -e
--- Sun Jun 23 23:52:12 2013
+-- Sat Nov 16 11:51:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
WCNT: out std_logic_vector(10 downto 0);
Empty: out std_logic;
Full: out std_logic;
- AlmostEmpty: out std_logic);
+ AlmostFull: out std_logic);
end fifo_32_data;
architecture Structure of fifo_32_data is
signal invout_1: std_logic;
signal rden_i_inv: std_logic;
signal invout_0: std_logic;
- signal cnt_con_inv: std_logic;
signal r_nw_inv: std_logic;
- signal fcnt_en_inv_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal co3: std_logic;
signal ifcount_10: std_logic;
signal co5: std_logic;
- signal cnt_con: std_logic;
signal co4: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal co5_2: std_logic;
signal rcount_10: std_logic;
signal co4_4: std_logic;
- signal scuba_vhi: std_logic;
signal cmp_ci_2: std_logic;
- signal fcnt_en_inv: std_logic;
- signal r_nw: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal cnt_con: std_logic;
signal fcount_0: std_logic;
signal fcount_1: std_logic;
signal co0_5: std_logic;
+ signal cnt_con_inv: std_logic;
signal fcount_2: std_logic;
signal fcount_3: std_logic;
signal co1_5: std_logic;
signal fcount_6: std_logic;
signal fcount_7: std_logic;
signal co3_5: std_logic;
+ signal scuba_vhi: std_logic;
signal fcount_8: std_logic;
signal fcount_9: std_logic;
signal co4_5: std_logic;
signal fcount_10: std_logic;
- signal ae_d: std_logic;
- signal ae_d_c: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
- FF_0: FD1S3BX
- port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
+ FF_0: FD1S3DX
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
NC0=>ircount_10, NC1=>open);
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- ae_cmp_ci_a: FADD2B
+ af_cmp_ci_a: FADD2B
port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
S1=>open);
- ae_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv, B1=>r_nw,
- CI=>cmp_ci_2, LE=>co0_5);
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
- ae_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co0_5, LE=>co1_5);
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv,
+ B1=>scuba_vhi, CI=>co0_5, GE=>co1_5);
- ae_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co1_5, LE=>co2_5);
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_5, GE=>co2_5);
- ae_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_5, LE=>co3_5);
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co2_5, GE=>co3_5);
- ae_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co3_5, LE=>co4_5);
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co3_5, GE=>co4_5);
- ae_cmp_5: ALEB2
+ af_cmp_5: AGEB2
port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co4_5, LE=>ae_d_c);
+ B1=>scuba_vlo, CI=>co4_5, GE=>af_d_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
a2: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
WCNT(0) <= fcount_0;
WCNT(1) <= fcount_1;
library work;
use work.nxyter_components.all;
-entity nxyter_registers is
+entity nx_control is
port(
CLK_IN : in std_logic;
RESET_IN : in std_logic;
-- Monitor PLL Locks
PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_ADC_CLK_LOCK_IN : in std_logic;
+ PLL_ADC_DCLK_LOCK_IN : in std_logic;
+ PLL_ADC_SCLK_LOCK_IN : in std_logic;
-- Signals
I2C_SM_RESET_OUT : out std_logic;
I2C_REG_RESET_OUT : out std_logic;
NX_TS_RESET_OUT : out std_logic;
+ I2C_OFFLINE_IN : in std_logic;
OFFLINE_OUT : out std_logic;
- -- NX Data Clock Handler
- NX_DATA_CLK_DPHASE_OUT : out std_logic_vector(3 downto 0);
- NX_DATA_CLK_FINEDELB_OUT : out std_logic_vector(3 downto 0);
- NX_DATA_CLK_LOCK_IN : in std_logic;
- NX_DATA_CLK_CLKOP_IN : in std_logic;
- NX_DATA_CLK_CLKOS_IN : in std_logic;
- NX_DATA_CLK_CLKOK_IN : in std_logic;
-
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
);
end entity;
-architecture Behavioral of nxyter_registers is
-
- -- I2C Reset
- signal i2c_sm_reset_start : std_logic;
- signal i2c_reg_reset_start : std_logic;
- signal nx_ts_reset_start : std_logic;
-
- signal i2c_sm_reset_o : std_logic;
- signal i2c_reg_reset_o : std_logic;
- signal nx_ts_reset_o : std_logic;
- signal offline_o : std_logic;
+architecture Behavioral of nx_control is
+
+ -- Offline Handler
+ signal offline_force_internal : std_logic;
+ signal offline_force : std_logic;
+ signal offline_o : std_logic;
+ signal offline_on : std_logic;
+ signal online_on : std_logic;
+ signal offline_last : std_logic;
+
+ -- I2C Reset
+ signal i2c_sm_reset_start : std_logic;
+ signal i2c_reg_reset_start : std_logic;
+ signal nx_ts_reset_start : std_logic;
+
+ signal i2c_sm_reset_o : std_logic;
+ signal i2c_reg_reset_o : std_logic;
+ signal nx_ts_reset_o : std_logic;
+
type STATES is (S_IDLE,
S_I2C_SM_RESET,
signal STATE : STATES;
-- Wait Timer
- signal wait_timer_init : unsigned(7 downto 0);
- signal wait_timer_done : std_logic;
+ signal wait_timer_init : unsigned(7 downto 0);
+ signal wait_timer_done : std_logic;
-- PLL Locks
- signal pll_nx_clk_lock : std_logic;
- signal pll_adc_clk_lock : std_logic;
- signal nx_data_clk_lock : std_logic;
+ signal pll_nx_clk_lock : std_logic;
+ signal pll_adc_dclk_lock : std_logic;
+ signal pll_adc_sclk_lock : std_logic;
- signal pll_nx_clk_notlock : std_logic;
- signal pll_adc_clk_notlock : std_logic;
- signal nx_data_clk_notlock : std_logic;
+ signal pll_nx_clk_notlock : std_logic;
+ signal pll_adc_dclk_notlock : std_logic;
+ signal pll_adc_sclk_notlock : std_logic;
signal pll_nx_clk_notlock_ctr : unsigned(15 downto 0);
- signal pll_adc_clk_notlock_ctr : unsigned(15 downto 0);
- signal nx_data_clk_notlock_ctr : unsigned(15 downto 0);
+ signal pll_adc_dclk_notlock_ctr : unsigned(15 downto 0);
+ signal pll_adc_sclk_notlock_ctr : unsigned(15 downto 0);
+
signal clear_notlock_counters : std_logic;
-- Nxyter Data Clock
- signal nx_data_clk_dphase_o : std_logic_vector(3 downto 0);
- signal nx_data_clk_finedelb_o : std_logic_vector(3 downto 0);
+ signal nx_data_clk_dphase_o : std_logic_vector(3 downto 0);
+ signal nx_data_clk_finedelb_o : std_logic_vector(3 downto 0);
-- Slave Bus
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
begin
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= i2c_sm_reset_o;
- DEBUG_OUT(2) <= i2c_reg_reset_o;
- DEBUG_OUT(3) <= nx_ts_reset_o;
-
- DEBUG_OUT(4) <= NX_DATA_CLK_LOCK_IN;
- DEBUG_OUT(5) <= NX_DATA_CLK_CLKOP_IN;
- DEBUG_OUT(6) <= NX_DATA_CLK_CLKOS_IN;
- DEBUG_OUT(7) <= NX_DATA_CLK_CLKOK_IN;
-
- DEBUG_OUT(11 downto 8) <= nx_data_clk_dphase_o;
- DEBUG_OUT(15 downto 12) <= nx_data_clk_finedelb_o;
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= i2c_sm_reset_o;
+ DEBUG_OUT(2) <= i2c_reg_reset_o;
+ DEBUG_OUT(3) <= nx_ts_reset_o;
+ DEBUG_OUT(4) <= PLL_NX_CLK_LOCK_IN;
+ DEBUG_OUT(5) <= pll_nx_clk_lock;
+ DEBUG_OUT(6) <= PLL_ADC_DCLK_LOCK_IN;
+ DEBUG_OUT(7) <= pll_adc_dclk_lock;
+ DEBUG_OUT(8) <= PLL_ADC_SCLK_LOCK_IN;
+ DEBUG_OUT(9) <= pll_adc_sclk_lock;
+
+
+ DEBUG_OUT(10) <= I2C_OFFLINE_IN;
+ DEBUG_OUT(11) <= offline_force;
+ DEBUG_OUT(12) <= offline_force_internal;
+ DEBUG_OUT(13) <= offline_o;
+ DEBUG_OUT(14) <= online_on;
+ DEBUG_OUT(15) <= '0';
nx_timer_1: nx_timer
generic map (
TIMER_START_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
-
+
+ -----------------------------------------------------------------------------
+ -- Offline Handler
+ -----------------------------------------------------------------------------
+
+ offline_force_internal <= '0';
+
+ PROC_NXYTER_OFFLINE: process(CLK_IN)
+ variable offline_state : std_logic_vector(1 downto 0) := "00";
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ offline_on <= '0';
+ online_on <= '0';
+ offline_o <= '1';
+ offline_last <= '0';
+ else
+ if (offline_force = '1' or offline_force_internal = '1') then
+ offline_o <= '1';
+ else
+ offline_o <= I2C_OFFLINE_IN;
+ end if;
+
+ -- Offline State changes
+ offline_on <= '0';
+ online_on <= '0';
+ offline_last <= offline_o;
+ offline_state := offline_o & offline_last;
+
+ case offline_state is
+ when "01" =>
+ offline_on <= '1';
+
+ when "10" =>
+ online_on <= '0';
+
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process PROC_NXYTER_OFFLINE;
+
-----------------------------------------------------------------------------
-- I2C SM Reset
-----------------------------------------------------------------------------
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- SIGNAL_A_IN => PLL_ADC_CLK_LOCK_IN,
- SIGNAL_OUT => pll_adc_clk_lock
+ SIGNAL_A_IN => PLL_ADC_DCLK_LOCK_IN,
+ SIGNAL_OUT => pll_adc_dclk_lock
);
signal_async_trans_3: signal_async_trans
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- SIGNAL_A_IN => NX_DATA_CLK_LOCK_IN,
- SIGNAL_OUT => nx_data_clk_lock
+ SIGNAL_A_IN => PLL_ADC_SCLK_LOCK_IN,
+ SIGNAL_OUT => pll_adc_sclk_lock
);
level_to_pulse_1: level_to_pulse
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- LEVEL_IN => not pll_adc_clk_lock,
- PULSE_OUT => pll_adc_clk_notlock
+ LEVEL_IN => not pll_adc_dclk_lock,
+ PULSE_OUT => pll_adc_dclk_notlock
);
level_to_pulse_3: level_to_pulse
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- LEVEL_IN => not nx_data_clk_lock,
- PULSE_OUT => nx_data_clk_notlock
+ LEVEL_IN => not pll_adc_sclk_lock,
+ PULSE_OUT => pll_adc_sclk_notlock
);
PROC_PLL_UNLOCK_COUNTERS: process (CLK_IN)
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' or clear_notlock_counters = '1') then
pll_nx_clk_notlock_ctr <= (others => '0');
- pll_adc_clk_notlock_ctr <= (others => '0');
- nx_data_clk_notlock_ctr <= (others => '0');
+ pll_adc_dclk_notlock_ctr <= (others => '0');
+ pll_adc_sclk_notlock_ctr <= (others => '0');
else
if (pll_nx_clk_notlock = '1') then
pll_nx_clk_notlock_ctr <= pll_nx_clk_notlock_ctr + 1;
end if;
- if (pll_adc_clk_notlock = '1') then
- pll_adc_clk_notlock_ctr <= pll_adc_clk_notlock_ctr + 1;
+
+ if (pll_adc_dclk_notlock = '1') then
+ pll_adc_dclk_notlock_ctr <= pll_adc_dclk_notlock_ctr + 1;
end if;
- if (nx_data_clk_notlock = '1') then
- nx_data_clk_notlock_ctr <= nx_data_clk_notlock_ctr + 1;
+
+ if (pll_adc_sclk_notlock = '1') then
+ pll_adc_sclk_notlock_ctr <= pll_adc_sclk_notlock_ctr + 1;
end if;
+
end if;
end if;
end process PROC_PLL_UNLOCK_COUNTERS;
i2c_sm_reset_start <= '0';
i2c_reg_reset_start <= '0';
nx_ts_reset_start <= '0';
- offline_o <= '1';
+ offline_force <= '0';
nx_data_clk_dphase_o <= x"7";
nx_data_clk_finedelb_o <= x"0";
clear_notlock_counters <= '0';
slv_ack_o <= '1';
when x"0003" =>
- offline_o <= SLV_DATA_IN(0);
+ offline_force <= SLV_DATA_IN(0);
slv_ack_o <= '1';
when x"000a" =>
elsif (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0003" =>
- slv_data_out_o(0) <= offline_o;
+ slv_data_out_o(0) <= offline_force;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0004" =>
+ slv_data_out_o(0) <= I2C_OFFLINE_IN;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0005" =>
+ slv_data_out_o(0) <= offline_o;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0006" =>
slv_data_out_o(0) <= pll_nx_clk_lock;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
- when x"0005" =>
- slv_data_out_o(0) <= pll_adc_clk_lock;
+ when x"0007" =>
+ slv_data_out_o(0) <= pll_adc_dclk_lock;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
- when x"000a" =>
+ when x"0008" =>
+ slv_data_out_o(0) <= pll_adc_sclk_lock;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0009" =>
slv_data_out_o(15 downto 0) <= pll_nx_clk_notlock_ctr;
slv_data_out_o(31 downto 6) <= (others => '0');
slv_ack_o <= '1';
+ when x"000a" =>
+ slv_data_out_o(15 downto 0) <= pll_adc_dclk_notlock_ctr;
+ slv_data_out_o(31 downto 6) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"000b" =>
- slv_data_out_o(15 downto 0) <= pll_adc_clk_notlock_ctr;
+ slv_data_out_o(15 downto 0) <= pll_adc_sclk_notlock_ctr;
slv_data_out_o(31 downto 6) <= (others => '0');
slv_ack_o <= '1';
end if;
end process PROC_NX_REGISTERS;
-
- -- Clock Handler
- NX_DATA_CLK_DPHASE_OUT <= nx_data_clk_dphase_o;
- NX_DATA_CLK_FINEDELB_OUT <= nx_data_clk_finedelb_o;
-
-
-- Output Signals
SLV_DATA_OUT <= slv_data_out_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
SLV_ACK_OUT <= slv_ack_o;
-
+
I2C_SM_RESET_OUT <= i2c_sm_reset_o;
I2C_REG_RESET_OUT <= i2c_reg_reset_o;
NX_TS_RESET_OUT <= nx_ts_reset_o;
OFFLINE_OUT <= offline_o;
+
end Behavioral;
fifo_delay <= FIFO_DELAY_IN;
fifo_delay_reset <= '1';
else
- fifo_delay_reset <= '0';
+ fifo_delay_reset <= '0';
end if;
end if;
end if;
ADC_B_IN : in std_logic_vector(1 downto 0);
ADC_NX_IN : in std_logic_vector(1 downto 0);
ADC_D_IN : in std_logic_vector(1 downto 0);
-
+ ADC_SCLK_LOCK_OUT : out std_logic;
+
-- Outputs
NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
architecture Behavioral of nx_data_receiver is
-- Clock Check
- signal counter_nx_domain : unsigned(7 downto 0);
- signal counter_nx_ref_domain : unsigned(7 downto 0);
- signal counter_nx_diff : unsigned(7 downto 0);
+ signal counter_nx_domain : unsigned(7 downto 0);
+ signal counter_nx_ref_domain : unsigned(7 downto 0);
+ signal counter_nx_diff : unsigned(7 downto 0);
-----------------------------------------------------------------------------
-- NX_TIMESTAMP_CLK Domain
-----------------------------------------------------------------------------
-- FIFO DC Input Handler
- signal nx_timestamp_ff : std_logic_vector(7 downto 0);
- signal nx_fifo_full : std_logic;
- signal nx_fifo_reset : std_logic;
-
- -- NX_TIMESTAMP_IN Process
- signal frame_byte_ctr : unsigned(1 downto 0);
- signal nx_frame_word : std_logic_vector(31 downto 0);
- signal nx_new_frame : std_logic;
-
- -- Frame Sync Process
- signal frame_byte_pos : unsigned(1 downto 0);
-
- -- RS Sync FlipFlop
- signal nx_frame_synced : std_logic;
- signal rs_sync_set : std_logic;
- signal rs_sync_reset : std_logic;
-
- -- Parity Check
- signal parity_error : std_logic;
-
- -- Write to FIFO Handler
- signal nx_fifo_data_input : std_logic_vector(31 downto 0);
- signal nx_fifo_write_enable : std_logic;
-
- -- NX Clock Active
- signal nx_clk_active_ff_0 : std_logic;
- signal nx_clk_active_ff_1 : std_logic;
- signal nx_clk_active_ff_2 : std_logic;
-
- -- ADC Ckl Generator
- signal adc_clk_skip : std_logic;
- signal adc_sampling_clk : std_logic;
- signal johnson_ff_0 : std_logic;
- signal johnson_ff_1 : std_logic;
- signal johnson_counter_sync : std_logic_vector(1 downto 0);
- signal adc_clk_ok : std_logic;
-
- signal pll_adc_sampling_clk_o : std_logic;
- signal pll_adc_sampling_clk_lock : std_logic;
- signal pll_adc_sampling_clk_reset : std_logic;
+ signal nx_timestamp_ff : std_logic_vector(7 downto 0);
+ signal nx_fifo_full : std_logic;
+ signal nx_fifo_reset : std_logic;
+
+ -- NX_TIMESTAMP_IN Process
+ signal frame_byte_ctr : unsigned(1 downto 0);
+ signal nx_frame_word : std_logic_vector(31 downto 0);
+ signal nx_new_frame : std_logic;
+
+ -- Frame Sync Process
+ signal frame_byte_pos : unsigned(1 downto 0);
+
+ -- RS Sync FlipFlop
+ signal nx_frame_synced : std_logic;
+ signal rs_sync_set : std_logic;
+ signal rs_sync_reset : std_logic;
+
+ -- Parity Check
+ signal parity_error : std_logic;
+
+ -- Write to FIFO Handler
+ signal nx_fifo_data_input : std_logic_vector(31 downto 0);
+ signal nx_fifo_write_enable : std_logic;
+
+ -- NX Clock Active
+ signal nx_clk_active_ff_0 : std_logic;
+ signal nx_clk_active_ff_1 : std_logic;
+ signal nx_clk_active_ff_2 : std_logic;
+
+ -- ADC Ckl Generator
+ signal adc_clk_skip : std_logic;
+ signal adc_sampling_clk : std_logic;
+ signal johnson_ff_0 : std_logic;
+ signal johnson_ff_1 : std_logic;
+ signal johnson_counter_sync : std_logic_vector(1 downto 0);
+ signal adc_clk_ok : std_logic;
+
+ signal pll_adc_sampling_clk_o : std_logic;
+ signal pll_adc_sampling_clk_lock : std_logic;
+ signal pll_adc_sampling_clk_reset : std_logic;
-- PLL ADC Monitor
- signal pll_adc_not_lock : std_logic;
- signal pll_adc_not_lock_ctr : unsigned(11 downto 0);
- signal pll_adc_not_lock_ctr_clear : std_logic;
+ signal pll_adc_not_lock : std_logic;
+ signal pll_adc_not_lock_ctr : unsigned(11 downto 0);
+ signal pll_adc_not_lock_ctr_clear : std_logic;
-- ADC RESET
- signal adc_clk_ok_last : std_logic;
- signal adc_reset_s : std_logic;
- signal adc_reset_ctr : unsigned(11 downto 0);
+ signal adc_clk_ok_last : std_logic;
+ signal adc_reset_s : std_logic;
+ signal adc_reset_ctr : unsigned(11 downto 0);
-- Reset Handler
- signal r_wait_timer_init : unsigned(27 downto 0);
- signal r_wait_timer_done : std_logic;
- signal reset_adc_handler : std_logic;
+ signal r_wait_timer_init : unsigned(27 downto 0);
+ signal r_wait_timer_done : std_logic;
+ signal reset_adc_handler : std_logic;
type R_STATES is (R_IDLE,
R_PLL_RESET,
);
signal R_STATE : R_STATES;
- signal sampling_clk_reset_p : std_logic;
- signal sampling_clk_reset : std_logic;
- signal adc_reset_p : std_logic;
- signal adc_reset : std_logic;
- signal data_handler_reset_p : std_logic;
- signal data_handler_reset : std_logic;
+ signal sampling_clk_reset_p : std_logic;
+ signal sampling_clk_reset : std_logic;
+ signal adc_reset_p : std_logic;
+ signal adc_reset : std_logic;
+ signal data_handler_reset_p : std_logic;
+ signal data_handler_reset : std_logic;
+ signal reset_handler_counter : unsigned(15 downto 0);
-----------------------------------------------------------------------------
-- CLK_IN Domain
-----------------------------------------------------------------------------
-- NX FIFO READ ENABLE
- signal nx_fifo_read_enable : std_logic;
- signal nx_fifo_empty : std_logic;
- signal nx_read_enable : std_logic;
- signal nx_fifo_data_valid_t : std_logic;
- signal nx_fifo_data_valid : std_logic;
-
- -- NX FIFO READ
- signal nx_timestamp_t : std_logic_vector(31 downto 0);
- signal nx_new_timestamp : std_logic;
- signal nx_new_timestamp_ctr : unsigned(3 downto 0);
- signal nx_fifo_data : std_logic_vector(31 downto 0);
-
- -- Resync Counter Process
- signal resync_counter : unsigned(11 downto 0);
- signal resync_ctr_inc : std_logic;
- signal nx_clk_active : std_logic;
-
- -- Parity Error Counter Process
- signal parity_error_counter : unsigned(11 downto 0);
- signal parity_error_ctr_inc : std_logic;
-
- signal reg_nx_frame_synced : std_logic;
+ signal nx_fifo_read_enable : std_logic;
+ signal nx_fifo_empty : std_logic;
+ signal nx_read_enable : std_logic;
+ signal nx_fifo_data_valid_t : std_logic;
+ signal nx_fifo_data_valid : std_logic;
+
+ -- NX FIFO READ
+ signal nx_timestamp_t : std_logic_vector(31 downto 0);
+ signal nx_new_timestamp : std_logic;
+ signal nx_new_timestamp_ctr : unsigned(3 downto 0);
+ signal nx_fifo_data : std_logic_vector(31 downto 0);
+
+ -- Resync Counter Process
+ signal resync_counter : unsigned(11 downto 0);
+ signal resync_ctr_inc : std_logic;
+ signal nx_clk_active : std_logic;
+
+ -- Parity Error Counter Process
+ signal parity_error_counter : unsigned(11 downto 0);
+ signal parity_error_ctr_inc : std_logic;
+
+ signal reg_nx_frame_synced : std_logic;
-----------------------------------------------------------------------------
-- ADC Data Handler
-----------------------------------------------------------------------------
-- ADC Handler
- signal adc_data : std_logic_vector(11 downto 0);
- signal test_adc_data : std_logic_vector(11 downto 0);
- signal adc_data_valid : std_logic;
+ signal adc_data : std_logic_vector(11 downto 0);
+ signal test_adc_data : std_logic_vector(11 downto 0);
+ signal adc_data_valid : std_logic;
- signal adc_data_t : std_logic_vector(11 downto 0);
- signal adc_new_data : std_logic;
- signal adc_new_data_ctr : unsigned(3 downto 0);
+ signal adc_data_t : std_logic_vector(11 downto 0);
+ signal adc_new_data : std_logic;
+ signal adc_new_data_ctr : unsigned(3 downto 0);
-- ADC TEST INPUT DATA
- signal adc_input_error_enable : std_logic;
- signal adc_input_error_ctr : unsigned(15 downto 0);
+ signal adc_input_error_enable : std_logic;
+ signal adc_input_error_ctr : unsigned(15 downto 0);
-- Data Output Handler
WAIT_TIMESTAMP
);
signal STATE : STATES;
- signal STATE_d : std_logic_vector(1 downto 0);
+ signal STATE_d : std_logic_vector(1 downto 0);
- signal nx_timestamp_o : std_logic_vector(31 downto 0);
- signal adc_data_o : std_logic_vector(11 downto 0);
- signal new_data_o : std_logic;
+ signal nx_timestamp_o : std_logic_vector(31 downto 0);
+ signal adc_data_o : std_logic_vector(11 downto 0);
+ signal new_data_o : std_logic;
-- Check Nxyter Data Clock via Johnson Counter
- signal nx_data_clock_test_0 : std_logic;
- signal nx_data_clock_test_1 : std_logic;
- signal nx_data_clock : std_logic;
- signal nx_data_clock_state : std_logic_vector(3 downto 0);
- signal nx_data_clock_ok : std_logic;
+ signal nx_data_clock_test_0 : std_logic;
+ signal nx_data_clock_test_1 : std_logic;
+ signal nx_data_clock : std_logic;
+ signal nx_data_clock_state : std_logic_vector(3 downto 0);
+ signal nx_data_clock_ok : std_logic;
signal pll_adc_sample_clk_dphase : std_logic_vector(3 downto 0);
signal pll_adc_sample_clk_finedelb : std_logic_vector(3 downto 0);
-- Slave Bus
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
- signal reset_resync_ctr : std_logic;
- signal reset_parity_error_ctr : std_logic;
- signal fifo_reset_r : std_logic;
- signal debug_adc : std_logic_vector(1 downto 0);
- signal reset_adc_handler_r : std_logic;
-
+ signal reset_resync_ctr : std_logic;
+ signal reset_parity_error_ctr : std_logic;
+ signal fifo_reset_r : std_logic;
+ signal debug_adc : std_logic_vector(1 downto 0);
+ signal reset_adc_handler_r : std_logic;
+ signal reset_handler_counter_clear : std_logic;
begin
PROC_DEBUG_MULT: process(debug_adc,
adc_reset_p <= '0';
data_handler_reset_p <= '0';
r_wait_timer_init <= x"00f_4240"; -- 1ms to settle down
+ reset_handler_counter <= (others => '0');
R_STATE <= R_PLL_RESET;
else
sampling_clk_reset_p <= '0';
data_handler_reset_p <= '0';
r_wait_timer_init <= (others => '0');
+ if (reset_handler_counter_clear = '1') then
+ reset_handler_counter <= (others => '0');
+ end if;
+
case R_STATE is
when R_IDLE =>
if (reset_adc_handler = '1' or
end if;
when R_PLL_RESET =>
+ if (reset_handler_counter_clear = '0') then
+ reset_handler_counter <= reset_handler_counter + 1;
+ end if;
if (r_wait_timer_done = '0') then
R_STATE <= R_WAIT_RESET_ADC;
else
pll_adc_sample_clk_finedelb <= (others => '0');
pll_adc_not_lock_ctr_clear <= '0';
reset_adc_handler_r <= '0';
+ reset_handler_counter_clear <= '0';
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
fifo_reset_r <= '0';
pll_adc_not_lock_ctr_clear <= '0';
reset_adc_handler_r <= '0';
+ reset_handler_counter_clear <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"000a" =>
+ when x"0009" =>
slv_data_out_o(0) <= adc_input_error_enable;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
- when x"000b" =>
+ when x"000a" =>
slv_data_out_o(15 downto 0) <= adc_input_error_ctr;
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- when x"000c" =>
+ when x"000b" =>
slv_data_out_o(0) <= nx_data_clock_ok;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
+ when x"000c" =>
+ slv_data_out_o(15 downto 0) <= reset_handler_counter;
+ slv_data_out_o(31 downto 6) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"000f" =>
slv_data_out_o(1 downto 0) <= debug_adc;
slv_data_out_o(31 downto 2) <= (others => '0');
pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0);
reset_adc_handler_r <= '1';
slv_ack_o <= '1';
-
+
when x"0009" =>
- reset_adc_handler_r <= '1';
- slv_ack_o <= '1';
-
- when x"000a" =>
adc_input_error_enable <= SLV_DATA_IN(0);
slv_ack_o <= '1';
+ when x"000c" =>
+ reset_handler_counter_clear <= '1';
+ slv_ack_o <= '1';
+
+ when x"000e" =>
+ reset_adc_handler_r <= '1';
+ slv_ack_o <= '1';
+
when x"000f" =>
debug_adc <= SLV_DATA_IN(1 downto 0);
slv_ack_o <= '1';
-- Output Signals
- NX_TIMESTAMP_OUT <= nx_timestamp_o;
- ADC_DATA_OUT <= adc_data_o;
- NEW_DATA_OUT <= new_data_o;
-
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
+ NX_TIMESTAMP_OUT <= nx_timestamp_o;
+ ADC_DATA_OUT <= adc_data_o;
+ NEW_DATA_OUT <= new_data_o;
+ ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock;
+
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
end Behavioral;
LVL2_TRIGGER_IN : in std_logic;
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
-
+ EVT_BUFFER_FULL_OUT : out std_logic;
+
--Response from FEE
FEE_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_WRITE_OUT : out std_logic;
signal fee_data_o : std_logic_vector(31 downto 0);
signal fee_data_write_o : std_logic;
signal fee_data_finished_o : std_logic;
- signal fee_almost_full_o : std_logic;
signal trigger_busy_o : std_logic;
signal evt_data_flush : std_logic;
signal fifo_empty : std_logic;
signal fifo_write_ctr : std_logic_vector(10 downto 0);
signal fifo_read_start : std_logic;
-
+ signal fifo_almost_full : std_logic;
+
signal fifo_read_enable_s : std_logic;
signal fifo_read_busy : std_logic;
signal fifo_no_data : std_logic;
signal fifo_read_done : std_logic;
+ signal evt_buffer_full_o : std_logic;
signal fifo_data : std_logic_vector(31 downto 0);
type R_STATES is (R_IDLE,
begin
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= '0';
- DEBUG_OUT(2) <= evt_data_clk;
- DEBUG_OUT(3) <= fifo_empty;
- DEBUG_OUT(4) <= fifo_read_enable;
- DEBUG_OUT(5) <= evt_data_flushed;
- DEBUG_OUT(6) <= '0';
- DEBUG_OUT(7) <= EVT_NOMORE_DATA_IN;
- --DEBUG_OUT(15 downto 8) <= evt_data_o(31 downto 24);
-
- DEBUG_OUT(8) <= LVL2_TRIGGER_IN;
- DEBUG_OUT(9) <= evt_data_flushed;
- DEBUG_OUT(10) <= FAST_CLEAR_IN;
- DEBUG_OUT(12) <= flush_end_enable;
- DEBUG_OUT(13) <= fee_data_write_o;
- DEBUG_OUT(14) <= fee_data_finished_o;
+ DEBUG_OUT(1) <= DATA_CLK_IN;
+ DEBUG_OUT(2) <= fifo_empty;
+ DEBUG_OUT(3) <= fifo_almost_full;
+ DEBUG_OUT(4) <= RESET_DATA_BUFFER_IN;
+ DEBUG_OUT(5) <= trigger_busy_o;
+ DEBUG_OUT(6) <= LVL2_TRIGGER_IN;
+ DEBUG_OUT(7) <= evt_data_flush;
+ DEBUG_OUT(8) <= flush_end_enable;
+ DEBUG_OUT(9) <= evt_data_clk;
+ DEBUG_OUT(10) <= fee_data_write_o;
+ DEBUG_OUT(11) <= evt_data_flushed;
+ DEBUG_OUT(12) <= fee_data_finished_o;
+ DEBUG_OUT(13) <= EVT_NOMORE_DATA_IN;
+ DEBUG_OUT(14) <= FAST_CLEAR_IN;
DEBUG_OUT(15) <= FEE_DATA_ALMOST_FULL_IN;
-----------------------------------------------------------------------------
evt_data_flush <= '0';
fee_data_finished_o <= '0';
trigger_busy_o <= '1';
- DEBUG_OUT(11) <= '0';
if (FAST_CLEAR_IN = '1') then
fee_data_finished_o <= '1';
end if;
when S_FLUSH_BUFFER_WAIT =>
- DEBUG_OUT(11) <= '1';
if (evt_data_flushed = '0') then
STATE <= S_FLUSH_BUFFER_WAIT;
else
Q => fifo_o,
WCNT => fifo_write_ctr,
Empty => fifo_empty,
- Full => fifo_full
+ Full => fifo_full,
+ AlmostFull => fifo_almost_full
);
fifo_reset <= RESET_IN or RESET_DATA_BUFFER_IN;
slv_data_out_o(10 downto 0) <= std_logic_vector(fifo_flush_ctr);
slv_data_out_o(31 downto 11) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0003" =>
slv_data_out_o <= register_fifo_status;
slv_ack_o <= '1';
end if;
end process PROC_SLAVE_BUS;
--- Output Signals
+
+ -- Output Signals
+
+ evt_buffer_full_o <= fifo_almost_full;
+
TRIGGER_BUSY_OUT <= trigger_busy_o;
+ EVT_BUFFER_FULL_OUT <= evt_buffer_full_o;
FEE_DATA_OUT <= fee_data_o;
FEE_DATA_WRITE_OUT <= fee_data_write_o;
signal wait_timer_done : std_logic;
signal trigger_o : std_logic;
signal ts_reset_o : std_logic;
+ signal testpulse_p : std_logic;
signal testpulse_o : std_logic;
signal extern_trigger : std_logic;
signal STATE : STATES;
-- Rate Calculation
- signal testpulse_p : std_logic;
+ signal testpulse : std_logic;
signal testpulse_rate_t : unsigned(27 downto 0);
signal rate_timer : unsigned(27 downto 0);
DEBUG_OUT(4) <= wait_timer_done;
DEBUG_OUT(5) <= ts_reset_o;
DEBUG_OUT(6) <= testpulse_o;
- DEBUG_OUT(7) <= testpulse_p;
+ DEBUG_OUT(7) <= testpulse;
DEBUG_OUT(8) <= test_debug;
DEBUG_OUT(15 downto 9) <= (others => '0');
-- Generate Trigger
-----------------------------------------------------------------------------
- -- signal_async_to_pulse_1: signal_async_to_pulse
- -- port map (
- -- CLK_IN => NX_MAIN_CLK_IN,
- -- RESET_IN => RESET_IN,
- -- PULSE_A_IN => TRIGGER_IN,
- -- PULSE_OUT => trigger
- -- );
-
level_to_pulse_1: level_to_pulse
port map (
CLK_IN => NX_MAIN_CLK_IN,
if( rising_edge(NX_MAIN_CLK_IN) ) then
if (RESET_IN = '1') then
trigger_o <= '0';
+ testpulse_p <= '0';
testpulse_o <= '0';
ts_reset_o <= '0';
wait_timer_init <= (others => '0');
STATE <= S_IDLE;
else
trigger_o <= '0';
+ testpulse_p <= '0';
testpulse_o <= '0';
ts_reset_o <= '0';
wait_timer_init <= (others => '0');
when S_IDLE =>
if (trigger = '1') then
extern_trigger <= '1';
+ testpulse_p <= '1';
testpulse_o <= '1';
if (reg_testpulse_length > 1) then
wait_timer_init(11 downto 0) <= reg_testpulse_length - 1;
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
RESET_A_IN => RESET_IN,
- PULSE_A_IN => testpulse_o,
+ PULSE_A_IN => testpulse_p,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
- PULSE_B_OUT => testpulse_p
+ PULSE_B_OUT => testpulse
);
PROC_CAL_RATES: process (CLK_IN)
rate_timer <= (others => '0');
else
if (rate_timer < x"5f5e100") then
- if ( testpulse_p = '1') then
+ if ( testpulse = '1') then
testpulse_rate_t <= testpulse_rate_t + 1;
end if;
rate_timer <= rate_timer + 1;
VALIDATE_TRIGGER_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
LVL2_TRIGGER_OUT : out std_logic;
- EVENT_BUFFER_CLEAR_OUT : out std_logic;
FAST_CLEAR_OUT : out std_logic;
TRIGGER_BUSY_OUT : out std_logic;
-- Trigger Handler
signal validate_trigger_o : std_logic;
signal lvl2_trigger_o : std_logic;
- signal event_buffer_clear_o : std_logic;
signal fast_clear_o : std_logic;
signal trigger_busy_o : std_logic;
signal fee_trg_release_o : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
signal send_testpulse_l : std_logic;
signal send_testpulse : std_logic;
-
+ signal event_buffer_clear_o : std_logic;
+
type STATES is (S_IDLE,
S_CTS_TRIGGER,
S_WAIT_TRG_DATA_VALID,
DEBUG_OUT(7) <= LVL2_TRIGGER_BUSY_IN;
DEBUG_OUT(8) <= validate_trigger_o;
DEBUG_OUT(9) <= lvl2_trigger_o;
- DEBUG_OUT(10) <= event_buffer_clear_o;
+ DEBUG_OUT(10) <= '0';
DEBUG_OUT(11) <= fee_trg_release_o;
DEBUG_OUT(12) <= trigger_busy_o;
DEBUG_OUT(13) <= timestamp_trigger;
when S_CTS_TRIGGER =>
-- Do nothing, Just send Trigger ACK in reply
- event_buffer_clear_o <= '1';
validate_trigger_o <= '1';
lvl2_trigger_o <= '1';
if (reg_testpulse_enable = '1') then
-- Internal Trigger Handler
when S_INTERNAL_TRIGGER =>
validate_trigger_o <= '1';
- event_buffer_clear_o <= '1';
STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
when S_WAIT_TRIGGER_VALIDATE_ACK =>
VALIDATE_TRIGGER_OUT <= validate_trigger_o;
TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o;
LVL2_TRIGGER_OUT <= lvl2_trigger_o;
- EVENT_BUFFER_CLEAR_OUT <= event_buffer_clear_o;
FAST_CLEAR_OUT <= fast_clear_o;
TRIGGER_BUSY_OUT <= trigger_busy_o;
FEE_TRG_RELEASE_OUT <= fee_trg_release_o;
ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: pileup
NX_TOKEN_RETURN_IN : in std_logic; -- 0: ovfl
NX_NOMORE_DATA_IN : in std_logic;
-
+
TRIGGER_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
- -- Outputs
+ -- Event Buffer I/O
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
NOMORE_DATA_OUT : out std_logic;
-
+ EVT_BUFFER_CLEAR_OUT : out std_logic;
+ EVT_BUFFER_FULL_IN : in std_logic;
+
-- Histogram
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
signal channel_index : std_logic_vector(6 downto 0);
signal channel_wait : std_logic_vector(127 downto 0);
signal channel_done : std_logic_vector(127 downto 0);
+ signal channel_hit : std_logic_vector(127 downto 0);
signal channel_all_done : std_logic;
+ signal channel_done_r : std_logic_vector(127 downto 0);
+ signal channel_wait_r : std_logic_vector(127 downto 0);
+ signal channel_hit_r : std_logic_vector(127 downto 0);
+ signal channel_all_done_r : std_logic;
+ signal token_update : std_logic;
+
-- Channel Status Commands
type CS_CMDS is (CS_RESET,
CS_TOKEN_UPDATE,
CS_SET_WAIT,
+ CS_SET_HIT,
CS_SET_DONE,
CS_NONE
);
signal channel_status_cmd : CS_CMDS;
-
+
-- Process Calculate Trigger Window
signal ts_window_lower_thr : unsigned(11 downto 0);
signal out_of_window_h : std_logic;
signal out_of_window_error : std_logic;
signal ch_status_cmd_pr : CS_CMDS;
-
+
+ -- Self Trigger Mode
+ signal self_trigger_mode : std_logic;
+
-- Process Trigger Handler
signal store_to_fifo : std_logic;
signal trigger_busy_o : std_logic;
signal nomore_data_o : std_logic;
signal wait_timer_init : unsigned(11 downto 0);
signal wait_timer_init_ns : unsigned(19 downto 0);
- signal token_return_ctr : std_logic;
+ signal token_return_last : std_logic;
+ signal token_return_first : std_logic;
signal ch_status_cmd_tr : CS_CMDS;
- type STATES is (S_IDLE,
+ type STATES is (S_TEST_SELF_TRIGGER,
+ S_IDLE,
S_TRIGGER,
S_WAIT_DATA,
S_WRITE_HEADER,
signal t_data_o : std_logic_vector(31 downto 0);
signal t_data_clk_o : std_logic;
signal busy_time_ctr : unsigned(11 downto 0);
- signal busy_time_min_done : std_logic;
- signal wait_timer_reset : std_logic;
+ signal wait_timer_reset_all : std_logic;
signal min_val_time_expired : std_logic;
signal event_counter : unsigned(9 downto 0);
signal out_of_window_error_ctr : unsigned(15 downto 0);
- signal readout_mode : std_logic_vector(2 downto 0);
+ signal readout_mode : std_logic_vector(3 downto 0);
signal timestamp_fpga : unsigned(11 downto 0);
signal timestamp_ref : unsigned(11 downto 0);
signal busy_time_ctr_last : unsigned(11 downto 0);
-
+ signal evt_buffer_clear_o : std_logic;
+
-- Timers
signal timer_reset : std_logic;
signal wait_timer_done : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal readout_mode_r : std_logic_vector(2 downto 0);
+ signal readout_mode_r : std_logic_vector(3 downto 0);
signal out_of_window_error_ctr_clear : std_logic;
-- Timestamp Trigger Window Settings
signal readout_time_max : unsigned(11 downto 0);
signal fpga_timestamp_offset : unsigned(11 downto 0);
+ signal state_d : std_logic_vector(1 downto 0);
begin
DEBUG_OUT(8) <= channel_all_done;
DEBUG_OUT(9) <= store_to_fifo;
DEBUG_OUT(10) <= data_clk_o;
- DEBUG_OUT(11) <= out_of_window_error;
- DEBUG_OUT(12) <= wait_timer_done;
- DEBUG_OUT(13) <= wait_timer_done_ns;
- DEBUG_OUT(14) <= busy_time_min_done;
+ DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
+ DEBUG_OUT(12) <= token_update; --TRIGGER_BUSY_IN; --wait_timer_done;
+ DEBUG_OUT(13) <= min_val_time_expired;
+ DEBUG_OUT(14) <= token_update;
DEBUG_OUT(15) <= nomore_data_o;
-- Timer
TIMER_DONE_OUT => wait_timer_done_ns
);
- timer_reset <= RESET_IN or wait_timer_reset;
+ timer_reset <= RESET_IN or wait_timer_reset_all;
-----------------------------------------------------------------------------
-- Filter only valid events
variable window_upper_thr : unsigned(11 downto 0);
variable ts_window_check_value : unsigned(11 downto 0);
variable deltaTStore : unsigned(13 downto 0);
-
+ variable store_data : std_logic;
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
-- Validate incomming Data
-----------------------------------------------------------------------
if (DATA_CLK_IN = '1') then
- if (store_to_fifo = '1') then
-
- if (readout_mode(2) = '0') then
- -- TS Window Active --> do TS check
-
- if (ts_window_check_value(11) = '1') then
- -- TS below Window: Set WAIT Bit in LUT and discard Data
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
- out_of_window_l <= '1';
- elsif (ts_window_check_value > ts_window_width) then
- -- TS above Window: Set DONE Bit in LUT and discard Data
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_DONE;
- out_of_window_h <= '1';
- elsif ((ts_window_check_value >= 0) and
- (ts_window_check_value <= ts_window_width)) then
- -- TS in between Window: Set WAIT Bit in LUT and Take Data
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
-
- case readout_mode(1 downto 0) is
- when "00" =>
- -- RefValue + TS window filter + ovfl valid + parity valid
- if (TIMESTAMP_STATUS_IN(2) = '0' and
- TIMESTAMP_STATUS_IN(0) = '0') then
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
- end if;
-
- when "01" =>
- -- RefValue + TS window filter + ovfl and pileup valid
- -- + parity valid
- if (TIMESTAMP_STATUS_IN = "000") then
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
- end if;
-
- -- when "11" =>
- -- -- RefValue + TS window filter + ovfl and pileup valid
- -- -- + parity valid
- -- if (TIMESTAMP_STATUS_IN = "000") then
- -- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- -- d_data_o(23 downto 12) <= ADC_DATA_IN;
- -- d_data_o(30 downto 24) <= CHANNEL_IN;
- -- d_data_o(30) <= TIMESTAMP_STATUS_IN(0);
- -- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- -- d_data_clk_o <= '1';
- -- end if;
-
- when others =>
- -- RefValue + TS window filter + ignore status
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
- end case;
-
- else
- -- TS Window Error condition, do nothing
- out_of_window_error <= '0';
- if (out_of_window_error_ctr_clear = '0') then
- out_of_window_error_ctr <= out_of_window_error_ctr + 1;
- end if;
+
+ if (store_to_fifo = '1' and EVT_BUFFER_FULL_IN = '0') then
+ store_data := '0';
+
+ -- TS Window Check
+ if (ts_window_check_value(11) = '1') then
+ -- TS below Window: Set WAIT Bit in LUT and discard Data
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_WAIT;
+ out_of_window_l <= '1';
+ store_data := '0';
+ elsif (ts_window_check_value > ts_window_width) then
+ -- TS above Window: Set DONE Bit in LUT and discard Data
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_DONE;
+ out_of_window_h <= '1';
+ store_data := '0';
+ elsif ((ts_window_check_value >= 0) and
+ (ts_window_check_value <= ts_window_width)) then
+ -- TS in between Window: Set WAIT Bit in LUT and Take Data
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_HIT;
+ store_data := '1';
+ else
+ -- TS Window Error condition, do nothing
+ out_of_window_error <= '1';
+ store_data := '0';
+ if (out_of_window_error_ctr_clear = '0') then
+ out_of_window_error_ctr <= out_of_window_error_ctr + 1;
end if;
+ end if;
- else
- -- TS Window Inactive, take data anyhow
+ --TS Window Disabled, always store data
+ if (readout_mode(2) = '1') then
+ store_data := '1';
+ end if;
+
+ if (store_data = '1') then
case readout_mode(1 downto 0) is
when "00" =>
- -- RefValue + ovfl valid + parity valid
+ -- RefValue + TS window filter + ovfl valid + parity valid
if (TIMESTAMP_STATUS_IN(2) = '0' and
TIMESTAMP_STATUS_IN(0) = '0') then
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
+ d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
+ d_data_o(23 downto 12) <= ADC_DATA_IN;
+ d_data_o(30 downto 24) <= CHANNEL_IN;
+ d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
+ d_data_clk_o <= '1';
end if;
when "01" =>
- -- RefValue + ovfl and pileup valid
+ -- RefValue + TS window filter + ovfl and pileup valid
-- + parity valid
if (TIMESTAMP_STATUS_IN = "000") then
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
+ d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
+ d_data_o(23 downto 12) <= ADC_DATA_IN;
+ d_data_o(30 downto 24) <= CHANNEL_IN;
+ d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
+ d_data_clk_o <= '1';
end if;
-
+
when others =>
- -- RefValue + ignore status
- d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
- d_data_o(23 downto 12) <= ADC_DATA_IN;
- d_data_o(30 downto 24) <= CHANNEL_IN;
- d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
- d_data_clk_o <= '1';
-
+ -- RefValue + ignore status
+ d_data_o(11 downto 0) <= deltaTStore(11 downto 0);
+ d_data_o(23 downto 12) <= ADC_DATA_IN;
+ d_data_o(30 downto 24) <= CHANNEL_IN;
+ d_data_o(31) <= TIMESTAMP_STATUS_IN(1);
+ d_data_clk_o <= '1';
end case;
end if;
if (out_of_window_error_ctr_clear = '1') then
- out_of_window_error_ctr <= (others => '0');
+ out_of_window_error_ctr <= (others => '0');
end if;
-- Fill Histogram
- histogram_fill_o <= '1';
- histogram_bin_o <= CHANNEL_IN;
- histogram_adc_o <= ADC_DATA_IN;
+ histogram_fill_o <= '1';
+ histogram_bin_o <= CHANNEL_IN;
+ histogram_adc_o <= ADC_DATA_IN;
end if;
end if;
-- Trigger Handler
-----------------------------------------------------------------------------
+ -- Set Self Trigger Mode Toggle Handler
+ PROC_SELF_TRIGGER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ self_trigger_mode <= '0';
+ else
+ if (trigger_busy_o = '0') then
+ if (readout_mode_r(3) = '1') then
+ self_trigger_mode <= '1';
+ else
+ self_trigger_mode <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process PROC_SELF_TRIGGER;
+
PROC_TRIGGER_HANDLER: process(CLK_IN)
variable wait_for_data_time : unsigned(19 downto 0);
variable min_validation_time : unsigned(19 downto 0);
nomore_data_o <= '0';
wait_timer_init <= (others => '0');
wait_timer_init_ns <= (others => '0');
- wait_timer_reset <= '0';
+ wait_timer_reset_all <= '0';
min_val_time_expired <= '0';
t_data_o <= (others => '0');
t_data_clk_o <= '0';
busy_time_ctr <= (others => '0');
busy_time_ctr_last <= (others => '0');
- busy_time_min_done <= '0';
- token_return_ctr <= '0';
+ token_return_last <= '0';
+ token_return_first <= '0';
ch_status_cmd_tr <= CS_RESET;
event_counter <= (others => '0');
readout_mode <= (others => '0');
timestamp_fpga <= (others => '0');
timestamp_ref <= (others => '0');
- STATE <= S_IDLE;
+ evt_buffer_clear_o <= '0';
+ STATE <= S_TEST_SELF_TRIGGER;
else
store_to_fifo <= '0';
wait_timer_init <= (others => '0');
wait_timer_init_ns <= (others => '0');
- wait_timer_reset <= '0';
+ wait_timer_reset_all <= '0';
trigger_busy_o <= '1';
nomore_data_o <= '0';
t_data_o <= (others => '0');
t_data_clk_o <= '0';
ch_status_cmd_tr <= CS_NONE;
- busy_time_min_done <= '0';
+ evt_buffer_clear_o <= '0';
+
+ --wait_for_data_time :=
+ -- resize(nxyter_cv_time, 20) + (data_fifo_delay_o * 32);
+ wait_for_data_time := x"00008";
+ min_validation_time := resize(ts_window_width * 4, 20);
+
+ -- Check Token Return
+ token_return_last <= NX_TOKEN_RETURN_IN;
+ if (store_to_fifo = '1' and
+ NX_TOKEN_RETURN_IN = '1' and
+ token_return_last = '0') then
+ if (token_return_first = '1') then
+ ch_status_cmd_tr <= CS_TOKEN_UPDATE;
+ else
+ token_return_first <= '1';
+ end if;
+ end if;
- wait_for_data_time :=
- resize(nxyter_cv_time, 20) + (data_fifo_delay_o * 32);
- min_validation_time := resize(ts_window_width * 4, 20);
+ case STATE is
- case STATE is
-
+ when S_TEST_SELF_TRIGGER =>
+ state_d <= "00";
+
+ if (self_trigger_mode = '1') then
+ -- Wait End of LVL2 Trigger Cycle
+ if (TRIGGER_BUSY_IN = '1') then
+ STATE <= S_TEST_SELF_TRIGGER;
+ else
+ readout_mode <= readout_mode_r;
+ timestamp_ref <= (others => '0');
+ STATE <= S_WRITE_HEADER;
+ end if;
+ else
+ STATE <= S_IDLE;
+ end if;
+
when S_IDLE =>
+ state_d <= "01";
+
if (TRIGGER_IN = '1') then
busy_time_ctr <= (others => '0');
STATE <= S_TRIGGER;
else
trigger_busy_o <= '0';
min_val_time_expired <= '0';
+ if (self_trigger_mode = '1') then
+ ch_status_cmd_tr <= CS_RESET;
+ store_to_fifo <= '1';
+ end if;
STATE <= S_IDLE;
end if;
when S_TRIGGER =>
- readout_mode <= readout_mode_r;
- ch_status_cmd_tr <= CS_RESET;
- -- wait for data arrival
- wait_timer_init_ns <= wait_for_data_time;
- STATE <= S_WAIT_DATA;
+ if (self_trigger_mode = '0') then
+ readout_mode <= readout_mode_r;
+
+ -- wait for data arrival and clear evt buffer
+ wait_timer_init_ns <= wait_for_data_time;
+ evt_buffer_clear_o <= '1';
+ STATE <= S_WAIT_DATA;
+ else
+ STATE <= S_WRITE_TRAILER;
+ end if;
when S_WAIT_DATA =>
if (wait_timer_done_ns = '0') then
end if;
when S_WRITE_HEADER =>
+ state_d <= "10";
+
t_data_o(11 downto 0) <= timestamp_ref;
t_data_o(21 downto 12) <= event_counter;
-- Readout Mode Mapping (so far)
-- 01: Special
-- 10: DEBUG
-- 11: UNDEF
- case readout_mode is
+ case readout_mode(2 downto 0) is
when "000" => t_data_o(23 downto 22) <= "00";
when "001" => t_data_o(23 downto 22) <= "01";
when "100" => t_data_o(23 downto 22) <= "10";
t_data_clk_o <= '1';
event_counter <= event_counter + 1;
- STATE <= S_PROCESS_START;
-
+ if (self_trigger_mode = '0') then
+ STATE <= S_PROCESS_START;
+ else
+ STATE <= S_IDLE;
+ end if;
+
when S_PROCESS_START =>
- token_return_ctr <= '0';
wait_timer_init <= readout_time_max;
wait_timer_init_ns <= min_validation_time;
+ token_return_first <= '0';
+ ch_status_cmd_tr <= CS_RESET;
store_to_fifo <= '1';
STATE <= S_WAIT_PROCESS_END;
when S_WAIT_PROCESS_END =>
- if (wait_timer_done = '1' or
- channel_all_done = '1' or
- (readout_mode(2) = '0' and
- NX_NOMORE_DATA_IN = '1' and
- min_val_time_expired = '1')
- )
- then
- wait_timer_reset <= '1';
+ -- Check minimum validation time
+ if (wait_timer_done_ns = '1') then
+ min_val_time_expired <= '1';
+ end if;
+
+ -- Always Exit in case of maximum validation time has expired
+ if (wait_timer_done = '1') then
+ wait_timer_reset_all <= '1';
+ STATE <= S_WRITE_TRAILER;
+ elsif (readout_mode(2) = '0' and
+ min_val_time_expired = '1' and
+ (channel_all_done = '1' or
+ NX_NOMORE_DATA_IN = '1')
+ ) then
+ wait_timer_reset_all <= '1';
STATE <= S_WRITE_TRAILER;
else
- busy_time_min_done <= wait_timer_done_ns;
- min_val_time_expired <= wait_timer_done_ns;
+ -- Continue Validation
store_to_fifo <= '1';
STATE <= S_WAIT_PROCESS_END;
-
- -- Check Token_Return
- if (busy_time_ctr > min_validation_time) then
- if (readout_mode(2) = '0' and NX_TOKEN_RETURN_IN = '1') then
- if (token_return_ctr = '1') then
- ch_status_cmd_tr <= CS_TOKEN_UPDATE;
- end if;
- token_return_ctr <= token_return_ctr or '1';
- end if;
- end if;
end if;
-
+
when S_WRITE_TRAILER =>
+ state_d <= "11";
t_data_o <= (others => '1');
t_data_clk_o <= '1';
- ch_status_cmd_tr <= CS_RESET;
STATE <= S_SET_NOMORE_DATA;
when S_SET_NOMORE_DATA =>
nomore_data_o <= '1';
busy_time_ctr_last <= busy_time_ctr;
- STATE <= S_IDLE;
+ STATE <= S_TEST_SELF_TRIGGER;
+
end case;
+
if (STATE /= S_IDLE) then
busy_time_ctr <= busy_time_ctr + 1;
end if;
-
+
end if;
end if;
end process PROC_TRIGGER_HANDLER;
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1') then
- channel_wait <= (others => '0');
- channel_done <= (others => '0');
- channel_all_done <= '0';
-
+ channel_wait <= (others => '0');
+ channel_done <= (others => '0');
+ channel_hit <= (others => '0');
+ channel_done_r <= (others => '0');
+ channel_wait_r <= (others => '0');
+ channel_hit_r <= (others => '0');
+ channel_all_done <= '0';
+ channel_all_done_r <= '0';
+ token_update <= '0';
else
+ token_update <= '0';
-- Check done status
- if (channel_done = all_one) then
- channel_all_done <= '1';
+ if (channel_status_cmd /= CS_RESET ) then
+ if (channel_done = all_one) then
+ channel_all_done <= '1';
+ end if;
+ else
+ channel_all_done <= '0';
+ channel_all_done_r <= channel_all_done;
end if;
-- Process Command
when CS_RESET =>
channel_wait <= (others => '0');
channel_done <= (others => '0');
- channel_all_done <= '0';
-
+ channel_hit <= (others => '0');
+ channel_done_r <= channel_done;
+ channel_hit_r <= channel_hit;
+ channel_wait_r <= channel_wait;
+
when CS_TOKEN_UPDATE =>
- channel_done <= channel_done or (not channel_wait);
+ if (min_val_time_expired = '1') then
+ channel_done <= channel_done or (not channel_wait);
+ token_update <= '1';
+ end if;
channel_wait <= (others => '0');
when CS_SET_WAIT =>
channel_wait(to_integer(unsigned(channel_index))) <= '1';
-
+
+ when CS_SET_HIT =>
+ channel_hit(to_integer(unsigned(channel_index))) <= '1';
+ channel_wait(to_integer(unsigned(channel_index))) <= '1';
+
when CS_SET_DONE =>
channel_done(to_integer(unsigned(channel_index))) <= '1';
- when others => null;
+ when CS_NONE => null;
end case;
end if;
ts_window_offset <= (others => '0');
ts_window_width <= "0000110010"; -- 50
cts_trigger_delay <= x"0c8";
- readout_mode_r <= "000";
+ readout_mode_r <= "0000";
readout_time_max <= x"3e8";
fpga_timestamp_offset <= (others => '0');
out_of_window_error_ctr_clear <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o( 2 downto 0) <= readout_mode_r;
- slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_data_out_o( 3 downto 0) <= readout_mode_r;
+ slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
when x"0001" =>
std_logic_vector(data_fifo_delay_o);
slv_data_out_o(31 downto 8) <= (others => '0');
slv_ack_o <= '1';
-
+
+ -- 4x Channel WAIT
+
when x"000b" =>
slv_data_out_o <=
- std_logic_vector(channel_done(31 downto 0));
- slv_ack_o <= '1';
+ std_logic_vector(channel_wait_r(31 downto 0));
+ slv_ack_o <= '1';
when x"000c" =>
slv_data_out_o <=
- std_logic_vector(channel_done(63 downto 32));
+ std_logic_vector(channel_wait_r(63 downto 32));
slv_ack_o <= '1';
when x"000d" =>
slv_data_out_o <=
- std_logic_vector(channel_done(95 downto 64));
+ std_logic_vector(channel_wait_r(95 downto 64));
slv_ack_o <= '1';
when x"000e" =>
slv_data_out_o <=
- std_logic_vector(channel_done(127 downto 96));
+ std_logic_vector(channel_wait_r(127 downto 96));
+ slv_ack_o <= '1';
+
+ -- 4x Channel HIT
+
+ when x"000f" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_hit_r(31 downto 0));
+ slv_ack_o <= '1';
+
+ when x"0010" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_hit_r(63 downto 32));
+ slv_ack_o <= '1';
+
+ when x"0011" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_hit_r(95 downto 64));
+ slv_ack_o <= '1';
+
+ when x"0012" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_hit_r(127 downto 96));
+ slv_ack_o <= '1';
+
+ -- 4x Channel DONE
+
+ when x"0013" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_done_r(31 downto 0));
+ slv_ack_o <= '1';
+
+ when x"0014" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_done_r(63 downto 32));
+ slv_ack_o <= '1';
+
+ when x"0015" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_done_r(95 downto 64));
+ slv_ack_o <= '1';
+
+ when x"0016" =>
+ slv_data_out_o <=
+ std_logic_vector(channel_done_r(127 downto 96));
+ slv_ack_o <= '1';
+
+ when x"0017" =>
+ slv_data_out_o(0) <= channel_all_done_r;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0018" =>
+ slv_data_out_o(0) <= EVT_BUFFER_FULL_IN;
+ slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
when others =>
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- readout_mode_r <= SLV_DATA_IN(2 downto 0);
+ readout_mode_r <= SLV_DATA_IN(3 downto 0);
slv_ack_o <= '1';
when x"0001" =>
DATA_CLK_OUT <= data_clk_o;
NOMORE_DATA_OUT <= nomore_data_o;
DATA_FIFO_DELAY_OUT <= std_logic_vector(data_fifo_delay_o);
+ EVT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;
HISTOGRAM_FILL_OUT <= histogram_fill_o;
HISTOGRAM_BIN_OUT <= histogram_bin_o;
CLK_NX_MAIN_IN : in std_logic;
CLK_ADC_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_ADC_CLK_LOCK_IN : in std_logic;
+ PLL_ADC_DCLK_LOCK_IN : in std_logic;
NX_DATA_CLK_TEST_IN : in std_logic;
TRIGGER_OUT : out std_logic;
I2C_SDA_INOUT : inout std_logic;
);
end component;
-component nxyter_registers
+component nx_control
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_ADC_CLK_LOCK_IN : in std_logic;
+ PLL_NX_CLK_LOCK_IN : in std_logic;
+ PLL_ADC_DCLK_LOCK_IN : in std_logic;
+ PLL_ADC_SCLK_LOCK_IN : in std_logic;
I2C_SM_RESET_OUT : out std_logic;
I2C_REG_RESET_OUT : out std_logic;
NX_TS_RESET_OUT : out std_logic;
+ I2C_OFFLINE_IN : in std_logic;
OFFLINE_OUT : out std_logic;
- NX_DATA_CLK_DPHASE_OUT : out std_logic_vector(3 downto 0);
- NX_DATA_CLK_FINEDELB_OUT : out std_logic_vector(3 downto 0);
- NX_DATA_CLK_LOCK_IN : in std_logic;
- NX_DATA_CLK_CLKOP_IN : in std_logic;
- NX_DATA_CLK_CLKOS_IN : in std_logic;
- NX_DATA_CLK_CLKOK_IN : in std_logic;
-
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
Q : out std_logic_vector(31 downto 0);
WCNT : out std_logic_vector(10 downto 0);
Empty : out std_logic;
- Full : out std_logic
+ Full : out std_logic;
+ AlmostFull : out std_logic
);
end component;
ADC_B_IN : in std_logic_vector(1 downto 0);
ADC_NX_IN : in std_logic_vector(1 downto 0);
ADC_D_IN : in std_logic_vector(1 downto 0);
+ ADC_SCLK_LOCK_OUT : out std_logic;
NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
NEW_DATA_OUT : out std_logic;
NX_TOKEN_RETURN_IN : in std_logic;
NX_NOMORE_DATA_IN : in std_logic;
TRIGGER_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
NOMORE_DATA_OUT : out std_logic;
+ EVT_BUFFER_CLEAR_OUT : out std_logic;
+ EVT_BUFFER_FULL_IN : in std_logic;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
LVL2_TRIGGER_IN : in std_logic;
FAST_CLEAR_IN : in std_logic;
TRIGGER_BUSY_OUT : out std_logic;
+ EVT_BUFFER_FULL_OUT : out std_logic;
FEE_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_WRITE_OUT : out std_logic;
FEE_DATA_FINISHED_OUT : out std_logic;
VALIDATE_TRIGGER_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
LVL2_TRIGGER_OUT : out std_logic;
- EVENT_BUFFER_CLEAR_OUT : out std_logic;
FAST_CLEAR_OUT : out std_logic;
TRIGGER_BUSY_OUT : out std_logic;
TRIGGER_TESTPULSE_OUT : out std_logic;
CLK_NX_MAIN_IN : in std_logic;
CLK_ADC_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
- PLL_ADC_CLK_LOCK_IN : in std_logic;
+ PLL_ADC_DCLK_LOCK_IN : in std_logic;
NX_DATA_CLK_TEST_IN : in std_logic;
TRIGGER_OUT : out std_logic;
signal nx_ts_reset_2 : std_logic;
signal nx_ts_reset_o : std_logic;
signal i2c_reg_reset_o : std_logic;
- signal nxyter_offline_reg : std_logic;
signal nxyter_offline : std_logic;
-- NX Register Access
signal spi_sdi : std_logic;
signal spi_sdo : std_logic;
- -- Data Receiver
+ -- Data Receiver
signal adc_data_valid : std_logic;
signal adc_new_data : std_logic;
signal new_timestamp : std_logic_vector(31 downto 0);
signal new_adc_data : std_logic_vector(11 downto 0);
signal new_data : std_logic;
-
+ signal pll_sadc_clk_lock : std_logic;
+
-- Data Delay
signal new_timestamp_delayed : std_logic_vector(31 downto 0);
signal new_adc_data_delayed : std_logic_vector(11 downto 0);
-- Event Buffer
signal trigger_evt_busy : std_logic;
+ signal evt_buffer_full : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
signal fee_data_o : std_logic_vector(31 downto 0);
signal fee_data_write_o : std_logic;
constant DEBUG_NUM_PORTS : integer := 13;
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
- -- Nxyter Data Clock Handler
- signal nx1_data_clk_dphase : std_logic_vector(3 downto 0);
- signal nx1_data_clk_finedelb : std_logic_vector(3 downto 0);
- signal nx1_data_clk_lock : std_logic;
- signal nx1_data_clk_clkop : std_logic;
- signal nx1_data_clk_clkos : std_logic;
- signal nx1_data_clk_clkok : std_logic;
-
begin
-------------------------------------------------------------------------------
generic map(
PORT_NUMBER => NUM_PORTS,
- PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler
+ PORT_ADDRESSES => ( 0 => x"0100", -- NX Control Handler
1 => x"0040", -- I2C Master
2 => x"0500", -- Data Receiver
3 => x"0600", -- Data Buffer
5 => x"0140", -- Trigger Generator
6 => x"0120", -- Data Validate
7 => x"0160", -- Trigger Handler
- 8 => x"0180", -- Trigger Validate
+ 8 => x"0400", -- Trigger Validate
9 => x"0200", -- NX Setup
10 => x"0800", -- NX Histograms
11 => x"0020", -- Debug Handler
others => x"0000"
),
- PORT_ADDR_MASK => ( 0 => 4, -- Control Register Handler
+ PORT_ADDR_MASK => ( 0 => 4, -- NX Control Handler
1 => 0, -- I2C master
2 => 4, -- Data Receiver
3 => 3, -- Data Buffer
5 => 3, -- Trigger Generator
6 => 4, -- Data Validate
7 => 4, -- Trigger Handler
- 8 => 4, -- Trigger Validate
+ 8 => 5, -- Trigger Validate
9 => 9, -- NX Setup
10 => 9, -- NX Histograms
11 => 0, -- Debug Handler
-------------------------------------------------------------------------------
-- Registers
-------------------------------------------------------------------------------
- nxyter_registers_1: nxyter_registers
+ nx_control_1: nx_control
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN,
- PLL_ADC_CLK_LOCK_IN => PLL_ADC_CLK_LOCK_IN,
+ PLL_ADC_DCLK_LOCK_IN => PLL_ADC_DCLK_LOCK_IN,
+ PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock,
I2C_SM_RESET_OUT => i2c_sm_reset_o,
I2C_REG_RESET_OUT => i2c_reg_reset_o,
NX_TS_RESET_OUT => nx_ts_reset_1,
- OFFLINE_OUT => nxyter_offline_reg,
-
- NX_DATA_CLK_DPHASE_OUT => nx1_data_clk_dphase,
- NX_DATA_CLK_FINEDELB_OUT => nx1_data_clk_finedelb,
- NX_DATA_CLK_LOCK_IN => nx1_data_clk_lock,
- NX_DATA_CLK_CLKOP_IN => nx1_data_clk_clkop,
- NX_DATA_CLK_CLKOS_IN => nx1_data_clk_clkos,
- NX_DATA_CLK_CLKOK_IN => nx1_data_clk_clkok,
-
+ I2C_OFFLINE_IN => nxyter_online_i2c,
+ OFFLINE_OUT => nxyter_offline,
+
SLV_READ_IN => slv_read(0),
SLV_WRITE_IN => slv_write(0),
SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
DEBUG_OUT => debug_line(1)
);
- nxyter_offline <= (not nxyter_online_i2c) or nxyter_offline_reg;
-
-------------------------------------------------------------------------------
-- I2C master block for accessing the nXyter
-------------------------------------------------------------------------------
VALIDATE_TRIGGER_OUT => trigger,
TIMESTAMP_TRIGGER_OUT => timestamp_trigger,
LVL2_TRIGGER_OUT => lvl2_trigger,
- EVENT_BUFFER_CLEAR_OUT => event_buffer_clear,
FAST_CLEAR_OUT => fast_clear,
TRIGGER_BUSY_OUT => trigger_busy,
NX_NOMORE_DATA_IN => nx_nomore_data,
TRIGGER_IN => trigger,
+ TRIGGER_BUSY_IN => trigger_busy,
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_validate_busy,
TIMESTAMP_FPGA_IN => timestamp_hold,
DATA_OUT => trigger_data,
DATA_CLK_OUT => trigger_data_clk,
NOMORE_DATA_OUT => validate_nomore_data,
+ EVT_BUFFER_CLEAR_OUT => event_buffer_clear,
+ EVT_BUFFER_FULL_IN => evt_buffer_full,
HISTOGRAM_FILL_OUT => trigger_validate_fill,
HISTOGRAM_BIN_OUT => trigger_validate_bin,
LVL2_TRIGGER_IN => lvl2_trigger,
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_evt_busy,
+ EVT_BUFFER_FULL_OUT => evt_buffer_full,
FEE_DATA_OUT => FEE_DATA_OUT,
FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
+----------------------------------------------------------------------
+-- NXyter BVoradcast Address is: 0xfe49 --
+----------------------------------------------------------------------
+
-- Control Register
0x8100 : w w: reset I2C State Machine
0x8101 : w w: reset I2C all Register
0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA)
-0x8103 : r/w Put Nxyter into offline mode
-0x8104 : r Nxyter Main Clock Lock (125 MHz)
-0x8105 : r ADC Data Clock Lock (187.5MHz)
-0x810a : r/w r: PLL Nxyter Main Clock NotLock Counter
+0x8103 : r/w Force Nxyter offline mode
+0x8104 : r Nxyter I2C Online Status
+0x8105 : r Nxyter Offline
+0x8106 : r Nxyter Main Clock Lock (250 MHz)
+0x8107 : r ADC Data Clock Lock (187.5 MHz)
+0x8108 : r ADC Sample Clock Lock (31.25 MHz)
+0x8109 : r/w r: PLL Nxyter Main Clock NotLock Counter (16 Bit)
w: Clear all pll_nx_clk_notlock_ctr
-0x810b : r PLL ADC Data Clock NotLock Counter
+0x810a : r PLL ADC Data Clock NotLock Counter (16 Bit)
+0x810b : r PLL ADC Sample Clock NotLock Counter (16 Bit)
-- NX I2C Setup Handler
0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c)
0x8161 : r/w Delay Testpulse Signal after Trigger (12 Bit, in 10ns)
0x8162 : r Accepted Trigger Rate (28 Bit, in Hz)
0x8163 : r/w r: Invalid Timing Trigger Counter
- w: clear Counter
+ w: Clear Counter
-- NX Data Receiver
0x8500 : r current Timestamp FIFO value
3..29: ignore
31: nx_frame_synced
0x8502 : r/w r: Resync Counter(12 Bit)
- w: clear Resync Counter
+ w: Clear Resync Counter
0x8503 : r/w r: Parity Error Counter (12 Bit)
- w: clear Parity Error Counter
+ w: Clear Parity Error Counter
0x8504 : r/w ADC Sampling PLL Clock Not Lock Counter
- w: clear counter
+ w: Clear Counter
0x8505 : r/w johnson_counter_sync (2 Bit), do not touch, experts only register
0x8506 : r/w PLL ADC Sampling Clock DPHASE (4 Bit)
0x8507 : r/w PLL ADC Sampling Clock FINEDELB (4 Bit)
0x8508 : r current ADC FIFO value
-0x8509 : w Reset ADC Handler
-0x850a : r/w Enable Test ADC Input Data Error Test
-0x850b : r ADC Input Data Error Counter (16 Bit)
+0x8509 : r/w Enable Test ADC Input Data Error Test
+0x850a : r ADC Input Data Error Counter (16 Bit)
(only valid in case of 0x8509 is 1, see line above)
-0x850c : r Nxyter Data Clock Status (1 = O.K.)
-
+0x850b : r Nxyter Data Clock Status (1 = O.K.)
+0x850c : r/w r: Reset Handler Counter (16 Bit)
+ w: Clear Counter
+0x850e : w Reset ADC Handler
0x850f : r/w Debug Multiplexer:
0: no ADC Values, normal Debug
1: ADC Value Nxyter
(see NX Trigger Validate)
-- NX Trigger Validate
-0x8180 : r/w Readout Mode: 3 Bits
+0x8400 : r/w Readout Mode: 4 Bits
+ Bit #3: Self Trigger Mode
Bit #2: 0: activate TS Selection Window
- 1: data wil be written to disk as long as
+ 1: disable TS Selection Window, i.e.
+ data will be written to disk as long as
Readout Time Max (Reg.: 0x8184) is valid
Bit #1..0 0: TS Ovfl and Parity Bit valid
1: TS Ovfl, Parity and Pileup Bit valid
2: ignore TS Status Bits
3: -------- " -------
-0x8181 : r/w Trigger Window Offset [TS_Offset] (11 Bit signed, in 4ns)
-0x8182 : r/w Trigger Window Width [TS_Width] (10 Bit, in 4ns)
-0x8183 : r/w CTS Trigger Delay [CTS_Delay] (10 Bit, in 4ns)
+0x8401 : r/w Trigger Window Offset [TS_Offset] (11 Bit signed, in 4ns)
+0x8402 : r/w Trigger Window Width [TS_Width] (10 Bit, in 4ns)
+0x8403 : r/w CTS Trigger Delay [CTS_Delay] (10 Bit, in 4ns)
FPGA_Timestamp = TS_Ref
Trigger Window Lower Threshold =
TS_FPGA - CTS_Delay +/- TS_Offset
Trigger Window Upper Threshold =
TS_FPGA - CTS_Delay + TS_Offset + TS_Width
-0x8184 : r/w Readout Time Max (10 Bit, in 10ns)
+0x8404 : r/w Readout Time Max (10 Bit, in 10ns)
-0x8185 : r/w FPGA Timestamp Offset (12 Bit, in 4ns)
-0x8186 : r Busy Time Counter (12 Bit, in 10ns)
-0x8187 : r timestamp_ref
-0x8188 : r window_lower_thr
-0x8189 : r/w Out of Window Error Counter (16 Bit)
+0x8405 : r/w FPGA Timestamp Offset (12 Bit, in 4ns)
+0x8406 : r Busy Time Counter (12 Bit, in 10ns)
+0x8407 : r timestamp_ref
+0x8408 : r window_lower_thr
+0x8409 : r/w Out of Window Error Counter (16 Bit)
w: Clear Counter
-0x818a : r data_fifo_delay (7 Bit, in 32ns)
-0x818b : r done counter ch 0..31
-0x818c : r done counter ch 32..63
-0x818d : r done counter ch 94..95
-0x818e : r done counter ch 96..127
+0x840a : r data_fifo_delay (7 Bit, in 32ns)
+0x840b : r WAIT flags ch 0..31
+0x840c : r WAIT flags ch 32..63
+0x840d : r WAIT flags ch 94..95
+0x840e : r WAIT flags ch 96..127
+0x840f : r HIT flags ch 0..31
+0x8410 : r HIT flags ch 32..63
+0x8411 : r HIT flags ch 94..95
+0x8412 : r HIT flags ch 96..127
+0x8413 : r DONE flags ch 0..31
+0x8414 : r DONE flags ch 32..63
+0x8415 : r DONE flags ch 94..95
+0x8416 : r DONE flags ch 96..127
+0x8417 : r channel_all_done
+0x8418 : r EVT_BUFFER_FULL_IN
-- Event Data Buffer
0x8600 : r read FIFO buffer
add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
-add_file -vhdl -lib "work" "source/nxyter_registers.vhd"
+add_file -vhdl -lib "work" "source/nx_control.vhd"
add_file -vhdl -lib "work" "source/nx_setup.vhd"
add_file -vhdl -lib "work" "source/nx_histograms.vhd"
CLK_NX_MAIN_IN => nx_main_clk,
CLK_ADC_IN => clk_adc_dat_1,
PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
- PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_1,
+ PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_1,
NX_DATA_CLK_TEST_IN => nx_data_clk_test,
TRIGGER_OUT => fee1_trigger,
CLK_NX_MAIN_IN => nx_main_clk,
CLK_ADC_IN => clk_adc_dat_2,
PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
- PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_2,
+ PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_2,
NX_DATA_CLK_TEST_IN => nx_data_clk_test,
TRIGGER_OUT => fee2_trigger,
jspc29 / trb3.git / commitdiff