--- /dev/null
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard
+-- and may be distributed in compiled form in any manner so long as the
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users.
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
+-- file shall indemnify and hold IEEE harmless from any damages or liability
+-- arising out of the use thereof.
+--
+-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
+-- MATH_REAL)
+--
+-- Library: This package shall be compiled into a library
+-- symbolically named IEEE.
+--
+-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose: This package defines a standard for designers to use in
+-- describing VHDL models that make use of common REAL constants
+-- and common REAL elementary mathematical functions.
+--
+-- Limitation: The values generated by the functions in this package may
+-- vary from platform to platform, and the precision of results
+-- is only guaranteed to be the minimum required by IEEE Std 1076-
+-- 1993.
+--
+-- Notes:
+-- No declarations or definitions shall be included in, or
+-- excluded from, this package.
+-- The "package declaration" defines the types, subtypes, and
+-- declarations of MATH_REAL.
+-- The standard mathematical definition and conventional meaning
+-- of the mathematical functions that are part of this standard
+-- represent the formal semantics of the implementation of the
+-- MATH_REAL package declaration. The purpose of the MATH_REAL
+-- package body is to provide a guideline for implementations to
+-- verify their implementation of MATH_REAL. Tool developers may
+-- choose to implement the package body in the most efficient
+-- manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version : 1.5
+-- Date : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package MATH_REAL is
+ constant CopyRightNotice: STRING
+ := "Copyright 1996 IEEE. All rights reserved.";
+
+ --
+ -- Constant Definitions
+ --
+ constant MATH_E : REAL := 2.71828_18284_59045_23536;
+ -- Value of e
+ constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
+ -- Value of 1/e
+ constant MATH_PI : REAL := 3.14159_26535_89793_23846;
+ -- Value of pi
+ constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
+ -- Value of 2*pi
+ constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
+ -- Value of 1/pi
+ constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
+ -- Value of pi/2
+ constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
+ -- Value of pi/3
+ constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
+ -- Value of pi/4
+ constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
+ -- Value 3*pi/2
+ constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
+ -- Natural log of 2
+ constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
+ -- Natural log of 10
+ constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
+ -- Log base 2 of e
+ constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
+ -- Log base 10 of e
+ constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
+ -- square root of 2
+ constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
+ -- square root of 1/2
+ constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
+ -- square root of pi
+ constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
+ -- Conversion factor from degree to radian
+ constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
+ -- Conversion factor from radian to degree
+
+ --
+ -- Function Declarations
+ --
+ function SIGN (X: in REAL ) return REAL;
+ -- Purpose:
+ -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
+ -- Special values:
+ -- None
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ABS(SIGN(X)) <= 1.0
+ -- Notes:
+ -- None
+
+ function CEIL (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns smallest INTEGER value (as REAL) not less than X
+ -- Special values:
+ -- None
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- CEIL(X) is mathematically unbounded
+ -- Notes:
+ -- a) Implementations have to support at least the domain
+ -- ABS(X) < REAL(INTEGER'HIGH)
+
+ function FLOOR (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns largest INTEGER value (as REAL) not greater than X
+ -- Special values:
+ -- FLOOR(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- FLOOR(X) is mathematically unbounded
+ -- Notes:
+ -- a) Implementations have to support at least the domain
+ -- ABS(X) < REAL(INTEGER'HIGH)
+
+ function ROUND (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Rounds X to the nearest integer value (as real). If X is
+ -- halfway between two integers, rounding is away from 0.0
+ -- Special values:
+ -- ROUND(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ROUND(X) is mathematically unbounded
+ -- Notes:
+ -- a) Implementations have to support at least the domain
+ -- ABS(X) < REAL(INTEGER'HIGH)
+
+ function TRUNC (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Truncates X towards 0.0 and returns truncated value
+ -- Special values:
+ -- TRUNC(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- TRUNC(X) is mathematically unbounded
+ -- Notes:
+ -- a) Implementations have to support at least the domain
+ -- ABS(X) < REAL(INTEGER'HIGH)
+
+ function "MOD" (X, Y: in REAL ) return REAL;
+ -- Purpose:
+ -- Returns floating point modulus of X/Y, with the same sign as
+ -- Y, and absolute value less than the absolute value of Y, and
+ -- for some INTEGER value N the result satisfies the relation
+ -- X = Y*N + MOD(X,Y)
+ -- Special values:
+ -- None
+ -- Domain:
+ -- X in REAL; Y in REAL and Y /= 0.0
+ -- Error conditions:
+ -- Error if Y = 0.0
+ -- Range:
+ -- ABS(MOD(X,Y)) < ABS(Y)
+ -- Notes:
+ -- None
+
+ function REALMAX (X, Y : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns the algebraically larger of X and Y
+ -- Special values:
+ -- REALMAX(X,Y) = X when X = Y
+ -- Domain:
+ -- X in REAL; Y in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- REALMAX(X,Y) is mathematically unbounded
+ -- Notes:
+ -- None
+
+ function REALMIN (X, Y : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns the algebraically smaller of X and Y
+ -- Special values:
+ -- REALMIN(X,Y) = X when X = Y
+ -- Domain:
+ -- X in REAL; Y in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- REALMIN(X,Y) is mathematically unbounded
+ -- Notes:
+ -- None
+
+ procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
+ -- Purpose:
+ -- Returns, in X, a pseudo-random number with uniform
+ -- distribution in the open interval (0.0, 1.0).
+ -- Special values:
+ -- None
+ -- Domain:
+ -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
+ -- Error conditions:
+ -- Error if SEED1 or SEED2 outside of valid domain
+ -- Range:
+ -- 0.0 < X < 1.0
+ -- Notes:
+ -- a) The semantics for this function are described by the
+ -- algorithm published by Pierre L'Ecuyer in "Communications
+ -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
+ -- The algorithm is based on the combination of two
+ -- multiplicative linear congruential generators for 32-bit
+ -- platforms.
+ --
+ -- b) Before the first call to UNIFORM, the seed values
+ -- (SEED1, SEED2) have to be initialized to values in the range
+ -- [1, 2147483562] and [1, 2147483398] respectively. The
+ -- seed values are modified after each call to UNIFORM.
+ --
+ -- c) This random number generator is portable for 32-bit
+ -- computers, and it has a period of ~2.30584*(10**18) for each
+ -- set of seed values.
+ --
+ -- d) For information on spectral tests for the algorithm, refer
+ -- to the L'Ecuyer article.
+
+ function SQRT (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns square root of X
+ -- Special values:
+ -- SQRT(0.0) = 0.0
+ -- SQRT(1.0) = 1.0
+ -- Domain:
+ -- X >= 0.0
+ -- Error conditions:
+ -- Error if X < 0.0
+ -- Range:
+ -- SQRT(X) >= 0.0
+ -- Notes:
+ -- a) The upper bound of the reachable range of SQRT is
+ -- approximately given by:
+ -- SQRT(X) <= SQRT(REAL'HIGH)
+
+ function CBRT (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns cube root of X
+ -- Special values:
+ -- CBRT(0.0) = 0.0
+ -- CBRT(1.0) = 1.0
+ -- CBRT(-1.0) = -1.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- CBRT(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of CBRT is approximately given by:
+ -- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
+
+ function "**" (X : in INTEGER; Y : in REAL) return REAL;
+ -- Purpose:
+ -- Returns Y power of X ==> X**Y
+ -- Special values:
+ -- X**0.0 = 1.0; X /= 0
+ -- 0**Y = 0.0; Y > 0.0
+ -- X**1.0 = REAL(X); X >= 0
+ -- 1**Y = 1.0
+ -- Domain:
+ -- X > 0
+ -- X = 0 for Y > 0.0
+ -- X < 0 for Y = 0.0
+ -- Error conditions:
+ -- Error if X < 0 and Y /= 0.0
+ -- Error if X = 0 and Y <= 0.0
+ -- Range:
+ -- X**Y >= 0.0
+ -- Notes:
+ -- a) The upper bound of the reachable range for "**" is
+ -- approximately given by:
+ -- X**Y <= REAL'HIGH
+
+ function "**" (X : in REAL; Y : in REAL) return REAL;
+ -- Purpose:
+ -- Returns Y power of X ==> X**Y
+ -- Special values:
+ -- X**0.0 = 1.0; X /= 0.0
+ -- 0.0**Y = 0.0; Y > 0.0
+ -- X**1.0 = X; X >= 0.0
+ -- 1.0**Y = 1.0
+ -- Domain:
+ -- X > 0.0
+ -- X = 0.0 for Y > 0.0
+ -- X < 0.0 for Y = 0.0
+ -- Error conditions:
+ -- Error if X < 0.0 and Y /= 0.0
+ -- Error if X = 0.0 and Y <= 0.0
+ -- Range:
+ -- X**Y >= 0.0
+ -- Notes:
+ -- a) The upper bound of the reachable range for "**" is
+ -- approximately given by:
+ -- X**Y <= REAL'HIGH
+
+ function EXP (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns e**X; where e = MATH_E
+ -- Special values:
+ -- EXP(0.0) = 1.0
+ -- EXP(1.0) = MATH_E
+ -- EXP(-1.0) = MATH_1_OVER_E
+ -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
+ -- Domain:
+ -- X in REAL such that EXP(X) <= REAL'HIGH
+ -- Error conditions:
+ -- Error if X > LOG(REAL'HIGH)
+ -- Range:
+ -- EXP(X) >= 0.0
+ -- Notes:
+ -- a) The usable domain of EXP is approximately given by:
+ -- X <= LOG(REAL'HIGH)
+
+ function LOG (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns natural logarithm of X
+ -- Special values:
+ -- LOG(1.0) = 0.0
+ -- LOG(MATH_E) = 1.0
+ -- Domain:
+ -- X > 0.0
+ -- Error conditions:
+ -- Error if X <= 0.0
+ -- Range:
+ -- LOG(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of LOG is approximately given by:
+ -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
+
+ function LOG2 (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns logarithm base 2 of X
+ -- Special values:
+ -- LOG2(1.0) = 0.0
+ -- LOG2(2.0) = 1.0
+ -- Domain:
+ -- X > 0.0
+ -- Error conditions:
+ -- Error if X <= 0.0
+ -- Range:
+ -- LOG2(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of LOG2 is approximately given by:
+ -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
+
+ function LOG10 (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns logarithm base 10 of X
+ -- Special values:
+ -- LOG10(1.0) = 0.0
+ -- LOG10(10.0) = 1.0
+ -- Domain:
+ -- X > 0.0
+ -- Error conditions:
+ -- Error if X <= 0.0
+ -- Range:
+ -- LOG10(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of LOG10 is approximately given by:
+ -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
+
+ function LOG (X: in REAL; BASE: in REAL) return REAL;
+ -- Purpose:
+ -- Returns logarithm base BASE of X
+ -- Special values:
+ -- LOG(1.0, BASE) = 0.0
+ -- LOG(BASE, BASE) = 1.0
+ -- Domain:
+ -- X > 0.0
+ -- BASE > 0.0
+ -- BASE /= 1.0
+ -- Error conditions:
+ -- Error if X <= 0.0
+ -- Error if BASE <= 0.0
+ -- Error if BASE = 1.0
+ -- Range:
+ -- LOG(X, BASE) is mathematically unbounded
+ -- Notes:
+ -- a) When BASE > 1.0, the reachable range of LOG is
+ -- approximately given by:
+ -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
+ -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
+ -- approximately given by:
+ -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
+
+ function SIN (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns sine of X; X in radians
+ -- Special values:
+ -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+ -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
+ -- INTEGER
+ -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
+ -- INTEGER
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ABS(SIN(X)) <= 1.0
+ -- Notes:
+ -- a) For larger values of ABS(X), degraded accuracy is allowed.
+
+ function COS ( X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns cosine of X; X in radians
+ -- Special values:
+ -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
+ -- INTEGER
+ -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
+ -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ABS(COS(X)) <= 1.0
+ -- Notes:
+ -- a) For larger values of ABS(X), degraded accuracy is allowed.
+
+ function TAN (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns tangent of X; X in radians
+ -- Special values:
+ -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+ -- Domain:
+ -- X in REAL and
+ -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
+ -- Error conditions:
+ -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
+ -- INTEGER
+ -- Range:
+ -- TAN(X) is mathematically unbounded
+ -- Notes:
+ -- a) For larger values of ABS(X), degraded accuracy is allowed.
+
+ function ARCSIN (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns inverse sine of X
+ -- Special values:
+ -- ARCSIN(0.0) = 0.0
+ -- ARCSIN(1.0) = MATH_PI_OVER_2
+ -- ARCSIN(-1.0) = -MATH_PI_OVER_2
+ -- Domain:
+ -- ABS(X) <= 1.0
+ -- Error conditions:
+ -- Error if ABS(X) > 1.0
+ -- Range:
+ -- ABS(ARCSIN(X) <= MATH_PI_OVER_2
+ -- Notes:
+ -- None
+
+ function ARCCOS (X : in REAL ) return REAL;
+ -- Purpose:
+ -- Returns inverse cosine of X
+ -- Special values:
+ -- ARCCOS(1.0) = 0.0
+ -- ARCCOS(0.0) = MATH_PI_OVER_2
+ -- ARCCOS(-1.0) = MATH_PI
+ -- Domain:
+ -- ABS(X) <= 1.0
+ -- Error conditions:
+ -- Error if ABS(X) > 1.0
+ -- Range:
+ -- 0.0 <= ARCCOS(X) <= MATH_PI
+ -- Notes:
+ -- None
+
+ function ARCTAN (Y : in REAL) return REAL;
+ -- Purpose:
+ -- Returns the value of the angle in radians of the point
+ -- (1.0, Y), which is in rectangular coordinates
+ -- Special values:
+ -- ARCTAN(0.0) = 0.0
+ -- Domain:
+ -- Y in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
+ -- Notes:
+ -- None
+
+ function ARCTAN (Y : in REAL; X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns the principal value of the angle in radians of
+ -- the point (X, Y), which is in rectangular coordinates
+ -- Special values:
+ -- ARCTAN(0.0, X) = 0.0 if X > 0.0
+ -- ARCTAN(0.0, X) = MATH_PI if X < 0.0
+ -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
+ -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
+ -- Domain:
+ -- Y in REAL
+ -- X in REAL, X /= 0.0 when Y = 0.0
+ -- Error conditions:
+ -- Error if X = 0.0 and Y = 0.0
+ -- Range:
+ -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
+ -- Notes:
+ -- None
+
+ function SINH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns hyperbolic sine of X
+ -- Special values:
+ -- SINH(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- SINH(X) is mathematically unbounded
+ -- Notes:
+ -- a) The usable domain of SINH is approximately given by:
+ -- ABS(X) <= LOG(REAL'HIGH)
+
+
+ function COSH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns hyperbolic cosine of X
+ -- Special values:
+ -- COSH(0.0) = 1.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- COSH(X) >= 1.0
+ -- Notes:
+ -- a) The usable domain of COSH is approximately given by:
+ -- ABS(X) <= LOG(REAL'HIGH)
+
+ function TANH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns hyperbolic tangent of X
+ -- Special values:
+ -- TANH(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ABS(TANH(X)) <= 1.0
+ -- Notes:
+ -- None
+
+ function ARCSINH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns inverse hyperbolic sine of X
+ -- Special values:
+ -- ARCSINH(0.0) = 0.0
+ -- Domain:
+ -- X in REAL
+ -- Error conditions:
+ -- None
+ -- Range:
+ -- ARCSINH(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of ARCSINH is approximately given by:
+ -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
+
+ function ARCCOSH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns inverse hyperbolic cosine of X
+ -- Special values:
+ -- ARCCOSH(1.0) = 0.0
+ -- Domain:
+ -- X >= 1.0
+ -- Error conditions:
+ -- Error if X < 1.0
+ -- Range:
+ -- ARCCOSH(X) >= 0.0
+ -- Notes:
+ -- a) The upper bound of the reachable range of ARCCOSH is
+ -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
+
+ function ARCTANH (X : in REAL) return REAL;
+ -- Purpose:
+ -- Returns inverse hyperbolic tangent of X
+ -- Special values:
+ -- ARCTANH(0.0) = 0.0
+ -- Domain:
+ -- ABS(X) < 1.0
+ -- Error conditions:
+ -- Error if ABS(X) >= 1.0
+ -- Range:
+ -- ARCTANH(X) is mathematically unbounded
+ -- Notes:
+ -- a) The reachable range of ARCTANH is approximately given by:
+ -- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
+
+end MATH_REAL;
+
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+
+-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard
+-- and may be distributed in compiled form in any manner so long as the
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users.
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
+-- file shall indemnify and hold IEEE harmless from any damages or liability
+-- arising out of the use thereof.
+
+--
+-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
+-- MATH_REAL)
+--
+-- Library: This package shall be compiled into a library
+-- symbolically named IEEE.
+--
+-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose: This package body is a nonnormative implementation of the
+-- functionality defined in the MATH_REAL package declaration.
+--
+-- Limitation: The values generated by the functions in this package may
+-- vary from platform to platform, and the precision of results
+-- is only guaranteed to be the minimum required by IEEE Std 1076
+-- -1993.
+--
+-- Notes:
+-- The "package declaration" defines the types, subtypes, and
+-- declarations of MATH_REAL.
+-- The standard mathematical definition and conventional meaning
+-- of the mathematical functions that are part of this standard
+-- represent the formal semantics of the implementation of the
+-- MATH_REAL package declaration. The purpose of the MATH_REAL
+-- package body is to clarify such semantics and provide a
+-- guideline for implementations to verify their implementation
+-- of MATH_REAL. Tool developers may choose to implement
+-- the package body in the most efficient manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version : 1.5
+-- Date : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package body MATH_REAL is
+
+ --
+ -- Local Constants for Use in the Package Body Only
+ --
+ constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
+ constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
+ constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
+ constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
+ constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
+ constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
+ constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
+
+ --
+ -- Local Type Declarations for Cordic Operations
+ --
+ type REAL_VECTOR is array (NATURAL range <>) of REAL;
+ type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
+ subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
+ subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
+ subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
+ subtype QUADRANT is INTEGER range 0 to 3;
+ type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
+
+ --
+ -- Auxiliary Functions for Cordic Algorithms
+ --
+ function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
+ NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
+ -- Description:
+ -- Returns power of two for a vector of values
+ -- Notes:
+ -- None
+ --
+ variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
+ variable TEMP : REAL := INITIAL_VALUE;
+ variable FLAG : BOOLEAN := TRUE;
+ begin
+ for I in 0 to NUMBER_OF_VALUES loop
+ V(I) := TEMP;
+ for P in D'RANGE loop
+ if I = D(P) then
+ FLAG := FALSE;
+ exit;
+ end if;
+ end loop;
+ if FLAG then
+ TEMP := TEMP/2.0;
+ end if;
+ FLAG := TRUE;
+ end loop;
+ return V;
+ end POWER_OF_2_SERIES;
+
+
+ constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
+ NATURAL_VECTOR'(100, 90),1.0,
+ MAX_ITER);
+
+ constant EPSILON : REAL_VECTOR_N := (
+ 7.8539816339744827e-01,
+ 4.6364760900080606e-01,
+ 2.4497866312686413e-01,
+ 1.2435499454676144e-01,
+ 6.2418809995957351e-02,
+ 3.1239833430268277e-02,
+ 1.5623728620476830e-02,
+ 7.8123410601011116e-03,
+ 3.9062301319669717e-03,
+ 1.9531225164788189e-03,
+ 9.7656218955931937e-04,
+ 4.8828121119489829e-04,
+ 2.4414062014936175e-04,
+ 1.2207031189367021e-04,
+ 6.1035156174208768e-05,
+ 3.0517578115526093e-05,
+ 1.5258789061315760e-05,
+ 7.6293945311019699e-06,
+ 3.8146972656064960e-06,
+ 1.9073486328101870e-06,
+ 9.5367431640596080e-07,
+ 4.7683715820308876e-07,
+ 2.3841857910155801e-07,
+ 1.1920928955078067e-07,
+ 5.9604644775390553e-08,
+ 2.9802322387695303e-08,
+ 1.4901161193847654e-08,
+ 7.4505805969238281e-09
+ );
+
+ function CORDIC ( X0 : in REAL;
+ Y0 : in REAL;
+ Z0 : in REAL;
+ N : in NATURAL; -- Precision factor
+ CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
+ -- or vectoring (Y -> 0)
+ ) return REAL_ARR_3 is
+ -- Description:
+ -- Compute cordic values
+ -- Notes:
+ -- None
+ variable X : REAL := X0;
+ variable Y : REAL := Y0;
+ variable Z : REAL := Z0;
+ variable X_TEMP : REAL;
+ begin
+ if CORDIC_MODE = ROTATION then
+ for K in 0 to N loop
+ X_TEMP := X;
+ if ( Z >= 0.0) then
+ X := X - Y * TWO_AT_MINUS(K);
+ Y := Y + X_TEMP * TWO_AT_MINUS(K);
+ Z := Z - EPSILON(K);
+ else
+ X := X + Y * TWO_AT_MINUS(K);
+ Y := Y - X_TEMP * TWO_AT_MINUS(K);
+ Z := Z + EPSILON(K);
+ end if;
+ end loop;
+ else
+ for K in 0 to N loop
+ X_TEMP := X;
+ if ( Y < 0.0) then
+ X := X - Y * TWO_AT_MINUS(K);
+ Y := Y + X_TEMP * TWO_AT_MINUS(K);
+ Z := Z - EPSILON(K);
+ else
+ X := X + Y * TWO_AT_MINUS(K);
+ Y := Y - X_TEMP * TWO_AT_MINUS(K);
+ Z := Z + EPSILON(K);
+ end if;
+ end loop;
+ end if;
+ return REAL_ARR_3'(X, Y, Z);
+ end CORDIC;
+
+ --
+ -- Bodies for Global Mathematical Functions Start Here
+ --
+ function SIGN (X: in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- None
+ begin
+ if ( X > 0.0 ) then
+ return 1.0;
+ elsif ( X < 0.0 ) then
+ return -1.0;
+ else
+ return 0.0;
+ end if;
+ end SIGN;
+
+ function CEIL (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) No conversion to an INTEGER type is expected, so truncate
+ -- cannot overflow for large arguments
+ -- b) The domain supported by this function is X <= LARGE
+ -- c) Returns X if ABS(X) >= LARGE
+
+ constant LARGE: REAL := REAL(INTEGER'HIGH);
+ variable RD: REAL;
+
+ begin
+ if ABS(X) >= LARGE then
+ return X;
+ end if;
+
+ RD := REAL ( INTEGER(X));
+ if RD = X then
+ return X;
+ end if;
+
+ if X > 0.0 then
+ if RD >= X then
+ return RD;
+ else
+ return RD + 1.0;
+ end if;
+ elsif X = 0.0 then
+ return 0.0;
+ else
+ if RD <= X then
+ return RD + 1.0;
+ else
+ return RD;
+ end if;
+ end if;
+ end CEIL;
+
+ function FLOOR (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) No conversion to an INTEGER type is expected, so truncate
+ -- cannot overflow for large arguments
+ -- b) The domain supported by this function is ABS(X) <= LARGE
+ -- c) Returns X if ABS(X) >= LARGE
+
+ constant LARGE: REAL := REAL(INTEGER'HIGH);
+ variable RD: REAL;
+
+ begin
+ if ABS( X ) >= LARGE then
+ return X;
+ end if;
+
+ RD := REAL ( INTEGER(X));
+ if RD = X then
+ return X;
+ end if;
+
+ if X > 0.0 then
+ if RD <= X then
+ return RD;
+ else
+ return RD - 1.0;
+ end if;
+ elsif X = 0.0 then
+ return 0.0;
+ else
+ if RD >= X then
+ return RD - 1.0;
+ else
+ return RD;
+ end if;
+ end if;
+ end FLOOR;
+
+ function ROUND (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 if X = 0.0
+ -- b) Returns FLOOR(X + 0.5) if X > 0
+ -- c) Returns CEIL(X - 0.5) if X < 0
+
+ begin
+ if X > 0.0 then
+ return FLOOR(X + 0.5);
+ elsif X < 0.0 then
+ return CEIL( X - 0.5);
+ else
+ return 0.0;
+ end if;
+ end ROUND;
+
+ function TRUNC (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 if X = 0.0
+ -- b) Returns FLOOR(X) if X > 0
+ -- c) Returns CEIL(X) if X < 0
+
+ begin
+ if X > 0.0 then
+ return FLOOR(X);
+ elsif X < 0.0 then
+ return CEIL( X);
+ else
+ return 0.0;
+ end if;
+ end TRUNC;
+
+
+
+
+ function "MOD" (X, Y: in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error
+
+ variable XNEGATIVE : BOOLEAN := X < 0.0;
+ variable YNEGATIVE : BOOLEAN := Y < 0.0;
+ variable VALUE : REAL;
+ begin
+ -- Check validity of input arguments
+ if (Y = 0.0) then
+ assert FALSE
+ report "MOD(X, 0.0) is undefined"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Compute value
+ if ( XNEGATIVE ) then
+ if ( YNEGATIVE ) then
+ VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+ else
+ VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+ end if;
+ else
+ if ( YNEGATIVE ) then
+ VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+ else
+ VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+ end if;
+ end if;
+
+ return VALUE;
+ end "MOD";
+
+
+ function REALMAX (X, Y : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) REALMAX(X,Y) = X when X = Y
+ --
+ begin
+ if X >= Y then
+ return X;
+ else
+ return Y;
+ end if;
+ end REALMAX;
+
+ function REALMIN (X, Y : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) REALMIN(X,Y) = X when X = Y
+ --
+ begin
+ if X <= Y then
+ return X;
+ else
+ return Y;
+ end if;
+ end REALMIN;
+
+
+ procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
+ is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error
+ --
+ variable Z, K: INTEGER;
+ variable TSEED1 : INTEGER := INTEGER'(SEED1);
+ variable TSEED2 : INTEGER := INTEGER'(SEED2);
+ begin
+ -- Check validity of arguments
+ if SEED1 > 2147483562 then
+ assert FALSE
+ report "SEED1 > 2147483562 in UNIFORM"
+ severity ERROR;
+ X := 0.0;
+ return;
+ end if;
+
+ if SEED2 > 2147483398 then
+ assert FALSE
+ report "SEED2 > 2147483398 in UNIFORM"
+ severity ERROR;
+ X := 0.0;
+ return;
+ end if;
+
+ -- Compute new seed values and pseudo-random number
+ K := TSEED1/53668;
+ TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
+
+ if TSEED1 < 0 then
+ TSEED1 := TSEED1 + 2147483563;
+ end if;
+
+ K := TSEED2/52774;
+ TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
+
+ if TSEED2 < 0 then
+ TSEED2 := TSEED2 + 2147483399;
+ end if;
+
+ Z := TSEED1 - TSEED2;
+ if Z < 1 then
+ Z := Z + 2147483562;
+ end if;
+
+ -- Get output values
+ SEED1 := POSITIVE'(TSEED1);
+ SEED2 := POSITIVE'(TSEED2);
+ X := REAL(Z)*4.656613e-10;
+ end UNIFORM;
+
+
+
+ function SQRT (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Uses the Newton-Raphson approximation:
+ -- F(n+1) = 0.5*[F(n) + x/F(n)]
+ -- b) Returns 0.0 on error
+ --
+
+ constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
+
+ variable INIVAL: REAL;
+ variable OLDVAL : REAL ;
+ variable NEWVAL : REAL ;
+ variable COUNT : INTEGER := 1;
+
+ begin
+ -- Check validity of argument
+ if ( X < 0.0 ) then
+ assert FALSE
+ report "X < 0.0 in SQRT(X)"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Get the square root for special cases
+ if X = 0.0 then
+ return 0.0;
+ else
+ if ( X = 1.0 ) then
+ return 1.0;
+ end if;
+ end if;
+
+ -- Get the square root for general cases
+ INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
+ OLDVAL := INIVAL;
+ NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+
+ -- Check for relative and absolute error and max count
+ while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
+ (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+ (COUNT < MAX_COUNT) ) loop
+ OLDVAL := NEWVAL;
+ NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+ COUNT := COUNT + 1;
+ end loop;
+ return NEWVAL;
+ end SQRT;
+
+ function CBRT (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Uses the Newton-Raphson approximation:
+ -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
+ --
+ constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+ variable INIVAL: REAL;
+ variable XLOCAL : REAL := X;
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable OLDVAL : REAL ;
+ variable NEWVAL : REAL ;
+ variable COUNT : INTEGER := 1;
+
+ begin
+
+ -- Compute root for special cases
+ if X = 0.0 then
+ return 0.0;
+ elsif ( X = 1.0 ) then
+ return 1.0;
+ else
+ if X = -1.0 then
+ return -1.0;
+ end if;
+ end if;
+
+ -- Compute root for general cases
+ if NEGATIVE then
+ XLOCAL := -X;
+ end if;
+
+ INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
+ -- imprecise
+ OLDVAL := INIVAL;
+ NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+
+ -- Check for relative and absolute errors and max count
+ while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
+ (ABS(NEWVAL - OLDVAL) > EPS ) ) AND
+ ( COUNT < MAX_COUNT ) ) loop
+ OLDVAL := NEWVAL;
+ NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+ COUNT := COUNT + 1;
+ end loop;
+
+ if NEGATIVE then
+ NEWVAL := -NEWVAL;
+ end if;
+
+ return NEWVAL;
+ end CBRT;
+
+ function "**" (X : in INTEGER; Y : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error condition
+
+ begin
+ -- Check validity of argument
+ if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
+ assert FALSE
+ report "X < 0 and Y /= 0.0 in X**Y"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
+ assert FALSE
+ report "X = 0 and Y <= 0.0 in X**Y"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Get value for special cases
+ if ( X = 0 and Y > 0.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = 1 ) then
+ return 1.0;
+ end if;
+
+ if ( Y = 0.0 and X /= 0 ) then
+ return 1.0;
+ end if;
+
+ if ( Y = 1.0) then
+ return (REAL(X));
+ end if;
+
+ -- Get value for general case
+ return EXP (Y * LOG (REAL(X)));
+ end "**";
+
+ function "**" (X : in REAL; Y : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error condition
+
+ begin
+ -- Check validity of argument
+ if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
+ assert FALSE
+ report "X < 0.0 and Y /= 0.0 in X**Y"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
+ assert FALSE
+ report "X = 0.0 and Y <= 0.0 in X**Y"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Get value for special cases
+ if ( X = 0.0 and Y > 0.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = 1.0 ) then
+ return 1.0;
+ end if;
+
+ if ( Y = 0.0 and X /= 0.0 ) then
+ return 1.0;
+ end if;
+
+ if ( Y = 1.0) then
+ return (X);
+ end if;
+
+ -- Get value for general case
+ return EXP (Y * LOG (X));
+ end "**";
+
+ function EXP (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) This function computes the exponential using the following
+ -- series:
+ -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
+ -- and reduces argument X to take advantage of exp(x+y) =
+ -- exp(x)*exp(y)
+ --
+ -- b) This implementation limits X to be less than LOG(REAL'HIGH)
+ -- to avoid overflow. Returns REAL'HIGH when X reaches that
+ -- limit
+ --
+ constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
+
+ variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
+ variable XLOCAL : REAL := ABS(X); -- Use positive value
+ variable OLDVAL: REAL ;
+ variable COUNT: INTEGER ;
+ variable NEWVAL: REAL ;
+ variable LAST_TERM: REAL ;
+ variable FACTOR : REAL := 1.0;
+
+ begin
+ -- Compute value for special cases
+ if X = 0.0 then
+ return 1.0;
+ end if;
+
+ if XLOCAL = 1.0 then
+ if RECIPROCAL then
+ return MATH_1_OVER_E;
+ else
+ return MATH_E;
+ end if;
+ end if;
+
+ if XLOCAL = 2.0 then
+ if RECIPROCAL then
+ return 1.0/MATH_E_P2;
+ else
+ return MATH_E_P2;
+ end if;
+ end if;
+
+ if XLOCAL = 10.0 then
+ if RECIPROCAL then
+ return 1.0/MATH_E_P10;
+ else
+ return MATH_E_P10;
+ end if;
+ end if;
+
+ if XLOCAL > LOG(REAL'HIGH) then
+ if RECIPROCAL then
+ return 0.0;
+ else
+ assert FALSE
+ report "X > LOG(REAL'HIGH) in EXP(X)"
+ severity NOTE;
+ return REAL'HIGH;
+ end if;
+ end if;
+
+ -- Reduce argument to ABS(X) < 1.0
+ while XLOCAL > 10.0 loop
+ XLOCAL := XLOCAL - 10.0;
+ FACTOR := FACTOR*MATH_E_P10;
+ end loop;
+
+ while XLOCAL > 1.0 loop
+ XLOCAL := XLOCAL - 1.0;
+ FACTOR := FACTOR*MATH_E;
+ end loop;
+
+ -- Compute value for case 0 < XLOCAL < 1
+ OLDVAL := 1.0;
+ LAST_TERM := XLOCAL;
+ NEWVAL:= OLDVAL + LAST_TERM;
+ COUNT := 2;
+
+ -- Check for relative and absolute errors and max count
+ while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
+ (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+ (COUNT < MAX_COUNT ) ) loop
+ OLDVAL := NEWVAL;
+ LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
+ NEWVAL := OLDVAL + LAST_TERM;
+ COUNT := COUNT + 1;
+ end loop;
+
+ -- Compute final value using exp(x+y) = exp(x)*exp(y)
+ NEWVAL := NEWVAL*FACTOR;
+
+ if RECIPROCAL then
+ NEWVAL := 1.0/NEWVAL;
+ end if;
+
+ return NEWVAL;
+ end EXP;
+
+
+ --
+ -- Auxiliary Functions to Compute LOG
+ --
+ function ILOGB(X: in REAL) return INTEGER IS
+ -- Description:
+ -- Returns n such that -1 <= ABS(X)/2^n < 2
+ -- Notes:
+ -- None
+
+ variable N: INTEGER := 0;
+ variable Y: REAL := ABS(X);
+
+ begin
+ if(Y = 1.0 or Y = 0.0) then
+ return 0;
+ end if;
+
+ if( Y > 1.0) then
+ while Y >= 2.0 loop
+ Y := Y/2.0;
+ N := N+1;
+ end loop;
+ return N;
+ end if;
+
+ -- O < Y < 1
+ while Y < 1.0 loop
+ Y := Y*2.0;
+ N := N -1;
+ end loop;
+ return N;
+ end ILOGB;
+
+ function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
+ -- Description:
+ -- Returns X*2^n
+ -- Notes:
+ -- None
+ begin
+ return X*(2.0 ** N);
+ end LDEXP;
+
+ function LOG (X : in REAL ) return REAL IS
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ --
+ -- Notes:
+ -- a) Returns REAL'LOW on error
+ --
+ -- Copyright (c) 1992 Regents of the University of California.
+ -- All rights reserved.
+ --
+ -- Redistribution and use in source and binary forms, with or without
+ -- modification, are permitted provided that the following conditions
+ -- are met:
+ -- 1. Redistributions of source code must retain the above copyright
+ -- notice, this list of conditions and the following disclaimer.
+ -- 2. Redistributions in binary form must reproduce the above copyright
+ -- notice, this list of conditions and the following disclaimer in the
+ -- documentation and/or other materials provided with the distribution.
+ -- 3. All advertising materials mentioning features or use of this
+ -- software must display the following acknowledgement:
+ -- This product includes software developed by the University of
+ -- California, Berkeley and its contributors.
+ -- 4. Neither the name of the University nor the names of its
+ -- contributors may be used to endorse or promote products derived
+ -- from this software without specific prior written permission.
+ --
+ -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+ -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
+ -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ -- DAMAGE.
+ --
+ -- NOTE: This VHDL version was generated using the C version of the
+ -- original function by the IEEE VHDL Mathematical Package
+ -- Working Group (CS/JT)
+
+ constant N: INTEGER := 128;
+
+ -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
+ -- Used for generation of extend precision logarithms.
+ -- The constant 35184372088832 is 2^45, so the divide is exact.
+ -- It ensures correct reading of logF_head, even for inaccurate
+ -- decimal-to-binary conversion routines. (Everybody gets the
+ -- right answer for INTEGERs less than 2^53.)
+ -- Values for LOG(F) were generated using error < 10^-57 absolute
+ -- with the bc -l package.
+
+ type REAL_VECTOR is array (NATURAL range <>) of REAL;
+
+ constant A1:REAL := 0.08333333333333178827;
+ constant A2:REAL := 0.01250000000377174923;
+ constant A3:REAL := 0.002232139987919447809;
+ constant A4:REAL := 0.0004348877777076145742;
+
+ constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
+ 0.0,
+ 0.007782140442060381246,
+ 0.015504186535963526694,
+ 0.023167059281547608406,
+ 0.030771658666765233647,
+ 0.038318864302141264488,
+ 0.045809536031242714670,
+ 0.053244514518837604555,
+ 0.060624621816486978786,
+ 0.067950661908525944454,
+ 0.075223421237524235039,
+ 0.082443669210988446138,
+ 0.089612158689760690322,
+ 0.096729626458454731618,
+ 0.103796793681567578460,
+ 0.110814366340264314203,
+ 0.117783035656430001836,
+ 0.124703478501032805070,
+ 0.131576357788617315236,
+ 0.138402322859292326029,
+ 0.145182009844575077295,
+ 0.151916042025732167530,
+ 0.158605030176659056451,
+ 0.165249572895390883786,
+ 0.171850256926518341060,
+ 0.178407657472689606947,
+ 0.184922338493834104156,
+ 0.191394852999565046047,
+ 0.197825743329758552135,
+ 0.204215541428766300668,
+ 0.210564769107350002741,
+ 0.216873938300523150246,
+ 0.223143551314024080056,
+ 0.229374101064877322642,
+ 0.235566071312860003672,
+ 0.241719936886966024758,
+ 0.247836163904594286577,
+ 0.253915209980732470285,
+ 0.259957524436686071567,
+ 0.265963548496984003577,
+ 0.271933715484010463114,
+ 0.277868451003087102435,
+ 0.283768173130738432519,
+ 0.289633292582948342896,
+ 0.295464212893421063199,
+ 0.301261330578199704177,
+ 0.307025035294827830512,
+ 0.312755710004239517729,
+ 0.318453731118097493890,
+ 0.324119468654316733591,
+ 0.329753286372579168528,
+ 0.335355541920762334484,
+ 0.340926586970454081892,
+ 0.346466767346100823488,
+ 0.351976423156884266063,
+ 0.357455888922231679316,
+ 0.362905493689140712376,
+ 0.368325561158599157352,
+ 0.373716409793814818840,
+ 0.379078352934811846353,
+ 0.384411698910298582632,
+ 0.389716751140440464951,
+ 0.394993808240542421117,
+ 0.400243164127459749579,
+ 0.405465108107819105498,
+ 0.410659924985338875558,
+ 0.415827895143593195825,
+ 0.420969294644237379543,
+ 0.426084395310681429691,
+ 0.431173464818130014464,
+ 0.436236766774527495726,
+ 0.441274560805140936281,
+ 0.446287102628048160113,
+ 0.451274644139630254358,
+ 0.456237433481874177232,
+ 0.461175715122408291790,
+ 0.466089729924533457960,
+ 0.470979715219073113985,
+ 0.475845904869856894947,
+ 0.480688529345570714212,
+ 0.485507815781602403149,
+ 0.490303988045525329653,
+ 0.495077266798034543171,
+ 0.499827869556611403822,
+ 0.504556010751912253908,
+ 0.509261901790523552335,
+ 0.513945751101346104405,
+ 0.518607764208354637958,
+ 0.523248143765158602036,
+ 0.527867089620485785417,
+ 0.532464798869114019908,
+ 0.537041465897345915436,
+ 0.541597282432121573947,
+ 0.546132437597407260909,
+ 0.550647117952394182793,
+ 0.555141507540611200965,
+ 0.559615787935399566777,
+ 0.564070138285387656651,
+ 0.568504735352689749561,
+ 0.572919753562018740922,
+ 0.577315365035246941260,
+ 0.581691739635061821900,
+ 0.586049045003164792433,
+ 0.590387446602107957005,
+ 0.594707107746216934174,
+ 0.599008189645246602594,
+ 0.603290851438941899687,
+ 0.607555250224322662688,
+ 0.611801541106615331955,
+ 0.616029877215623855590,
+ 0.620240409751204424537,
+ 0.624433288012369303032,
+ 0.628608659422752680256,
+ 0.632766669570628437213,
+ 0.636907462236194987781,
+ 0.641031179420679109171,
+ 0.645137961373620782978,
+ 0.649227946625615004450,
+ 0.653301272011958644725,
+ 0.657358072709030238911,
+ 0.661398482245203922502,
+ 0.665422632544505177065,
+ 0.669430653942981734871,
+ 0.673422675212350441142,
+ 0.677398823590920073911,
+ 0.681359224807238206267,
+ 0.685304003098281100392,
+ 0.689233281238557538017,
+ 0.693147180560117703862);
+
+ constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
+ 0.0,
+ -0.00000000000000543229938420049,
+ 0.00000000000000172745674997061,
+ -0.00000000000001323017818229233,
+ -0.00000000000001154527628289872,
+ -0.00000000000000466529469958300,
+ 0.00000000000005148849572685810,
+ -0.00000000000002532168943117445,
+ -0.00000000000005213620639136504,
+ -0.00000000000001819506003016881,
+ 0.00000000000006329065958724544,
+ 0.00000000000008614512936087814,
+ -0.00000000000007355770219435028,
+ 0.00000000000009638067658552277,
+ 0.00000000000007598636597194141,
+ 0.00000000000002579999128306990,
+ -0.00000000000004654729747598444,
+ -0.00000000000007556920687451336,
+ 0.00000000000010195735223708472,
+ -0.00000000000017319034406422306,
+ -0.00000000000007718001336828098,
+ 0.00000000000010980754099855238,
+ -0.00000000000002047235780046195,
+ -0.00000000000008372091099235912,
+ 0.00000000000014088127937111135,
+ 0.00000000000012869017157588257,
+ 0.00000000000017788850778198106,
+ 0.00000000000006440856150696891,
+ 0.00000000000016132822667240822,
+ -0.00000000000007540916511956188,
+ -0.00000000000000036507188831790,
+ 0.00000000000009120937249914984,
+ 0.00000000000018567570959796010,
+ -0.00000000000003149265065191483,
+ -0.00000000000009309459495196889,
+ 0.00000000000017914338601329117,
+ -0.00000000000001302979717330866,
+ 0.00000000000023097385217586939,
+ 0.00000000000023999540484211737,
+ 0.00000000000015393776174455408,
+ -0.00000000000036870428315837678,
+ 0.00000000000036920375082080089,
+ -0.00000000000009383417223663699,
+ 0.00000000000009433398189512690,
+ 0.00000000000041481318704258568,
+ -0.00000000000003792316480209314,
+ 0.00000000000008403156304792424,
+ -0.00000000000034262934348285429,
+ 0.00000000000043712191957429145,
+ -0.00000000000010475750058776541,
+ -0.00000000000011118671389559323,
+ 0.00000000000037549577257259853,
+ 0.00000000000013912841212197565,
+ 0.00000000000010775743037572640,
+ 0.00000000000029391859187648000,
+ -0.00000000000042790509060060774,
+ 0.00000000000022774076114039555,
+ 0.00000000000010849569622967912,
+ -0.00000000000023073801945705758,
+ 0.00000000000015761203773969435,
+ 0.00000000000003345710269544082,
+ -0.00000000000041525158063436123,
+ 0.00000000000032655698896907146,
+ -0.00000000000044704265010452446,
+ 0.00000000000034527647952039772,
+ -0.00000000000007048962392109746,
+ 0.00000000000011776978751369214,
+ -0.00000000000010774341461609578,
+ 0.00000000000021863343293215910,
+ 0.00000000000024132639491333131,
+ 0.00000000000039057462209830700,
+ -0.00000000000026570679203560751,
+ 0.00000000000037135141919592021,
+ -0.00000000000017166921336082431,
+ -0.00000000000028658285157914353,
+ -0.00000000000023812542263446809,
+ 0.00000000000006576659768580062,
+ -0.00000000000028210143846181267,
+ 0.00000000000010701931762114254,
+ 0.00000000000018119346366441110,
+ 0.00000000000009840465278232627,
+ -0.00000000000033149150282752542,
+ -0.00000000000018302857356041668,
+ -0.00000000000016207400156744949,
+ 0.00000000000048303314949553201,
+ -0.00000000000071560553172382115,
+ 0.00000000000088821239518571855,
+ -0.00000000000030900580513238244,
+ -0.00000000000061076551972851496,
+ 0.00000000000035659969663347830,
+ 0.00000000000035782396591276383,
+ -0.00000000000046226087001544578,
+ 0.00000000000062279762917225156,
+ 0.00000000000072838947272065741,
+ 0.00000000000026809646615211673,
+ -0.00000000000010960825046059278,
+ 0.00000000000002311949383800537,
+ -0.00000000000058469058005299247,
+ -0.00000000000002103748251144494,
+ -0.00000000000023323182945587408,
+ -0.00000000000042333694288141916,
+ -0.00000000000043933937969737844,
+ 0.00000000000041341647073835565,
+ 0.00000000000006841763641591466,
+ 0.00000000000047585534004430641,
+ 0.00000000000083679678674757695,
+ -0.00000000000085763734646658640,
+ 0.00000000000021913281229340092,
+ -0.00000000000062242842536431148,
+ -0.00000000000010983594325438430,
+ 0.00000000000065310431377633651,
+ -0.00000000000047580199021710769,
+ -0.00000000000037854251265457040,
+ 0.00000000000040939233218678664,
+ 0.00000000000087424383914858291,
+ 0.00000000000025218188456842882,
+ -0.00000000000003608131360422557,
+ -0.00000000000050518555924280902,
+ 0.00000000000078699403323355317,
+ -0.00000000000067020876961949060,
+ 0.00000000000016108575753932458,
+ 0.00000000000058527188436251509,
+ -0.00000000000035246757297904791,
+ -0.00000000000018372084495629058,
+ 0.00000000000088606689813494916,
+ 0.00000000000066486268071468700,
+ 0.00000000000063831615170646519,
+ 0.00000000000025144230728376072,
+ -0.00000000000017239444525614834);
+
+ variable M, J:INTEGER;
+ variable F1, F2, G, Q, U, U2, V: REAL;
+ variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
+ variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
+
+ -- double logb(), ldexp();
+
+ variable U1:REAL;
+
+ begin
+
+ -- Check validity of argument
+ if ( X <= 0.0 ) then
+ assert FALSE
+ report "X <= 0.0 in LOG(X)"
+ severity ERROR;
+ return(REAL'LOW);
+ end if;
+
+ -- Compute value for special cases
+ if ( X = 1.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = MATH_E ) then
+ return 1.0;
+ end if;
+
+ -- Argument reduction: 1 <= g < 2; x/2^m = g;
+ -- y = F*(1 + f/F) for |f| <= 2^-8
+
+ M := ILOGB(X);
+ G := LDEXP(X, -M);
+ J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
+ F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
+ F2 := G - F1;
+
+ -- Approximate expansion for log(1+f2/F1) ~= u + q
+ G := 1.0/(2.0*F1+F2);
+ U := 2.0*F2*G;
+ V := U*U;
+ Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
+
+ -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
+ -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
+ -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
+ --
+ if ( J /= 0 or M /= 0) then
+ U1 := U + 513.0;
+ U1 := U1 - 513.0;
+
+ -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
+ -- u1 = u to 24 bits.
+ --
+ else
+ U1 := U;
+ --TRUNC(U1); --In c this is u1 = (double) (float) (u1)
+ end if;
+
+ U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
+ -- u1 + u2 = 2f/(2F+f) to extra precision.
+
+ -- log(x) = log(2^m*F1*(1+f2/F1)) =
+ -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
+ -- (exact) + (tiny)
+
+ U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
+ U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
+ U2 := U2 + LOGF_TAIL(N)*REAL(M);
+ return (U1 + U2);
+ end LOG;
+
+
+ function LOG2 (X: in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns REAL'LOW on error
+ begin
+ -- Check validity of arguments
+ if ( X <= 0.0 ) then
+ assert FALSE
+ report "X <= 0.0 in LOG2(X)"
+ severity ERROR;
+ return(REAL'LOW);
+ end if;
+
+ -- Compute value for special cases
+ if ( X = 1.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = 2.0 ) then
+ return 1.0;
+ end if;
+
+ -- Compute value for general case
+ return ( MATH_LOG2_OF_E*LOG(X) );
+ end LOG2;
+
+
+ function LOG10 (X: in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns REAL'LOW on error
+ begin
+ -- Check validity of arguments
+ if ( X <= 0.0 ) then
+ assert FALSE
+ report "X <= 0.0 in LOG10(X)"
+ severity ERROR;
+ return(REAL'LOW);
+ end if;
+
+ -- Compute value for special cases
+ if ( X = 1.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = 10.0 ) then
+ return 1.0;
+ end if;
+
+ -- Compute value for general case
+ return ( MATH_LOG10_OF_E*LOG(X) );
+ end LOG10;
+
+
+ function LOG (X: in REAL; BASE: in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns REAL'LOW on error
+ begin
+ -- Check validity of arguments
+ if ( X <= 0.0 ) then
+ assert FALSE
+ report "X <= 0.0 in LOG(X, BASE)"
+ severity ERROR;
+ return(REAL'LOW);
+ end if;
+
+ if ( BASE <= 0.0 or BASE = 1.0 ) then
+ assert FALSE
+ report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
+ severity ERROR;
+ return(REAL'LOW);
+ end if;
+
+ -- Compute value for special cases
+ if ( X = 1.0 ) then
+ return 0.0;
+ end if;
+
+ if ( X = BASE ) then
+ return 1.0;
+ end if;
+
+ -- Compute value for general case
+ return ( LOG(X)/LOG(BASE));
+ end LOG;
+
+
+ function SIN (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) SIN(-X) = -SIN(X)
+ -- b) SIN(X) = X if ABS(X) < EPS
+ -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
+ -- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
+ -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
+ -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+ -- EPS< ABS(X) <BASE_EPS
+
+ constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
+
+ variable N : INTEGER;
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X) ;
+ variable VALUE: REAL;
+ variable TEMP : REAL;
+
+ begin
+ -- Make XLOCAL < MATH_2_PI
+ if XLOCAL > MATH_2_PI then
+ TEMP := FLOOR(XLOCAL/MATH_2_PI);
+ XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+ end if;
+
+ if XLOCAL < 0.0 then
+ assert FALSE
+ report "XLOCAL <= 0.0 after reduction in SIN(X)"
+ severity ERROR;
+ XLOCAL := -XLOCAL;
+ end if;
+
+ -- Compute value for special cases
+ if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
+ return 0.0;
+ end if;
+
+ if XLOCAL = MATH_PI_OVER_2 then
+ if NEGATIVE then
+ return -1.0;
+ else
+ return 1.0;
+ end if;
+ end if;
+
+ if XLOCAL = MATH_3_PI_OVER_2 then
+ if NEGATIVE then
+ return 1.0;
+ else
+ return -1.0;
+ end if;
+ end if;
+
+ if XLOCAL < EPS then
+ if NEGATIVE then
+ return -XLOCAL;
+ else
+ return XLOCAL;
+ end if;
+ else
+ if XLOCAL < BASE_EPS then
+ TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
+ if NEGATIVE then
+ return -TEMP;
+ else
+ return TEMP;
+ end if;
+ end if;
+ end if;
+
+ TEMP := MATH_PI - XLOCAL;
+ if ABS(TEMP) < EPS then
+ if NEGATIVE then
+ return -TEMP;
+ else
+ return TEMP;
+ end if;
+ else
+ if ABS(TEMP) < BASE_EPS then
+ TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+ if NEGATIVE then
+ return -TEMP;
+ else
+ return TEMP;
+ end if;
+ end if;
+ end if;
+
+ TEMP := MATH_2_PI - XLOCAL;
+ if ABS(TEMP) < EPS then
+ if NEGATIVE then
+ return TEMP;
+ else
+ return -TEMP;
+ end if;
+ else
+ if ABS(TEMP) < BASE_EPS then
+ TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+ if NEGATIVE then
+ return TEMP;
+ else
+ return -TEMP;
+ end if;
+ end if;
+ end if;
+
+ TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
+ if TEMP < EPS then
+ TEMP := 1.0 - TEMP*TEMP*0.5;
+ if NEGATIVE then
+ return -TEMP;
+ else
+ return TEMP;
+ end if;
+ else
+ if TEMP < BASE_EPS then
+ TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+ if NEGATIVE then
+ return -TEMP;
+ else
+ return TEMP;
+ end if;
+ end if;
+ end if;
+
+ TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
+ if TEMP < EPS then
+ TEMP := 1.0 - TEMP*TEMP*0.5;
+ if NEGATIVE then
+ return TEMP;
+ else
+ return -TEMP;
+ end if;
+ else
+ if TEMP < BASE_EPS then
+ TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+ if NEGATIVE then
+ return TEMP;
+ else
+ return -TEMP;
+ end if;
+ end if;
+ end if;
+
+ -- Compute value for general cases
+ if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
+ VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
+ end if;
+
+ N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
+ case QUADRANT( N mod 4) is
+ when 0 =>
+ VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
+ when 1 =>
+ VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
+ ROTATION)(0);
+ when 2 =>
+ VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
+ when 3 =>
+ VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
+ ROTATION)(0);
+ end case;
+
+ if NEGATIVE then
+ return -VALUE;
+ else
+ return VALUE;
+ end if;
+ end SIN;
+
+
+ function COS (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) COS(-X) = COS(X)
+ -- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
+ -- c) COS(MATH_PI + X) = -COS(X)
+ -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
+ -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+ -- EPS< ABS(X) <BASE_EPS
+ --
+ constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+ variable XLOCAL : REAL := ABS(X);
+ variable VALUE: REAL;
+ variable TEMP : REAL;
+
+ begin
+ -- Make XLOCAL < MATH_2_PI
+ if XLOCAL > MATH_2_PI then
+ TEMP := FLOOR(XLOCAL/MATH_2_PI);
+ XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+ end if;
+
+ if XLOCAL < 0.0 then
+ assert FALSE
+ report "XLOCAL <= 0.0 after reduction in COS(X)"
+ severity ERROR;
+ XLOCAL := -XLOCAL;
+ end if;
+
+ -- Compute value for special cases
+ if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
+ return 1.0;
+ end if;
+
+ if XLOCAL = MATH_PI then
+ return -1.0;
+ end if;
+
+ if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
+ return 0.0;
+ end if;
+
+ TEMP := ABS(XLOCAL);
+ if ( TEMP < EPS) then
+ return (1.0 - 0.5*TEMP*TEMP);
+ else
+ if (TEMP < BASE_EPS) then
+ return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+ end if;
+ end if;
+
+ TEMP := ABS(XLOCAL -MATH_2_PI);
+ if ( TEMP < EPS) then
+ return (1.0 - 0.5*TEMP*TEMP);
+ else
+ if (TEMP < BASE_EPS) then
+ return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+ end if;
+ end if;
+
+ TEMP := ABS (XLOCAL - MATH_PI);
+ if TEMP < EPS then
+ return (-1.0 + 0.5*TEMP*TEMP);
+ else
+ if (TEMP < BASE_EPS) then
+ return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
+ end if;
+ end if;
+
+ -- Compute value for general cases
+ return SIN(MATH_PI_OVER_2 - XLOCAL);
+ end COS;
+
+ function TAN (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) TAN(0.0) = 0.0
+ -- b) TAN(-X) = -TAN(X)
+ -- c) Returns REAL'LOW on error if X < 0.0
+ -- d) Returns REAL'HIGH on error if X > 0.0
+
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X) ;
+ variable VALUE: REAL;
+ variable TEMP : REAL;
+
+ begin
+ -- Make 0.0 <= XLOCAL <= MATH_2_PI
+ if XLOCAL > MATH_2_PI then
+ TEMP := FLOOR(XLOCAL/MATH_2_PI);
+ XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+ end if;
+
+ if XLOCAL < 0.0 then
+ assert FALSE
+ report "XLOCAL <= 0.0 after reduction in TAN(X)"
+ severity ERROR;
+ XLOCAL := -XLOCAL;
+ end if;
+
+ -- Check validity of argument
+ if XLOCAL = MATH_PI_OVER_2 then
+ assert FALSE
+ report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
+ severity ERROR;
+ if NEGATIVE then
+ return(REAL'LOW);
+ else
+ return(REAL'HIGH);
+ end if;
+ end if;
+
+ if XLOCAL = MATH_3_PI_OVER_2 then
+ assert FALSE
+ report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
+ severity ERROR;
+ if NEGATIVE then
+ return(REAL'HIGH);
+ else
+ return(REAL'LOW);
+ end if;
+ end if;
+
+ -- Compute value for special cases
+ if XLOCAL = 0.0 or XLOCAL = MATH_PI then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ VALUE := SIN(XLOCAL)/COS(XLOCAL);
+ if NEGATIVE then
+ return -VALUE;
+ else
+ return VALUE;
+ end if;
+ end TAN;
+
+ function ARCSIN (X : in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) ARCSIN(-X) = -ARCSIN(X)
+ -- b) Returns X on error
+
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X);
+ variable VALUE : REAL;
+
+ begin
+ -- Check validity of arguments
+ if XLOCAL > 1.0 then
+ assert FALSE
+ report "ABS(X) > 1.0 in ARCSIN(X)"
+ severity ERROR;
+ return X;
+ end if;
+
+ -- Compute value for special cases
+ if XLOCAL = 0.0 then
+ return 0.0;
+ elsif XLOCAL = 1.0 then
+ if NEGATIVE then
+ return -MATH_PI_OVER_2;
+ else
+ return MATH_PI_OVER_2;
+ end if;
+ end if;
+
+ -- Compute value for general cases
+ if XLOCAL < 0.9 then
+ VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
+ else
+ VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+ end if;
+
+ if NEGATIVE then
+ VALUE := -VALUE;
+ end if;
+
+ return VALUE;
+ end ARCSIN;
+
+ function ARCCOS (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
+ -- b) Returns X on error
+
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X);
+ variable VALUE : REAL;
+
+ begin
+ -- Check validity of argument
+ if XLOCAL > 1.0 then
+ assert FALSE
+ report "ABS(X) > 1.0 in ARCCOS(X)"
+ severity ERROR;
+ return X;
+ end if;
+
+ -- Compute value for special cases
+ if X = 1.0 then
+ return 0.0;
+ elsif X = 0.0 then
+ return MATH_PI_OVER_2;
+ elsif X = -1.0 then
+ return MATH_PI;
+ end if;
+
+ -- Compute value for general cases
+ if XLOCAL > 0.9 then
+ VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+ else
+ VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
+ end if;
+
+
+ if NEGATIVE then
+ VALUE := MATH_PI - VALUE;
+ end if;
+
+ return VALUE;
+ end ARCCOS;
+
+
+ function ARCTAN (Y : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) ARCTAN(-Y) = -ARCTAN(Y)
+ -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
+ -- c) ARCTAN(Y) = Y for |Y| < EPS
+
+ constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
+
+ variable NEGATIVE : BOOLEAN := Y < 0.0;
+ variable RECIPROCAL : BOOLEAN;
+ variable YLOCAL : REAL := ABS(Y);
+ variable VALUE : REAL;
+
+ begin
+ -- Make argument |Y| <=1.0
+ if YLOCAL > 1.0 then
+ YLOCAL := 1.0/YLOCAL;
+ RECIPROCAL := TRUE;
+ else
+ RECIPROCAL := FALSE;
+ end if;
+
+ -- Compute value for special cases
+ if YLOCAL = 0.0 then
+ if RECIPROCAL then
+ if NEGATIVE then
+ return (-MATH_PI_OVER_2);
+ else
+ return (MATH_PI_OVER_2);
+ end if;
+ else
+ return 0.0;
+ end if;
+ end if;
+
+ if YLOCAL < EPS then
+ if NEGATIVE then
+ if RECIPROCAL then
+ return (-MATH_PI_OVER_2 + YLOCAL);
+ else
+ return -YLOCAL;
+ end if;
+ else
+ if RECIPROCAL then
+ return (MATH_PI_OVER_2 - YLOCAL);
+ else
+ return YLOCAL;
+ end if;
+ end if;
+ end if;
+
+ -- Compute value for general cases
+ VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
+
+ if RECIPROCAL then
+ VALUE := MATH_PI_OVER_2 - VALUE;
+ end if;
+
+ if NEGATIVE then
+ VALUE := -VALUE;
+ end if;
+
+ return VALUE;
+ end ARCTAN;
+
+
+ function ARCTAN (Y : in REAL; X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error
+
+ variable YLOCAL : REAL;
+ variable VALUE : REAL;
+ begin
+
+ -- Check validity of arguments
+ if (Y = 0.0 and X = 0.0 ) then
+ assert FALSE report
+ "ARCTAN(0.0, 0.0) is undetermined"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Compute value for special cases
+ if Y = 0.0 then
+ if X > 0.0 then
+ return 0.0;
+ else
+ return MATH_PI;
+ end if;
+ end if;
+
+ if X = 0.0 then
+ if Y > 0.0 then
+ return MATH_PI_OVER_2;
+ else
+ return -MATH_PI_OVER_2;
+ end if;
+ end if;
+
+
+ -- Compute value for general cases
+ YLOCAL := ABS(Y/X);
+
+ VALUE := ARCTAN(YLOCAL);
+
+ if X < 0.0 then
+ VALUE := MATH_PI - VALUE;
+ end if;
+
+ if Y < 0.0 then
+ VALUE := -VALUE;
+ end if;
+
+ return VALUE;
+ end ARCTAN;
+
+
+ function SINH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns (EXP(X) - EXP(-X))/2.0
+ -- b) SINH(-X) = SINH(X)
+
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X);
+ variable TEMP : REAL;
+ variable VALUE : REAL;
+
+ begin
+ -- Compute value for special cases
+ if XLOCAL = 0.0 then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ TEMP := EXP(XLOCAL);
+ VALUE := (TEMP - 1.0/TEMP)*0.5;
+
+ if NEGATIVE then
+ VALUE := -VALUE;
+ end if;
+
+ return VALUE;
+ end SINH;
+
+ function COSH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns (EXP(X) + EXP(-X))/2.0
+ -- b) COSH(-X) = COSH(X)
+
+ variable XLOCAL : REAL := ABS(X);
+ variable TEMP : REAL;
+ variable VALUE : REAL;
+ begin
+ -- Compute value for special cases
+ if XLOCAL = 0.0 then
+ return 1.0;
+ end if;
+
+
+ -- Compute value for general cases
+ TEMP := EXP(XLOCAL);
+ VALUE := (TEMP + 1.0/TEMP)*0.5;
+
+ return VALUE;
+ end COSH;
+
+ function TANH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
+ -- b) TANH(-X) = -TANH(X)
+
+ variable NEGATIVE : BOOLEAN := X < 0.0;
+ variable XLOCAL : REAL := ABS(X);
+ variable TEMP : REAL;
+ variable VALUE : REAL;
+
+ begin
+ -- Compute value for special cases
+ if XLOCAL = 0.0 then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ TEMP := EXP(XLOCAL);
+ VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
+
+ if NEGATIVE then
+ return -VALUE;
+ else
+ return VALUE;
+ end if;
+ end TANH;
+
+ function ARCSINH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns LOG( X + SQRT( X*X + 1.0))
+
+ begin
+ -- Compute value for special cases
+ if X = 0.0 then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ return ( LOG( X + SQRT( X*X + 1.0)) );
+ end ARCSINH;
+
+
+
+ function ARCCOSH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
+ -- b) Returns X on error
+
+ begin
+ -- Check validity of arguments
+ if X < 1.0 then
+ assert FALSE
+ report "X < 1.0 in ARCCOSH(X)"
+ severity ERROR;
+ return X;
+ end if;
+
+ -- Compute value for special cases
+ if X = 1.0 then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ return ( LOG( X + SQRT( X*X - 1.0)));
+ end ARCCOSH;
+
+ function ARCTANH (X : in REAL) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
+ -- b) Returns X on error
+ begin
+ -- Check validity of arguments
+ if ABS(X) >= 1.0 then
+ assert FALSE
+ report "ABS(X) >= 1.0 in ARCTANH(X)"
+ severity ERROR;
+ return X;
+ end if;
+
+ -- Compute value for special cases
+ if X = 0.0 then
+ return 0.0;
+ end if;
+
+ -- Compute value for general cases
+ return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
+ end ARCTANH;
+
+end MATH_REAL;
--- /dev/null
+(edif FIFO_36x128_DynThr_OutReg
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2015 9 10 11 4 28)
+ (program "SCUBA" (version "Diamond (64-bit) 3.5.0.102"))))
+ (comment "/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf 0 ")
+ (library ORCLIB
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+ (technology
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+ (port CI
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+ (port GE
+ (direction OUTPUT)))))
+ (cell ALEB2
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+ (port Empty
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+ (port Full
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+ (property NGD_DRC_MASK (integer 1))
+ (contents
+ (instance AND2_t5
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+ (instance INV_5
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+ (cellRef INV)))
+ (instance AND2_t4
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+ (instance INV_4
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+ (instance AND2_t3
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+ (instance XOR2_t2
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+ (instance INV_3
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+ (instance INV_2
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+ (instance LUT4_1
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+ (property initval
+ (string "0x3232")))
+ (instance LUT4_0
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x3232")))
+ (instance AND2_t1
+ (viewRef view1
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+ (instance INV_1
+ (viewRef view1
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+ (instance XOR2_t0
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance INV_0
+ (viewRef view1
+ (cellRef INV)))
+ (instance pdp_ram_0_0_0
+ (viewRef view1
+ (cellRef PDPW16KC))
+ (property MEM_LPC_FILE
+ (string "FIFO_36x128_DynThr_OutReg.lpc"))
+ (property MEM_INIT_FILE
+ (string ""))
+ (property CSDECODE_R
+ (string "0b001"))
+ (property CSDECODE_W
+ (string "0b001"))
+ (property GSR
+ (string "DISABLED"))
+ (property RESETMODE
+ (string "SYNC"))
+ (property REGMODE
+ (string "OUTREG"))
+ (property DATA_WIDTH_R
+ (string "36"))
+ (property DATA_WIDTH_W
+ (string "36")))
+ (instance FF_50
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_49
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_48
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_47
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_46
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_45
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_44
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_43
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_42
+ (viewRef view1
+ (cellRef FD1S3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_41
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_40
+ (viewRef view1
+ (cellRef FD1P3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_39
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_38
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_37
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_36
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_35
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_34
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_33
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_32
+ (viewRef view1
+ (cellRef FD1P3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_31
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_30
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_29
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_28
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_27
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_26
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_25
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_24
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_23
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_22
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_21
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_20
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_19
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_18
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_17
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_16
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_15
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_14
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_13
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_12
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_11
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_10
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_9
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_8
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_7
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_6
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_5
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_4
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_3
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_2
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_1
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_0
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance bdcnt_bctr_cia
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance bdcnt_bctr_0
+ (viewRef view1
+ (cellRef CB2)))
+ (instance bdcnt_bctr_1
+ (viewRef view1
+ (cellRef CB2)))
+ (instance bdcnt_bctr_2
+ (viewRef view1
+ (cellRef CB2)))
+ (instance bdcnt_bctr_3
+ (viewRef view1
+ (cellRef CB2)))
+ (instance e_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance e_cmp_0
+ (viewRef view1
+ (cellRef ALEB2)))
+ (instance e_cmp_1
+ (viewRef view1
+ (cellRef ALEB2)))
+ (instance e_cmp_2
+ (viewRef view1
+ (cellRef ALEB2)))
+ (instance e_cmp_3
+ (viewRef view1
+ (cellRef ALEB2)))
+ (instance a0
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance g_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance g_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance g_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance g_cmp_2
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance g_cmp_3
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance a1
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance w_ctr_cia
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance w_ctr_0
+ (viewRef view1
+ (cellRef CU2)))
+ (instance w_ctr_1
+ (viewRef view1
+ (cellRef CU2)))
+ (instance w_ctr_2
+ (viewRef view1
+ (cellRef CU2)))
+ (instance w_ctr_3
+ (viewRef view1
+ (cellRef CU2)))
+ (instance scuba_vhi_inst
+ (viewRef view1
+ (cellRef VHI)))
+ (instance r_ctr_cia
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance r_ctr_0
+ (viewRef view1
+ (cellRef CU2)))
+ (instance r_ctr_1
+ (viewRef view1
+ (cellRef CU2)))
+ (instance r_ctr_2
+ (viewRef view1
+ (cellRef CU2)))
+ (instance r_ctr_3
+ (viewRef view1
+ (cellRef CU2)))
+ (instance precin_inst237
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance wcnt_0
+ (viewRef view1
+ (cellRef FSUB2B)))
+ (instance wcnt_1
+ (viewRef view1
+ (cellRef FSUB2B)))
+ (instance wcnt_2
+ (viewRef view1
+ (cellRef FSUB2B)))
+ (instance wcnt_3
+ (viewRef view1
+ (cellRef FSUB2B)))
+ (instance wcnt_4
+ (viewRef view1
+ (cellRef FSUB2B)))
+ (instance af_set_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance af_set_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_set_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_set_cmp_2
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_set_cmp_3
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vlo_inst
+ (viewRef view1
+ (cellRef VLO)))
+ (instance a2
+ (viewRef view1
+ (cellRef FADD2B)))
+ (net invout_2
+ (joined
+ (portRef Z (instanceRef INV_5))
+ (portRef B (instanceRef AND2_t5))))
+ (net invout_1
+ (joined
+ (portRef Z (instanceRef INV_4))
+ (portRef B (instanceRef AND2_t4))))
+ (net rden_i_inv
+ (joined
+ (portRef Z (instanceRef INV_3))
+ (portRef B (instanceRef AND2_t3))))
+ (net invout_0
+ (joined
+ (portRef Z (instanceRef INV_1))
+ (portRef B (instanceRef AND2_t1))))
+ (net r_nw
+ (joined
+ (portRef Z (instanceRef AND2_t1))))
+ (net fcnt_en
+ (joined
+ (portRef SP (instanceRef FF_43))
+ (portRef Z (instanceRef XOR2_t2))
+ (portRef SP (instanceRef FF_50))
+ (portRef SP (instanceRef FF_49))
+ (portRef SP (instanceRef FF_48))
+ (portRef SP (instanceRef FF_47))
+ (portRef SP (instanceRef FF_46))
+ (portRef SP (instanceRef FF_45))
+ (portRef SP (instanceRef FF_44))))
+ (net empty_d
+ (joined
+ (portRef D (instanceRef FF_42))
+ (portRef DO0 (instanceRef LUT4_1))))
+ (net full_d
+ (joined
+ (portRef D (instanceRef FF_41))
+ (portRef DO0 (instanceRef LUT4_0))))
+ (net wptr_0
+ (joined
+ (portRef Q (instanceRef FF_24))
+ (portRef ADW0 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_1
+ (joined
+ (portRef Q (instanceRef FF_23))
+ (portRef ADW1 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_2
+ (joined
+ (portRef Q (instanceRef FF_22))
+ (portRef ADW2 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_3
+ (joined
+ (portRef Q (instanceRef FF_21))
+ (portRef ADW3 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_4
+ (joined
+ (portRef Q (instanceRef FF_20))
+ (portRef ADW4 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_5
+ (joined
+ (portRef Q (instanceRef FF_19))
+ (portRef ADW5 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_6
+ (joined
+ (portRef Q (instanceRef FF_18))
+ (portRef ADW6 (instanceRef pdp_ram_0_0_0))))
+ (net wptr_7
+ (joined
+ (portRef Q (instanceRef FF_17))))
+ (net rptr_7
+ (joined
+ (portRef Q (instanceRef FF_9))
+ (portRef B (instanceRef XOR2_t0))))
+ (net ifcount_0
+ (joined
+ (portRef NC0 (instanceRef bdcnt_bctr_0))
+ (portRef D (instanceRef FF_50))))
+ (net ifcount_1
+ (joined
+ (portRef NC1 (instanceRef bdcnt_bctr_0))
+ (portRef D (instanceRef FF_49))))
+ (net bdcnt_bctr_ci
+ (joined
+ (portRef CI (instanceRef bdcnt_bctr_0))
+ (portRef COUT (instanceRef bdcnt_bctr_cia))))
+ (net ifcount_2
+ (joined
+ (portRef NC0 (instanceRef bdcnt_bctr_1))
+ (portRef D (instanceRef FF_48))))
+ (net ifcount_3
+ (joined
+ (portRef NC1 (instanceRef bdcnt_bctr_1))
+ (portRef D (instanceRef FF_47))))
+ (net co0
+ (joined
+ (portRef CI (instanceRef bdcnt_bctr_1))
+ (portRef CO (instanceRef bdcnt_bctr_0))))
+ (net ifcount_4
+ (joined
+ (portRef NC0 (instanceRef bdcnt_bctr_2))
+ (portRef D (instanceRef FF_46))))
+ (net ifcount_5
+ (joined
+ (portRef NC1 (instanceRef bdcnt_bctr_2))
+ (portRef D (instanceRef FF_45))))
+ (net co1
+ (joined
+ (portRef CI (instanceRef bdcnt_bctr_2))
+ (portRef CO (instanceRef bdcnt_bctr_1))))
+ (net ifcount_6
+ (joined
+ (portRef NC0 (instanceRef bdcnt_bctr_3))
+ (portRef D (instanceRef FF_44))))
+ (net ifcount_7
+ (joined
+ (portRef NC1 (instanceRef bdcnt_bctr_3))
+ (portRef D (instanceRef FF_43))))
+ (net co3
+ (joined
+ (portRef CO (instanceRef bdcnt_bctr_3))))
+ (net co2
+ (joined
+ (portRef CI (instanceRef bdcnt_bctr_3))
+ (portRef CO (instanceRef bdcnt_bctr_2))))
+ (net cmp_ci
+ (joined
+ (portRef CI (instanceRef e_cmp_0))
+ (portRef COUT (instanceRef e_cmp_ci_a))))
+ (net rden_i
+ (joined
+ (portRef B0 (instanceRef e_cmp_0))
+ (portRef Z (instanceRef AND2_t4))
+ (portRef B (instanceRef XOR2_t2))
+ (portRef A (instanceRef INV_3))
+ (portRef AD1 (instanceRef LUT4_0))
+ (portRef A (instanceRef AND2_t1))
+ (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+ (portRef SP (instanceRef FF_32))
+ (portRef SP (instanceRef FF_31))
+ (portRef SP (instanceRef FF_30))
+ (portRef SP (instanceRef FF_29))
+ (portRef SP (instanceRef FF_28))
+ (portRef SP (instanceRef FF_27))
+ (portRef SP (instanceRef FF_26))
+ (portRef SP (instanceRef FF_25))
+ (portRef SP (instanceRef FF_16))
+ (portRef SP (instanceRef FF_15))
+ (portRef SP (instanceRef FF_14))
+ (portRef SP (instanceRef FF_13))
+ (portRef SP (instanceRef FF_12))
+ (portRef SP (instanceRef FF_11))
+ (portRef SP (instanceRef FF_10))
+ (portRef SP (instanceRef FF_9))))
+ (net co0_1
+ (joined
+ (portRef CI (instanceRef e_cmp_1))
+ (portRef LE (instanceRef e_cmp_0))))
+ (net co1_1
+ (joined
+ (portRef CI (instanceRef e_cmp_2))
+ (portRef LE (instanceRef e_cmp_1))))
+ (net co2_1
+ (joined
+ (portRef CI (instanceRef e_cmp_3))
+ (portRef LE (instanceRef e_cmp_2))))
+ (net cmp_le_1
+ (joined
+ (portRef S0 (instanceRef a0))
+ (portRef AD2 (instanceRef LUT4_1))))
+ (net cmp_le_1_c
+ (joined
+ (portRef CI (instanceRef a0))
+ (portRef LE (instanceRef e_cmp_3))))
+ (net cmp_ci_1
+ (joined
+ (portRef CI (instanceRef g_cmp_0))
+ (portRef COUT (instanceRef g_cmp_ci_a))))
+ (net fcount_0
+ (joined
+ (portRef A0 (instanceRef g_cmp_0))
+ (portRef Q (instanceRef FF_50))
+ (portRef PC0 (instanceRef bdcnt_bctr_0))
+ (portRef A0 (instanceRef e_cmp_0))))
+ (net fcount_1
+ (joined
+ (portRef A1 (instanceRef g_cmp_0))
+ (portRef Q (instanceRef FF_49))
+ (portRef PC1 (instanceRef bdcnt_bctr_0))
+ (portRef A1 (instanceRef e_cmp_0))))
+ (net co0_2
+ (joined
+ (portRef CI (instanceRef g_cmp_1))
+ (portRef GE (instanceRef g_cmp_0))))
+ (net fcount_2
+ (joined
+ (portRef A0 (instanceRef g_cmp_1))
+ (portRef Q (instanceRef FF_48))
+ (portRef PC0 (instanceRef bdcnt_bctr_1))
+ (portRef A0 (instanceRef e_cmp_1))))
+ (net fcount_3
+ (joined
+ (portRef A1 (instanceRef g_cmp_1))
+ (portRef Q (instanceRef FF_47))
+ (portRef PC1 (instanceRef bdcnt_bctr_1))
+ (portRef A1 (instanceRef e_cmp_1))))
+ (net co1_2
+ (joined
+ (portRef CI (instanceRef g_cmp_2))
+ (portRef GE (instanceRef g_cmp_1))))
+ (net fcount_4
+ (joined
+ (portRef A0 (instanceRef g_cmp_2))
+ (portRef Q (instanceRef FF_46))
+ (portRef PC0 (instanceRef bdcnt_bctr_2))
+ (portRef A0 (instanceRef e_cmp_2))))
+ (net fcount_5
+ (joined
+ (portRef A1 (instanceRef g_cmp_2))
+ (portRef Q (instanceRef FF_45))
+ (portRef PC1 (instanceRef bdcnt_bctr_2))
+ (portRef A1 (instanceRef e_cmp_2))))
+ (net co2_2
+ (joined
+ (portRef CI (instanceRef g_cmp_3))
+ (portRef GE (instanceRef g_cmp_2))))
+ (net wren_i_inv
+ (joined
+ (portRef B1 (instanceRef g_cmp_3))
+ (portRef Z (instanceRef INV_2))))
+ (net fcount_6
+ (joined
+ (portRef A0 (instanceRef g_cmp_3))
+ (portRef Q (instanceRef FF_44))
+ (portRef PC0 (instanceRef bdcnt_bctr_3))
+ (portRef A0 (instanceRef e_cmp_3))))
+ (net fcount_7
+ (joined
+ (portRef A1 (instanceRef g_cmp_3))
+ (portRef Q (instanceRef FF_43))
+ (portRef PC1 (instanceRef bdcnt_bctr_3))
+ (portRef A1 (instanceRef e_cmp_3))))
+ (net cmp_ge_d1
+ (joined
+ (portRef S0 (instanceRef a1))
+ (portRef AD2 (instanceRef LUT4_0))))
+ (net cmp_ge_d1_c
+ (joined
+ (portRef CI (instanceRef a1))
+ (portRef GE (instanceRef g_cmp_3))))
+ (net iwcount_0
+ (joined
+ (portRef NC0 (instanceRef w_ctr_0))
+ (portRef D (instanceRef FF_40))))
+ (net iwcount_1
+ (joined
+ (portRef NC1 (instanceRef w_ctr_0))
+ (portRef D (instanceRef FF_39))))
+ (net w_ctr_ci
+ (joined
+ (portRef CI (instanceRef w_ctr_0))
+ (portRef COUT (instanceRef w_ctr_cia))))
+ (net iwcount_2
+ (joined
+ (portRef NC0 (instanceRef w_ctr_1))
+ (portRef D (instanceRef FF_38))))
+ (net iwcount_3
+ (joined
+ (portRef NC1 (instanceRef w_ctr_1))
+ (portRef D (instanceRef FF_37))))
+ (net co0_3
+ (joined
+ (portRef CI (instanceRef w_ctr_1))
+ (portRef CO (instanceRef w_ctr_0))))
+ (net iwcount_4
+ (joined
+ (portRef NC0 (instanceRef w_ctr_2))
+ (portRef D (instanceRef FF_36))))
+ (net iwcount_5
+ (joined
+ (portRef NC1 (instanceRef w_ctr_2))
+ (portRef D (instanceRef FF_35))))
+ (net co1_3
+ (joined
+ (portRef CI (instanceRef w_ctr_2))
+ (portRef CO (instanceRef w_ctr_1))))
+ (net iwcount_6
+ (joined
+ (portRef NC0 (instanceRef w_ctr_3))
+ (portRef D (instanceRef FF_34))))
+ (net iwcount_7
+ (joined
+ (portRef NC1 (instanceRef w_ctr_3))
+ (portRef D (instanceRef FF_33))))
+ (net co3_1
+ (joined
+ (portRef CO (instanceRef w_ctr_3))))
+ (net co2_3
+ (joined
+ (portRef CI (instanceRef w_ctr_3))
+ (portRef CO (instanceRef w_ctr_2))))
+ (net wcount_7
+ (joined
+ (portRef PC1 (instanceRef w_ctr_3))
+ (portRef A (instanceRef XOR2_t0))
+ (portRef Q (instanceRef FF_33))
+ (portRef D (instanceRef FF_17))))
+ (net scuba_vhi
+ (joined
+ (portRef Z (instanceRef scuba_vhi_inst))
+ (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+ (portRef BE3 (instanceRef pdp_ram_0_0_0))
+ (portRef BE2 (instanceRef pdp_ram_0_0_0))
+ (portRef BE1 (instanceRef pdp_ram_0_0_0))
+ (portRef BE0 (instanceRef pdp_ram_0_0_0))
+ (portRef CER (instanceRef pdp_ram_0_0_0))
+ (portRef B0 (instanceRef e_cmp_ci_a))
+ (portRef B1 (instanceRef e_cmp_ci_a))
+ (portRef A0 (instanceRef e_cmp_ci_a))
+ (portRef A1 (instanceRef e_cmp_ci_a))
+ (portRef B0 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef g_cmp_ci_a))
+ (portRef A0 (instanceRef g_cmp_ci_a))
+ (portRef A1 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef w_ctr_cia))
+ (portRef A1 (instanceRef w_ctr_cia))
+ (portRef B1 (instanceRef r_ctr_cia))
+ (portRef A1 (instanceRef r_ctr_cia))))
+ (net ircount_0
+ (joined
+ (portRef NC0 (instanceRef r_ctr_0))
+ (portRef D (instanceRef FF_32))))
+ (net ircount_1
+ (joined
+ (portRef NC1 (instanceRef r_ctr_0))
+ (portRef D (instanceRef FF_31))))
+ (net r_ctr_ci
+ (joined
+ (portRef CI (instanceRef r_ctr_0))
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+ (portRef RdEn)
+ (portRef A (instanceRef AND2_t4))))
+ (net wren
+ (joined
+ (portRef WrEn)
+ (portRef A (instanceRef AND2_t5))))
+ (net clk
+ (joined
+ (portRef Clock)
+ (portRef CLKR (instanceRef pdp_ram_0_0_0))
+ (portRef CLKW (instanceRef pdp_ram_0_0_0))
+ (portRef CK (instanceRef FF_50))
+ (portRef CK (instanceRef FF_49))
+ (portRef CK (instanceRef FF_48))
+ (portRef CK (instanceRef FF_47))
+ (portRef CK (instanceRef FF_46))
+ (portRef CK (instanceRef FF_45))
+ (portRef CK (instanceRef FF_44))
+ (portRef CK (instanceRef FF_43))
+ (portRef CK (instanceRef FF_42))
+ (portRef CK (instanceRef FF_41))
+ (portRef CK (instanceRef FF_40))
+ (portRef CK (instanceRef FF_39))
+ (portRef CK (instanceRef FF_38))
+ (portRef CK (instanceRef FF_37))
+ (portRef CK (instanceRef FF_36))
+ (portRef CK (instanceRef FF_35))
+ (portRef CK (instanceRef FF_34))
+ (portRef CK (instanceRef FF_33))
+ (portRef CK (instanceRef FF_32))
+ (portRef CK (instanceRef FF_31))
+ (portRef CK (instanceRef FF_30))
+ (portRef CK (instanceRef FF_29))
+ (portRef CK (instanceRef FF_28))
+ (portRef CK (instanceRef FF_27))
+ (portRef CK (instanceRef FF_26))
+ (portRef CK (instanceRef FF_25))
+ (portRef CK (instanceRef FF_24))
+ (portRef CK (instanceRef FF_23))
+ (portRef CK (instanceRef FF_22))
+ (portRef CK (instanceRef FF_21))
+ (portRef CK (instanceRef FF_20))
+ (portRef CK (instanceRef FF_19))
+ (portRef CK (instanceRef FF_18))
+ (portRef CK (instanceRef FF_17))
+ (portRef CK (instanceRef FF_16))
+ (portRef CK (instanceRef FF_15))
+ (portRef CK (instanceRef FF_14))
+ (portRef CK (instanceRef FF_13))
+ (portRef CK (instanceRef FF_12))
+ (portRef CK (instanceRef FF_11))
+ (portRef CK (instanceRef FF_10))
+ (portRef CK (instanceRef FF_9))
+ (portRef CK (instanceRef FF_8))
+ (portRef CK (instanceRef FF_7))
+ (portRef CK (instanceRef FF_6))
+ (portRef CK (instanceRef FF_5))
+ (portRef CK (instanceRef FF_4))
+ (portRef CK (instanceRef FF_3))
+ (portRef CK (instanceRef FF_2))
+ (portRef CK (instanceRef FF_1))
+ (portRef CK (instanceRef FF_0))))
+ (net datain35
+ (joined
+ (portRef (member Data 0))
+ (portRef DI35 (instanceRef pdp_ram_0_0_0))))
+ (net datain34
+ (joined
+ (portRef (member Data 1))
+ (portRef DI34 (instanceRef pdp_ram_0_0_0))))
+ (net datain33
+ (joined
+ (portRef (member Data 2))
+ (portRef DI33 (instanceRef pdp_ram_0_0_0))))
+ (net datain32
+ (joined
+ (portRef (member Data 3))
+ (portRef DI32 (instanceRef pdp_ram_0_0_0))))
+ (net datain31
+ (joined
+ (portRef (member Data 4))
+ (portRef DI31 (instanceRef pdp_ram_0_0_0))))
+ (net datain30
+ (joined
+ (portRef (member Data 5))
+ (portRef DI30 (instanceRef pdp_ram_0_0_0))))
+ (net datain29
+ (joined
+ (portRef (member Data 6))
+ (portRef DI29 (instanceRef pdp_ram_0_0_0))))
+ (net datain28
+ (joined
+ (portRef (member Data 7))
+ (portRef DI28 (instanceRef pdp_ram_0_0_0))))
+ (net datain27
+ (joined
+ (portRef (member Data 8))
+ (portRef DI27 (instanceRef pdp_ram_0_0_0))))
+ (net datain26
+ (joined
+ (portRef (member Data 9))
+ (portRef DI26 (instanceRef pdp_ram_0_0_0))))
+ (net datain25
+ (joined
+ (portRef (member Data 10))
+ (portRef DI25 (instanceRef pdp_ram_0_0_0))))
+ (net datain24
+ (joined
+ (portRef (member Data 11))
+ (portRef DI24 (instanceRef pdp_ram_0_0_0))))
+ (net datain23
+ (joined
+ (portRef (member Data 12))
+ (portRef DI23 (instanceRef pdp_ram_0_0_0))))
+ (net datain22
+ (joined
+ (portRef (member Data 13))
+ (portRef DI22 (instanceRef pdp_ram_0_0_0))))
+ (net datain21
+ (joined
+ (portRef (member Data 14))
+ (portRef DI21 (instanceRef pdp_ram_0_0_0))))
+ (net datain20
+ (joined
+ (portRef (member Data 15))
+ (portRef DI20 (instanceRef pdp_ram_0_0_0))))
+ (net datain19
+ (joined
+ (portRef (member Data 16))
+ (portRef DI19 (instanceRef pdp_ram_0_0_0))))
+ (net datain18
+ (joined
+ (portRef (member Data 17))
+ (portRef DI18 (instanceRef pdp_ram_0_0_0))))
+ (net datain17
+ (joined
+ (portRef (member Data 18))
+ (portRef DI17 (instanceRef pdp_ram_0_0_0))))
+ (net datain16
+ (joined
+ (portRef (member Data 19))
+ (portRef DI16 (instanceRef pdp_ram_0_0_0))))
+ (net datain15
+ (joined
+ (portRef (member Data 20))
+ (portRef DI15 (instanceRef pdp_ram_0_0_0))))
+ (net datain14
+ (joined
+ (portRef (member Data 21))
+ (portRef DI14 (instanceRef pdp_ram_0_0_0))))
+ (net datain13
+ (joined
+ (portRef (member Data 22))
+ (portRef DI13 (instanceRef pdp_ram_0_0_0))))
+ (net datain12
+ (joined
+ (portRef (member Data 23))
+ (portRef DI12 (instanceRef pdp_ram_0_0_0))))
+ (net datain11
+ (joined
+ (portRef (member Data 24))
+ (portRef DI11 (instanceRef pdp_ram_0_0_0))))
+ (net datain10
+ (joined
+ (portRef (member Data 25))
+ (portRef DI10 (instanceRef pdp_ram_0_0_0))))
+ (net datain9
+ (joined
+ (portRef (member Data 26))
+ (portRef DI9 (instanceRef pdp_ram_0_0_0))))
+ (net datain8
+ (joined
+ (portRef (member Data 27))
+ (portRef DI8 (instanceRef pdp_ram_0_0_0))))
+ (net datain7
+ (joined
+ (portRef (member Data 28))
+ (portRef DI7 (instanceRef pdp_ram_0_0_0))))
+ (net datain6
+ (joined
+ (portRef (member Data 29))
+ (portRef DI6 (instanceRef pdp_ram_0_0_0))))
+ (net datain5
+ (joined
+ (portRef (member Data 30))
+ (portRef DI5 (instanceRef pdp_ram_0_0_0))))
+ (net datain4
+ (joined
+ (portRef (member Data 31))
+ (portRef DI4 (instanceRef pdp_ram_0_0_0))))
+ (net datain3
+ (joined
+ (portRef (member Data 32))
+ (portRef DI3 (instanceRef pdp_ram_0_0_0))))
+ (net datain2
+ (joined
+ (portRef (member Data 33))
+ (portRef DI2 (instanceRef pdp_ram_0_0_0))))
+ (net datain1
+ (joined
+ (portRef (member Data 34))
+ (portRef DI1 (instanceRef pdp_ram_0_0_0))))
+ (net datain0
+ (joined
+ (portRef (member Data 35))
+ (portRef DI0 (instanceRef pdp_ram_0_0_0))))))))
+ (design FIFO_36x128_DynThr_OutReg
+ (cellRef FIFO_36x128_DynThr_OutReg
+ (libraryRef ORCLIB)))
+)
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="FIFO_36x128_DynThr_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 09 10 11:04:29.334" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="FIFO_36x128_DynThr_OutReg.lpc" type="lpc" modified="2015 09 10 11:04:27.000"/>
+ <File name="FIFO_36x128_DynThr_OutReg.vhd" type="top_level_vhdl" modified="2015 09 10 11:04:28.000"/>
+ <File name="FIFO_36x128_DynThr_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 09 10 11:04:28.000"/>
+ <File name="tb_FIFO_36x128_DynThr_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 09 10 11:04:28.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+MODULE FIFO_36x128_DynThr_OutReg DEFIN FIFO_36x128_DynThr_OutReg.vhd
+ SUBMODULE FADD2B
+ INSTANCE a2
+ SUBMODULE VLO
+ INSTANCE scuba_vlo_inst
+ SUBMODULE AGEB2
+ INSTANCE af_set_cmp_3
+ SUBMODULE AGEB2
+ INSTANCE af_set_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE af_set_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE af_set_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE af_set_cmp_ci_a
+ SUBMODULE FSUB2B
+ INSTANCE wcnt_4
+ SUBMODULE FSUB2B
+ INSTANCE wcnt_3
+ SUBMODULE FSUB2B
+ INSTANCE wcnt_2
+ SUBMODULE FSUB2B
+ INSTANCE wcnt_1
+ SUBMODULE FSUB2B
+ INSTANCE wcnt_0
+ SUBMODULE FADD2B
+ INSTANCE precin_inst237
+ SUBMODULE CU2
+ INSTANCE r_ctr_3
+ SUBMODULE CU2
+ INSTANCE r_ctr_2
+ SUBMODULE CU2
+ INSTANCE r_ctr_1
+ SUBMODULE CU2
+ INSTANCE r_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE r_ctr_cia
+ SUBMODULE VHI
+ INSTANCE scuba_vhi_inst
+ SUBMODULE CU2
+ INSTANCE w_ctr_3
+ SUBMODULE CU2
+ INSTANCE w_ctr_2
+ SUBMODULE CU2
+ INSTANCE w_ctr_1
+ SUBMODULE CU2
+ INSTANCE w_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE w_ctr_cia
+ SUBMODULE FADD2B
+ INSTANCE a1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_3
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE g_cmp_ci_a
+ SUBMODULE FADD2B
+ INSTANCE a0
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_3
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_2
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_1
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE e_cmp_ci_a
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_3
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_2
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_1
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_0
+ SUBMODULE FADD2B
+ INSTANCE bdcnt_bctr_cia
+ SUBMODULE FD1S3DX
+ INSTANCE FF_0
+ SUBMODULE FD1S3DX
+ INSTANCE FF_1
+ SUBMODULE FD1S3DX
+ INSTANCE FF_2
+ SUBMODULE FD1S3DX
+ INSTANCE FF_3
+ SUBMODULE FD1S3DX
+ INSTANCE FF_4
+ SUBMODULE FD1S3DX
+ INSTANCE FF_5
+ SUBMODULE FD1S3DX
+ INSTANCE FF_6
+ SUBMODULE FD1S3DX
+ INSTANCE FF_7
+ SUBMODULE FD1S3DX
+ INSTANCE FF_8
+ SUBMODULE FD1P3DX
+ INSTANCE FF_9
+ SUBMODULE FD1P3DX
+ INSTANCE FF_10
+ SUBMODULE FD1P3DX
+ INSTANCE FF_11
+ SUBMODULE FD1P3DX
+ INSTANCE FF_12
+ SUBMODULE FD1P3DX
+ INSTANCE FF_13
+ SUBMODULE FD1P3DX
+ INSTANCE FF_14
+ SUBMODULE FD1P3DX
+ INSTANCE FF_15
+ SUBMODULE FD1P3DX
+ INSTANCE FF_16
+ SUBMODULE FD1P3DX
+ INSTANCE FF_17
+ SUBMODULE FD1P3DX
+ INSTANCE FF_18
+ SUBMODULE FD1P3DX
+ INSTANCE FF_19
+ SUBMODULE FD1P3DX
+ INSTANCE FF_20
+ SUBMODULE FD1P3DX
+ INSTANCE FF_21
+ SUBMODULE FD1P3DX
+ INSTANCE FF_22
+ SUBMODULE FD1P3DX
+ INSTANCE FF_23
+ SUBMODULE FD1P3DX
+ INSTANCE FF_24
+ SUBMODULE FD1P3DX
+ INSTANCE FF_25
+ SUBMODULE FD1P3DX
+ INSTANCE FF_26
+ SUBMODULE FD1P3DX
+ INSTANCE FF_27
+ SUBMODULE FD1P3DX
+ INSTANCE FF_28
+ SUBMODULE FD1P3DX
+ INSTANCE FF_29
+ SUBMODULE FD1P3DX
+ INSTANCE FF_30
+ SUBMODULE FD1P3DX
+ INSTANCE FF_31
+ SUBMODULE FD1P3BX
+ INSTANCE FF_32
+ SUBMODULE FD1P3DX
+ INSTANCE FF_33
+ SUBMODULE FD1P3DX
+ INSTANCE FF_34
+ SUBMODULE FD1P3DX
+ INSTANCE FF_35
+ SUBMODULE FD1P3DX
+ INSTANCE FF_36
+ SUBMODULE FD1P3DX
+ INSTANCE FF_37
+ SUBMODULE FD1P3DX
+ INSTANCE FF_38
+ SUBMODULE FD1P3DX
+ INSTANCE FF_39
+ SUBMODULE FD1P3BX
+ INSTANCE FF_40
+ SUBMODULE FD1S3DX
+ INSTANCE FF_41
+ SUBMODULE FD1S3BX
+ INSTANCE FF_42
+ SUBMODULE FD1P3DX
+ INSTANCE FF_43
+ SUBMODULE FD1P3DX
+ INSTANCE FF_44
+ SUBMODULE FD1P3DX
+ INSTANCE FF_45
+ SUBMODULE FD1P3DX
+ INSTANCE FF_46
+ SUBMODULE FD1P3DX
+ INSTANCE FF_47
+ SUBMODULE FD1P3DX
+ INSTANCE FF_48
+ SUBMODULE FD1P3DX
+ INSTANCE FF_49
+ SUBMODULE FD1P3DX
+ INSTANCE FF_50
+ SUBMODULE PDPW16KC
+ INSTANCE pdp_ram_0_0_0
+ SUBMODULE INV
+ INSTANCE INV_0
+ SUBMODULE XOR2
+ INSTANCE XOR2_t0
+ SUBMODULE INV
+ INSTANCE INV_1
+ SUBMODULE AND2
+ INSTANCE AND2_t1
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_1
+ SUBMODULE INV
+ INSTANCE INV_2
+ SUBMODULE INV
+ INSTANCE INV_3
+ SUBMODULE XOR2
+ INSTANCE XOR2_t2
+ SUBMODULE AND2
+ INSTANCE AND2_t3
+ SUBMODULE INV
+ INSTANCE INV_4
+ SUBMODULE AND2
+ INSTANCE AND2_t4
+ SUBMODULE INV
+ INSTANCE INV_5
+ SUBMODULE AND2
+ INSTANCE AND2_t5
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=FIFO_36x128_DynThr_OutReg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/10/2015
+Time=11:04:27
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=128
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n FIFO_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 0
--- /dev/null
+Data[35] i
+Data[34] i
+Data[33] i
+Data[32] i
+Data[31] i
+Data[30] i
+Data[29] i
+Data[28] i
+Data[27] i
+Data[26] i
+Data[25] i
+Data[24] i
+Data[23] i
+Data[22] i
+Data[21] i
+Data[20] i
+Data[19] i
+Data[18] i
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+Clock i
+WrEn i
+RdEn i
+Reset i
+AmFullThresh[6] i
+AmFullThresh[5] i
+AmFullThresh[4] i
+AmFullThresh[3] i
+AmFullThresh[2] i
+AmFullThresh[1] i
+AmFullThresh[0] i
+Q[35] o
+Q[34] o
+Q[33] o
+Q[32] o
+Q[31] o
+Q[30] o
+Q[29] o
+Q[28] o
+Q[27] o
+Q[26] o
+Q[25] o
+Q[24] o
+Q[23] o
+Q[22] o
+Q[21] o
+Q[20] o
+Q[19] o
+Q[18] o
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostFull o
--- /dev/null
+FIFO_36x128_DynThr_OutReg.vhd
--- /dev/null
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 11:04:28 2015
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 0
+ Circuit name : FIFO_36x128_DynThr_OutReg
+ Module type : fifoblk
+ Module Version : 5.1
+ Ports :
+ Inputs : Data[35:0], Clock, WrEn, RdEn, Reset, AmFullThresh[6:0]
+ Outputs : Q[35:0], Empty, Full, AlmostFull
+ I/O buffer : not inserted
+ EDIF output : FIFO_36x128_DynThr_OutReg.edn
+ VHDL output : FIFO_36x128_DynThr_OutReg.vhd
+ VHDL template : FIFO_36x128_DynThr_OutReg_tmpl.vhd
+ VHDL testbench : tb_FIFO_36x128_DynThr_OutReg_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : FIFO_36x128_DynThr_OutReg.srp
+ Element Usage :
+ AGEB2 : 8
+ ALEB2 : 4
+ AND2 : 4
+ CU2 : 8
+ CB2 : 4
+ FADD2B : 10
+ FSUB2B : 5
+ FD1P3BX : 2
+ FD1P3DX : 38
+ FD1S3BX : 1
+ FD1S3DX : 10
+ INV : 6
+ ROM16X1A : 2
+ XOR2 : 2
+ PDPW16KC : 1
+ Estimated Resource Usage:
+ LUT : 86
+ EBR : 1
+ Reg : 51
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+--/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf 0
+
+-- Thu Sep 10 11:04:28 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity FIFO_36x128_DynThr_OutReg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end FIFO_36x128_DynThr_OutReg;
+
+architecture Structure of FIFO_36x128_DynThr_OutReg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal rptr_7: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co3: std_logic;
+ signal co2: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co3_1: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_7: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co3_2: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal precin: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal rptr_0: std_logic;
+ signal cnt_con: std_logic;
+ signal wcount_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal wcount_1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal wcount_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal wcount_5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_DynThr_OutReg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_5: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_4: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_3: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_2: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_7, B=>rptr_7, Z=>wcnt_sub_msb);
+
+ INV_0: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ pdp_ram_0_0_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
+ ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
+ ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
+ ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
+ ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
+ DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
+ DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
+ DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
+ DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
+ DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
+ DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
+ DO35=>Q(17));
+
+ FF_50: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_49: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_48: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_47: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_46: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_45: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_44: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_43: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_42: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_41: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_40: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_39: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_38: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_37: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_36: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_35: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_34: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_33: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_32: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_31: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_30: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_29: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_28: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_27: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_26: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_25: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_24: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_23: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_22: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_21: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_20: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_19: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_18: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_17: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_16: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_15: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_14: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_13: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_12: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_11: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_10: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_9: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_8: FD1S3DX
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_7: FD1S3DX
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_6: FD1S3DX
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_5: FD1S3DX
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_4: FD1S3DX
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_3: FD1S3DX
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_2: FD1S3DX
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_1: FD1S3DX
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co2_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_1,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_2,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ precin_inst237: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open,
+ S1=>open);
+
+ wcnt_0: FSUB2B
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ BI=>precin, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
+
+ wcnt_1: FSUB2B
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
+
+ wcnt_2: FSUB2B
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
+
+ wcnt_3: FSUB2B
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ BI=>co2_5, BOUT=>co3_3, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
+
+ wcnt_4: FSUB2B
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co3_3, BOUT=>open, S0=>wcnt_sub_7,
+ S1=>open);
+
+ af_set_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+ af_set_cmp_0: AGEB2
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>scuba_vlo, CI=>co2_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of FIFO_36x128_DynThr_OutReg is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:CB2 use entity ecp3.CB2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: module
+
+Starting process:
+
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 11:04:28 2015
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 0
+ Circuit name : FIFO_36x128_DynThr_OutReg
+ Module type : fifoblk
+ Module Version : 5.1
+ Ports :
+ Inputs : Data[35:0], Clock, WrEn, RdEn, Reset, AmFullThresh[6:0]
+ Outputs : Q[35:0], Empty, Full, AlmostFull
+ I/O buffer : not inserted
+ EDIF output : FIFO_36x128_DynThr_OutReg.edn
+ VHDL output : FIFO_36x128_DynThr_OutReg.vhd
+ VHDL template : FIFO_36x128_DynThr_OutReg_tmpl.vhd
+ VHDL testbench : tb_FIFO_36x128_DynThr_OutReg_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : FIFO_36x128_DynThr_OutReg.srp
+ Estimated Resource Usage:
+ LUT : 86
+ EBR : 1
+ Reg : 51
+
+END SCUBA Module Synthesis
+
+File: FIFO_36x128_DynThr_OutReg.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings: 0
+
+Total Errors: 0
+
+
--- /dev/null
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+-- Thu Sep 10 11:04:28 2015
+
+-- parameterized module component declaration
+component FIFO_36x128_DynThr_OutReg
+ port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(35 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostFull: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : FIFO_36x128_DynThr_OutReg
+ port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, AmFullThresh(6 downto 0)=>__, Q(35 downto 0)=>__,
+ Empty=>__, Full=>__, AlmostFull=>__);
(keywordMap (keywordLevel 0))
(status
(written
- (timestamp 2015 4 13 14 41 29)
- (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
- (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf -1 ")
+ (timestamp 2015 9 10 16 31 43)
+ (program "SCUBA" (version "Diamond (64-bit) 3.5.0.102"))))
+ (comment "/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf 120 ")
(library ORCLIB
(edifLevel 0)
(technology
(port Empty
(direction OUTPUT))
(port Full
+ (direction OUTPUT))
+ (port AlmostFull
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
- (instance AND2_t3
+ (instance AND2_t4
(viewRef view1
(cellRef AND2)))
- (instance INV_3
+ (instance INV_8
(viewRef view1
(cellRef INV)))
- (instance AND2_t2
+ (instance AND2_t3
(viewRef view1
(cellRef AND2)))
- (instance INV_2
+ (instance INV_7
(viewRef view1
(cellRef INV)))
- (instance AND2_t1
+ (instance AND2_t2
(viewRef view1
(cellRef AND2)))
- (instance XOR2_t0
+ (instance XOR2_t1
(viewRef view1
(cellRef XOR2)))
- (instance INV_1
+ (instance INV_6
(viewRef view1
(cellRef INV)))
- (instance INV_0
+ (instance INV_5
(viewRef view1
(cellRef INV)))
(instance LUT4_1
(cellRef ROM16X1A))
(property initval
(string "0x3232")))
+ (instance AND2_t0
+ (viewRef view1
+ (cellRef AND2)))
+ (instance INV_4
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_3
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_2
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_1
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_0
+ (viewRef view1
+ (cellRef INV)))
(instance pdp_ram_0_0_0
(viewRef view1
(cellRef PDPW16KC))
(string "36"))
(property DATA_WIDTH_W
(string "36")))
+ (instance FF_26
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
(instance FF_25
(viewRef view1
(cellRef FD1P3DX))
(string "ENABLED")))
(instance FF_18
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3BX))
(property GSR
(string "ENABLED")))
(instance FF_17
(viewRef view1
- (cellRef FD1S3BX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance FF_16
(viewRef view1
- (cellRef FD1S3DX))
+ (cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_15
(string "ENABLED")))
(instance FF_0
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance bdcnt_bctr_cia
(instance w_ctr_3
(viewRef view1
(cellRef CU2)))
- (instance scuba_vlo_inst
- (viewRef view1
- (cellRef VLO)))
- (instance scuba_vhi_inst
- (viewRef view1
- (cellRef VHI)))
(instance r_ctr_cia
(viewRef view1
(cellRef FADD2B)))
(instance r_ctr_3
(viewRef view1
(cellRef CU2)))
+ (instance af_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance af_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_cmp_2
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vhi_inst
+ (viewRef view1
+ (cellRef VHI)))
+ (instance af_cmp_3
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vlo_inst
+ (viewRef view1
+ (cellRef VLO)))
+ (instance a2
+ (viewRef view1
+ (cellRef FADD2B)))
+ (net invout_2
+ (joined
+ (portRef Z (instanceRef INV_8))
+ (portRef B (instanceRef AND2_t4))))
(net invout_1
(joined
- (portRef Z (instanceRef INV_3))
+ (portRef Z (instanceRef INV_7))
(portRef B (instanceRef AND2_t3))))
- (net invout_0
+ (net rden_i_inv
(joined
- (portRef Z (instanceRef INV_2))
+ (portRef Z (instanceRef INV_6))
(portRef B (instanceRef AND2_t2))))
- (net rden_i_inv
+ (net invout_0
(joined
- (portRef Z (instanceRef INV_1))
- (portRef B (instanceRef AND2_t1))))
+ (portRef Z (instanceRef INV_4))
+ (portRef B (instanceRef AND2_t0))))
+ (net r_nw_inv
+ (joined
+ (portRef Z (instanceRef INV_1))))
+ (net r_nw
+ (joined
+ (portRef A (instanceRef INV_1))
+ (portRef Z (instanceRef AND2_t0))))
+ (net fcnt_en_inv
+ (joined
+ (portRef A (instanceRef INV_0))
+ (portRef Z (instanceRef INV_3))))
(net fcnt_en
(joined
- (portRef SP (instanceRef FF_18))
- (portRef Z (instanceRef XOR2_t0))
+ (portRef SP (instanceRef FF_19))
+ (portRef Z (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_3))
+ (portRef SP (instanceRef FF_26))
(portRef SP (instanceRef FF_25))
(portRef SP (instanceRef FF_24))
(portRef SP (instanceRef FF_23))
(portRef SP (instanceRef FF_22))
(portRef SP (instanceRef FF_21))
- (portRef SP (instanceRef FF_20))
- (portRef SP (instanceRef FF_19))))
+ (portRef SP (instanceRef FF_20))))
(net empty_d
(joined
- (portRef D (instanceRef FF_17))
+ (portRef D (instanceRef FF_18))
(portRef DO0 (instanceRef LUT4_1))))
(net full_d
(joined
- (portRef D (instanceRef FF_16))
+ (portRef D (instanceRef FF_17))
(portRef DO0 (instanceRef LUT4_0))))
(net ifcount_0
(joined
(portRef NC0 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_25))))
+ (portRef D (instanceRef FF_26))))
(net ifcount_1
(joined
(portRef NC1 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_24))))
+ (portRef D (instanceRef FF_25))))
(net bdcnt_bctr_ci
(joined
(portRef CI (instanceRef bdcnt_bctr_0))
(net ifcount_2
(joined
(portRef NC0 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_23))))
+ (portRef D (instanceRef FF_24))))
(net ifcount_3
(joined
(portRef NC1 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_22))))
+ (portRef D (instanceRef FF_23))))
(net co0
(joined
(portRef CI (instanceRef bdcnt_bctr_1))
(net ifcount_4
(joined
(portRef NC0 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_21))))
+ (portRef D (instanceRef FF_22))))
(net ifcount_5
(joined
(portRef NC1 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_20))))
+ (portRef D (instanceRef FF_21))))
(net co1
(joined
(portRef CI (instanceRef bdcnt_bctr_2))
(net ifcount_6
(joined
(portRef NC0 (instanceRef bdcnt_bctr_3))
- (portRef D (instanceRef FF_19))))
+ (portRef D (instanceRef FF_20))))
(net ifcount_7
(joined
(portRef NC1 (instanceRef bdcnt_bctr_3))
- (portRef D (instanceRef FF_18))))
+ (portRef D (instanceRef FF_19))))
(net co3
(joined
(portRef CO (instanceRef bdcnt_bctr_3))))
- (net cnt_con
- (joined
- (portRef CON (instanceRef bdcnt_bctr_3))
- (portRef Z (instanceRef AND2_t1))
- (portRef B1 (instanceRef bdcnt_bctr_cia))
- (portRef A1 (instanceRef bdcnt_bctr_cia))
- (portRef CON (instanceRef bdcnt_bctr_0))
- (portRef CON (instanceRef bdcnt_bctr_1))
- (portRef CON (instanceRef bdcnt_bctr_2))))
(net co2
(joined
(portRef CI (instanceRef bdcnt_bctr_3))
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(net Full
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+ (portRef Q (instanceRef FF_18))
+ (portRef A (instanceRef INV_7))
(portRef AD0 (instanceRef LUT4_1))))
(net dataout35
(joined
(joined
(portRef Reset)
(portRef RST (instanceRef pdp_ram_0_0_0))
+ (portRef CD (instanceRef FF_26))
(portRef CD (instanceRef FF_25))
(portRef CD (instanceRef FF_24))
(portRef CD (instanceRef FF_23))
(portRef CD (instanceRef FF_21))
(portRef CD (instanceRef FF_20))
(portRef CD (instanceRef FF_19))
- (portRef CD (instanceRef FF_18))
- (portRef PD (instanceRef FF_17))
+ (portRef PD (instanceRef FF_18))
+ (portRef CD (instanceRef FF_17))
(portRef CD (instanceRef FF_16))
(portRef CD (instanceRef FF_15))
(portRef CD (instanceRef FF_14))
(net rden
(joined
(portRef RdEn)
- (portRef A (instanceRef AND2_t2))))
+ (portRef A (instanceRef AND2_t3))))
(net wren
(joined
(portRef WrEn)
- (portRef A (instanceRef AND2_t3))))
+ (portRef A (instanceRef AND2_t4))))
(net clk
(joined
(portRef Clock)
(portRef CLKR (instanceRef pdp_ram_0_0_0))
(portRef CLKW (instanceRef pdp_ram_0_0_0))
+ (portRef CK (instanceRef FF_26))
(portRef CK (instanceRef FF_25))
(portRef CK (instanceRef FF_24))
(portRef CK (instanceRef FF_23))
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="FIFO_36x128_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 04 13 14:41:31.037" version="5.0" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="FIFO_36x128_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 09 10 16:31:45.003" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="FIFO_36x128_OutReg.lpc" type="lpc" modified="2015 04 13 14:41:29.000"/>
- <File name="FIFO_36x128_OutReg.vhd" type="top_level_vhdl" modified="2015 04 13 14:41:29.000"/>
- <File name="FIFO_36x128_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 04 13 14:41:29.000"/>
- <File name="tb_FIFO_36x128_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 04 13 14:41:29.000"/>
+ <File name="FIFO_36x128_OutReg.lpc" type="lpc" modified="2015 09 10 16:31:43.000"/>
+ <File name="FIFO_36x128_OutReg.vhd" type="top_level_vhdl" modified="2015 09 10 16:31:43.000"/>
+ <File name="FIFO_36x128_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 09 10 16:31:43.000"/>
+ <File name="tb_FIFO_36x128_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 09 10 16:31:43.000"/>
</Package>
</DiamondModule>
+MODULE FIFO_36x128_OutReg DEFIN FIFO_36x128_OutReg.vhd
+ SUBMODULE FADD2B
+ INSTANCE a2
+ SUBMODULE VLO
+ INSTANCE scuba_vlo_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_3
+ SUBMODULE VHI
+ INSTANCE scuba_vhi_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE af_cmp_ci_a
+ SUBMODULE CU2
+ INSTANCE r_ctr_3
+ SUBMODULE CU2
+ INSTANCE r_ctr_2
+ SUBMODULE CU2
+ INSTANCE r_ctr_1
+ SUBMODULE CU2
+ INSTANCE r_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE r_ctr_cia
+ SUBMODULE CU2
+ INSTANCE w_ctr_3
+ SUBMODULE CU2
+ INSTANCE w_ctr_2
+ SUBMODULE CU2
+ INSTANCE w_ctr_1
+ SUBMODULE CU2
+ INSTANCE w_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE w_ctr_cia
+ SUBMODULE FADD2B
+ INSTANCE a1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_3
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE g_cmp_ci_a
+ SUBMODULE FADD2B
+ INSTANCE a0
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_3
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_2
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_1
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE e_cmp_ci_a
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_3
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_2
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_1
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_0
+ SUBMODULE FADD2B
+ INSTANCE bdcnt_bctr_cia
+ SUBMODULE FD1S3DX
+ INSTANCE FF_0
+ SUBMODULE FD1P3DX
+ INSTANCE FF_1
+ SUBMODULE FD1P3DX
+ INSTANCE FF_2
+ SUBMODULE FD1P3DX
+ INSTANCE FF_3
+ SUBMODULE FD1P3DX
+ INSTANCE FF_4
+ SUBMODULE FD1P3DX
+ INSTANCE FF_5
+ SUBMODULE FD1P3DX
+ INSTANCE FF_6
+ SUBMODULE FD1P3DX
+ INSTANCE FF_7
+ SUBMODULE FD1P3DX
+ INSTANCE FF_8
+ SUBMODULE FD1P3DX
+ INSTANCE FF_9
+ SUBMODULE FD1P3DX
+ INSTANCE FF_10
+ SUBMODULE FD1P3DX
+ INSTANCE FF_11
+ SUBMODULE FD1P3DX
+ INSTANCE FF_12
+ SUBMODULE FD1P3DX
+ INSTANCE FF_13
+ SUBMODULE FD1P3DX
+ INSTANCE FF_14
+ SUBMODULE FD1P3DX
+ INSTANCE FF_15
+ SUBMODULE FD1P3DX
+ INSTANCE FF_16
+ SUBMODULE FD1S3DX
+ INSTANCE FF_17
+ SUBMODULE FD1S3BX
+ INSTANCE FF_18
+ SUBMODULE FD1P3DX
+ INSTANCE FF_19
+ SUBMODULE FD1P3DX
+ INSTANCE FF_20
+ SUBMODULE FD1P3DX
+ INSTANCE FF_21
+ SUBMODULE FD1P3DX
+ INSTANCE FF_22
+ SUBMODULE FD1P3DX
+ INSTANCE FF_23
+ SUBMODULE FD1P3DX
+ INSTANCE FF_24
+ SUBMODULE FD1P3DX
+ INSTANCE FF_25
+ SUBMODULE FD1P3DX
+ INSTANCE FF_26
+ SUBMODULE PDPW16KC
+ INSTANCE pdp_ram_0_0_0
+ SUBMODULE INV
+ INSTANCE INV_0
+ SUBMODULE INV
+ INSTANCE INV_1
+ SUBMODULE INV
+ INSTANCE INV_2
+ SUBMODULE INV
+ INSTANCE INV_3
+ SUBMODULE INV
+ INSTANCE INV_4
+ SUBMODULE AND2
+ INSTANCE AND2_t0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_1
+ SUBMODULE INV
+ INSTANCE INV_5
+ SUBMODULE INV
+ INSTANCE INV_6
+ SUBMODULE XOR2
+ INSTANCE XOR2_t1
+ SUBMODULE AND2
+ INSTANCE AND2_t2
+ SUBMODULE INV
+ INSTANCE INV_7
+ SUBMODULE AND2
+ INSTANCE AND2_t3
+ SUBMODULE INV
+ INSTANCE INV_8
+ SUBMODULE AND2
+ INSTANCE AND2_t4
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
-CoreRevision=5.0
+CoreRevision=5.1
ModuleName=FIFO_36x128_OutReg
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/13/2015
-Time=14:41:29
+Date=09/10/2015
+Time=16:31:43
[Parameters]
Verilog=0
PeMode=Static - Dual Threshold
PeAssert=10
PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=120
PfDeassert=506
RDataCount=0
EnECC=0
EnFWFT=0
[Command]
-cmd_line= -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf -1
+cmd_line= -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 120
--- /dev/null
+Data[35] i
+Data[34] i
+Data[33] i
+Data[32] i
+Data[31] i
+Data[30] i
+Data[29] i
+Data[28] i
+Data[27] i
+Data[26] i
+Data[25] i
+Data[24] i
+Data[23] i
+Data[22] i
+Data[21] i
+Data[20] i
+Data[19] i
+Data[18] i
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+Clock i
+WrEn i
+RdEn i
+Reset i
+Q[35] o
+Q[34] o
+Q[33] o
+Q[32] o
+Q[31] o
+Q[30] o
+Q[29] o
+Q[28] o
+Q[27] o
+Q[26] o
+Q[25] o
+Q[24] o
+Q[23] o
+Q[22] o
+Q[21] o
+Q[20] o
+Q[19] o
+Q[18] o
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostFull o
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Mon Apr 13 14:41:29 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:31:43 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 120
Circuit name : FIFO_36x128_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x128_OutReg.edn
VHDL output : FIFO_36x128_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x128_OutReg.srp
Element Usage :
- AGEB2 : 4
+ AGEB2 : 8
ALEB2 : 4
- AND2 : 3
+ AND2 : 4
CU2 : 8
CB2 : 4
- FADD2B : 7
+ FADD2B : 9
FD1P3DX : 24
FD1S3BX : 1
- FD1S3DX : 1
- INV : 4
+ FD1S3DX : 2
+ INV : 9
ROM16X1A : 2
XOR2 : 1
PDPW16KC : 1
Estimated Resource Usage:
- LUT : 60
+ LUT : 73
EBR : 1
- Reg : 26
+ Reg : 27
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf -1
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+--/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -regout -no_enable -pe -1 -pf 120
--- Mon Apr 13 14:41:29 2015
+-- Thu Sep 10 16:31:43 2015
library IEEE;
use IEEE.std_logic_1164.all;
Reset: in std_logic;
Q: out std_logic_vector(35 downto 0);
Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic;
+ AlmostFull: out std_logic);
end FIFO_36x128_OutReg;
architecture Structure of FIFO_36x128_OutReg is
-- internal signal declarations
+ signal invout_2: std_logic;
signal invout_1: std_logic;
- signal invout_0: std_logic;
signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal ifcount_6: std_logic;
signal ifcount_7: std_logic;
signal co3: std_logic;
- signal cnt_con: std_logic;
signal co2: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
signal co1_2: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
signal co2_2: std_logic;
signal wren_i: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal co2_3: std_logic;
signal wcount_6: std_logic;
signal wcount_7: std_logic;
- signal scuba_vlo: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_ctr_ci: std_logic;
signal co2_4: std_logic;
signal rcount_6: std_logic;
signal rcount_7: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
-- local component declarations
component AGEB2
attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128_OutReg.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_26 : label is "ENABLED";
attribute GSR of FF_25 : label is "ENABLED";
attribute GSR of FF_24 : label is "ENABLED";
attribute GSR of FF_23 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t3: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_3: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
- AND2_t2: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_2: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
- AND2_t1: AND2
+ AND2_t2: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t0: XOR2
+ XOR2_t1: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_1: INV
+ INV_6: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_0: INV
+ INV_5: INV
port map (A=>wren_i, Z=>wren_i_inv);
LUT4_1: ROM16X1A
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
pdp_ram_0_0_0: PDPW16KC
generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
- FF_25: FD1P3DX
+ FF_26: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_24: FD1P3DX
+ FF_25: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_23: FD1P3DX
+ FF_24: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_22: FD1P3DX
+ FF_23: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_21: FD1P3DX
+ FF_22: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_20: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_19: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_18: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
- FF_17: FD1S3BX
+ FF_18: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_16: FD1S3DX
+ FF_17: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_15: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_14: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_13: FD1P3DX
+ FF_14: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_12: FD1P3DX
+ FF_13: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_11: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_10: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_9: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_8: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
- FF_7: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_6: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_5: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_4: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_3: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_2: FD1P3DX
+ FF_3: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_1: FD1P3DX
+ FF_2: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
- FF_0: FD1P3DX
+ FF_1: FD1P3DX
port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
+ FF_0: FD1S3DX
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_1,
NC0=>iwcount_6, NC1=>iwcount_7);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_ctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_2,
NC0=>ircount_6, NC1=>ircount_7);
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con,
+ B1=>cnt_con_inv, CI=>co0_5, GE=>co1_5);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_5, GE=>co2_5);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vlo, CI=>co2_5, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
Empty <= empty_i;
Full <= full_i;
end Structure;
Starting process:
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Mon Apr 13 14:41:29 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:31:43 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -outdata REGISTERED -no_enable -pe -1 -pf 120
Circuit name : FIFO_36x128_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x128_OutReg.edn
VHDL output : FIFO_36x128_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x128_OutReg.srp
Estimated Resource Usage:
- LUT : 60
+ LUT : 73
EBR : 1
- Reg : 26
+ Reg : 27
END SCUBA Module Synthesis
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
--- Mon Apr 13 14:41:29 2015
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+-- Thu Sep 10 16:31:43 2015
-- parameterized module component declaration
component FIFO_36x128_OutReg
port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic;
WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
Q: out std_logic_vector(35 downto 0); Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic; AlmostFull: out std_logic);
end component;
-- parameterized module component instance
__ : FIFO_36x128_OutReg
port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__);
+ Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostFull=>__);
(keywordMap (keywordLevel 0))
(status
(written
- (timestamp 2015 4 17 11 33 22)
- (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
- (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf -1 ")
+ (timestamp 2015 9 10 16 33 18)
+ (program "SCUBA" (version "Diamond (64-bit) 3.5.0.102"))))
+ (comment "/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf 24 ")
(library ORCLIB
(edifLevel 0)
(technology
(port Empty
(direction OUTPUT))
(port Full
+ (direction OUTPUT))
+ (port AlmostFull
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
- (instance AND2_t3
+ (instance AND2_t4
(viewRef view1
(cellRef AND2)))
- (instance INV_3
+ (instance INV_8
(viewRef view1
(cellRef INV)))
- (instance AND2_t2
+ (instance AND2_t3
(viewRef view1
(cellRef AND2)))
- (instance INV_2
+ (instance INV_7
(viewRef view1
(cellRef INV)))
- (instance AND2_t1
+ (instance AND2_t2
(viewRef view1
(cellRef AND2)))
- (instance XOR2_t0
+ (instance XOR2_t1
(viewRef view1
(cellRef XOR2)))
- (instance INV_1
+ (instance INV_6
(viewRef view1
(cellRef INV)))
- (instance INV_0
+ (instance INV_5
(viewRef view1
(cellRef INV)))
(instance LUT4_1
(cellRef ROM16X1A))
(property initval
(string "0x3232")))
+ (instance AND2_t0
+ (viewRef view1
+ (cellRef AND2)))
+ (instance INV_4
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_3
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_2
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_1
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_0
+ (viewRef view1
+ (cellRef INV)))
(instance pdp_ram_0_0_0
(viewRef view1
(cellRef PDPW16KC))
(string "36"))
(property DATA_WIDTH_W
(string "36")))
+ (instance FF_20
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
(instance FF_19
(viewRef view1
(cellRef FD1P3DX))
(string "ENABLED")))
(instance FF_14
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3BX))
(property GSR
(string "ENABLED")))
(instance FF_13
(viewRef view1
- (cellRef FD1S3BX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance FF_12
(viewRef view1
- (cellRef FD1S3DX))
+ (cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_11
(string "ENABLED")))
(instance FF_0
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance bdcnt_bctr_cia
(instance w_ctr_2
(viewRef view1
(cellRef CU2)))
- (instance scuba_vlo_inst
- (viewRef view1
- (cellRef VLO)))
- (instance scuba_vhi_inst
- (viewRef view1
- (cellRef VHI)))
(instance r_ctr_cia
(viewRef view1
(cellRef FADD2B)))
(instance r_ctr_2
(viewRef view1
(cellRef CU2)))
+ (instance af_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance af_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vhi_inst
+ (viewRef view1
+ (cellRef VHI)))
+ (instance af_cmp_2
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vlo_inst
+ (viewRef view1
+ (cellRef VLO)))
+ (instance a2
+ (viewRef view1
+ (cellRef FADD2B)))
+ (net invout_2
+ (joined
+ (portRef Z (instanceRef INV_8))
+ (portRef B (instanceRef AND2_t4))))
(net invout_1
(joined
- (portRef Z (instanceRef INV_3))
+ (portRef Z (instanceRef INV_7))
(portRef B (instanceRef AND2_t3))))
- (net invout_0
+ (net rden_i_inv
(joined
- (portRef Z (instanceRef INV_2))
+ (portRef Z (instanceRef INV_6))
(portRef B (instanceRef AND2_t2))))
- (net rden_i_inv
+ (net invout_0
+ (joined
+ (portRef Z (instanceRef INV_4))
+ (portRef B (instanceRef AND2_t0))))
+ (net r_nw_inv
(joined
- (portRef Z (instanceRef INV_1))
- (portRef B (instanceRef AND2_t1))))
+ (portRef Z (instanceRef INV_1))))
+ (net r_nw
+ (joined
+ (portRef A (instanceRef INV_1))
+ (portRef Z (instanceRef AND2_t0))))
+ (net fcnt_en_inv
+ (joined
+ (portRef A (instanceRef INV_0))
+ (portRef Z (instanceRef INV_3))))
(net fcnt_en
(joined
- (portRef SP (instanceRef FF_14))
- (portRef Z (instanceRef XOR2_t0))
+ (portRef SP (instanceRef FF_15))
+ (portRef Z (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_3))
+ (portRef SP (instanceRef FF_20))
(portRef SP (instanceRef FF_19))
(portRef SP (instanceRef FF_18))
(portRef SP (instanceRef FF_17))
- (portRef SP (instanceRef FF_16))
- (portRef SP (instanceRef FF_15))))
+ (portRef SP (instanceRef FF_16))))
(net empty_d
(joined
- (portRef D (instanceRef FF_13))
+ (portRef D (instanceRef FF_14))
(portRef DO0 (instanceRef LUT4_1))))
(net full_d
(joined
- (portRef D (instanceRef FF_12))
+ (portRef D (instanceRef FF_13))
(portRef DO0 (instanceRef LUT4_0))))
(net ifcount_0
(joined
(portRef NC0 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_19))))
+ (portRef D (instanceRef FF_20))))
(net ifcount_1
(joined
(portRef NC1 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_18))))
+ (portRef D (instanceRef FF_19))))
(net bdcnt_bctr_ci
(joined
(portRef CI (instanceRef bdcnt_bctr_0))
(net ifcount_2
(joined
(portRef NC0 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_17))))
+ (portRef D (instanceRef FF_18))))
(net ifcount_3
(joined
(portRef NC1 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_16))))
+ (portRef D (instanceRef FF_17))))
(net co0
(joined
(portRef CI (instanceRef bdcnt_bctr_1))
(net ifcount_4
(joined
(portRef NC0 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_15))))
+ (portRef D (instanceRef FF_16))))
(net ifcount_5
(joined
(portRef NC1 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_14))))
+ (portRef D (instanceRef FF_15))))
(net co2
(joined
(portRef CO (instanceRef bdcnt_bctr_2))))
- (net cnt_con
- (joined
- (portRef CON (instanceRef bdcnt_bctr_2))
- (portRef Z (instanceRef AND2_t1))
- (portRef B1 (instanceRef bdcnt_bctr_cia))
- (portRef A1 (instanceRef bdcnt_bctr_cia))
- (portRef CON (instanceRef bdcnt_bctr_0))
- (portRef CON (instanceRef bdcnt_bctr_1))))
(net co1
(joined
(portRef CI (instanceRef bdcnt_bctr_2))
(net rden_i
(joined
(portRef B0 (instanceRef e_cmp_0))
- (portRef Z (instanceRef AND2_t2))
- (portRef B (instanceRef XOR2_t0))
- (portRef A (instanceRef INV_1))
+ (portRef Z (instanceRef AND2_t3))
+ (portRef B (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_6))
(portRef AD1 (instanceRef LUT4_0))
+ (portRef A (instanceRef AND2_t0))
(portRef CSR0 (instanceRef pdp_ram_0_0_0))
+ (portRef SP (instanceRef FF_6))
(portRef SP (instanceRef FF_5))
(portRef SP (instanceRef FF_4))
(portRef SP (instanceRef FF_3))
(portRef SP (instanceRef FF_2))
- (portRef SP (instanceRef FF_1))
- (portRef SP (instanceRef FF_0))))
+ (portRef SP (instanceRef FF_1))))
(net co0_1
(joined
(portRef CI (instanceRef e_cmp_1))
(joined
(portRef CI (instanceRef g_cmp_0))
(portRef COUT (instanceRef g_cmp_ci_a))))
- (net fcount_0
- (joined
- (portRef A0 (instanceRef g_cmp_0))
- (portRef Q (instanceRef FF_19))
- (portRef PC0 (instanceRef bdcnt_bctr_0))
- (portRef A0 (instanceRef e_cmp_0))))
- (net fcount_1
- (joined
- (portRef A1 (instanceRef g_cmp_0))
- (portRef Q (instanceRef FF_18))
- (portRef PC1 (instanceRef bdcnt_bctr_0))
- (portRef A1 (instanceRef e_cmp_0))))
(net co0_2
(joined
(portRef CI (instanceRef g_cmp_1))
(portRef GE (instanceRef g_cmp_0))))
- (net fcount_2
- (joined
- (portRef A0 (instanceRef g_cmp_1))
- (portRef Q (instanceRef FF_17))
- (portRef PC0 (instanceRef bdcnt_bctr_1))
- (portRef A0 (instanceRef e_cmp_1))))
- (net fcount_3
- (joined
- (portRef A1 (instanceRef g_cmp_1))
- (portRef Q (instanceRef FF_16))
- (portRef PC1 (instanceRef bdcnt_bctr_1))
- (portRef A1 (instanceRef e_cmp_1))))
(net co1_2
(joined
(portRef CI (instanceRef g_cmp_2))
(net wren_i
(joined
(portRef B0 (instanceRef g_cmp_2))
- (portRef Z (instanceRef AND2_t3))
- (portRef A (instanceRef AND2_t1))
- (portRef A (instanceRef XOR2_t0))
- (portRef A (instanceRef INV_0))
+ (portRef Z (instanceRef AND2_t4))
+ (portRef A (instanceRef AND2_t2))
+ (portRef A (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_5))
(portRef AD1 (instanceRef LUT4_1))
+ (portRef A (instanceRef INV_4))
(portRef CEW (instanceRef pdp_ram_0_0_0))
+ (portRef SP (instanceRef FF_12))
(portRef SP (instanceRef FF_11))
(portRef SP (instanceRef FF_10))
(portRef SP (instanceRef FF_9))
(portRef SP (instanceRef FF_8))
(portRef SP (instanceRef FF_7))
- (portRef SP (instanceRef FF_6))
(portRef B0 (instanceRef g_cmp_0))
(portRef B1 (instanceRef g_cmp_0))
(portRef B0 (instanceRef g_cmp_1))
(net wren_i_inv
(joined
(portRef B1 (instanceRef g_cmp_2))
- (portRef Z (instanceRef INV_0))))
- (net fcount_4
- (joined
- (portRef A0 (instanceRef g_cmp_2))
- (portRef Q (instanceRef FF_15))
- (portRef PC0 (instanceRef bdcnt_bctr_2))
- (portRef A0 (instanceRef e_cmp_2))))
- (net fcount_5
- (joined
- (portRef A1 (instanceRef g_cmp_2))
- (portRef Q (instanceRef FF_14))
- (portRef PC1 (instanceRef bdcnt_bctr_2))
- (portRef A1 (instanceRef e_cmp_2))))
+ (portRef Z (instanceRef INV_5))))
(net cmp_ge_d1
(joined
(portRef S0 (instanceRef a1))
(net iwcount_0
(joined
(portRef NC0 (instanceRef w_ctr_0))
- (portRef D (instanceRef FF_11))))
+ (portRef D (instanceRef FF_12))))
(net iwcount_1
(joined
(portRef NC1 (instanceRef w_ctr_0))
- (portRef D (instanceRef FF_10))))
+ (portRef D (instanceRef FF_11))))
(net w_ctr_ci
(joined
(portRef CI (instanceRef w_ctr_0))
(joined
(portRef PC0 (instanceRef w_ctr_0))
(portRef ADW0 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_11))))
+ (portRef Q (instanceRef FF_12))))
(net wcount_1
(joined
(portRef PC1 (instanceRef w_ctr_0))
(portRef ADW1 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_10))))
+ (portRef Q (instanceRef FF_11))))
(net iwcount_2
(joined
(portRef NC0 (instanceRef w_ctr_1))
- (portRef D (instanceRef FF_9))))
+ (portRef D (instanceRef FF_10))))
(net iwcount_3
(joined
(portRef NC1 (instanceRef w_ctr_1))
- (portRef D (instanceRef FF_8))))
+ (portRef D (instanceRef FF_9))))
(net co0_3
(joined
(portRef CI (instanceRef w_ctr_1))
(joined
(portRef PC0 (instanceRef w_ctr_1))
(portRef ADW2 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_9))))
+ (portRef Q (instanceRef FF_10))))
(net wcount_3
(joined
(portRef PC1 (instanceRef w_ctr_1))
(portRef ADW3 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_8))))
+ (portRef Q (instanceRef FF_9))))
(net iwcount_4
(joined
(portRef NC0 (instanceRef w_ctr_2))
- (portRef D (instanceRef FF_7))))
+ (portRef D (instanceRef FF_8))))
(net iwcount_5
(joined
(portRef NC1 (instanceRef w_ctr_2))
- (portRef D (instanceRef FF_6))))
+ (portRef D (instanceRef FF_7))))
(net co2_1
(joined
(portRef CO (instanceRef w_ctr_2))))
(joined
(portRef PC0 (instanceRef w_ctr_2))
(portRef ADW4 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_7))))
+ (portRef Q (instanceRef FF_8))))
(net wcount_5
(joined
(portRef PC1 (instanceRef w_ctr_2))
- (portRef Q (instanceRef FF_6))))
- (net scuba_vlo
- (joined
- (portRef Z (instanceRef scuba_vlo_inst))
- (portRef AD3 (instanceRef LUT4_1))
- (portRef AD3 (instanceRef LUT4_0))
- (portRef CSR2 (instanceRef pdp_ram_0_0_0))
- (portRef CSW2 (instanceRef pdp_ram_0_0_0))
- (portRef CSR1 (instanceRef pdp_ram_0_0_0))
- (portRef CSW1 (instanceRef pdp_ram_0_0_0))
- (portRef ADR13 (instanceRef pdp_ram_0_0_0))
- (portRef ADR12 (instanceRef pdp_ram_0_0_0))
- (portRef ADR11 (instanceRef pdp_ram_0_0_0))
- (portRef ADR10 (instanceRef pdp_ram_0_0_0))
- (portRef ADR4 (instanceRef pdp_ram_0_0_0))
- (portRef ADR3 (instanceRef pdp_ram_0_0_0))
- (portRef ADR2 (instanceRef pdp_ram_0_0_0))
- (portRef ADR1 (instanceRef pdp_ram_0_0_0))
- (portRef ADR0 (instanceRef pdp_ram_0_0_0))
- (portRef ADW8 (instanceRef pdp_ram_0_0_0))
- (portRef ADW7 (instanceRef pdp_ram_0_0_0))
- (portRef ADW6 (instanceRef pdp_ram_0_0_0))
- (portRef ADW5 (instanceRef pdp_ram_0_0_0))
- (portRef CI (instanceRef bdcnt_bctr_cia))
- (portRef B0 (instanceRef bdcnt_bctr_cia))
- (portRef A0 (instanceRef bdcnt_bctr_cia))
- (portRef CI (instanceRef e_cmp_ci_a))
- (portRef B1 (instanceRef e_cmp_0))
- (portRef B0 (instanceRef e_cmp_1))
- (portRef B1 (instanceRef e_cmp_1))
- (portRef B0 (instanceRef e_cmp_2))
- (portRef B1 (instanceRef e_cmp_2))
- (portRef B0 (instanceRef a0))
- (portRef B1 (instanceRef a0))
- (portRef A0 (instanceRef a0))
- (portRef A1 (instanceRef a0))
- (portRef CI (instanceRef g_cmp_ci_a))
- (portRef B0 (instanceRef a1))
- (portRef B1 (instanceRef a1))
- (portRef A0 (instanceRef a1))
- (portRef A1 (instanceRef a1))
- (portRef CI (instanceRef w_ctr_cia))
- (portRef B0 (instanceRef w_ctr_cia))
- (portRef A0 (instanceRef w_ctr_cia))
- (portRef CI (instanceRef r_ctr_cia))
- (portRef B0 (instanceRef r_ctr_cia))
- (portRef A0 (instanceRef r_ctr_cia))))
- (net scuba_vhi
- (joined
- (portRef Z (instanceRef scuba_vhi_inst))
- (portRef CSW0 (instanceRef pdp_ram_0_0_0))
- (portRef BE3 (instanceRef pdp_ram_0_0_0))
- (portRef BE2 (instanceRef pdp_ram_0_0_0))
- (portRef BE1 (instanceRef pdp_ram_0_0_0))
- (portRef BE0 (instanceRef pdp_ram_0_0_0))
- (portRef CER (instanceRef pdp_ram_0_0_0))
- (portRef B0 (instanceRef e_cmp_ci_a))
- (portRef B1 (instanceRef e_cmp_ci_a))
- (portRef A0 (instanceRef e_cmp_ci_a))
- (portRef A1 (instanceRef e_cmp_ci_a))
- (portRef B0 (instanceRef g_cmp_ci_a))
- (portRef B1 (instanceRef g_cmp_ci_a))
- (portRef A0 (instanceRef g_cmp_ci_a))
- (portRef A1 (instanceRef g_cmp_ci_a))
- (portRef B1 (instanceRef w_ctr_cia))
- (portRef A1 (instanceRef w_ctr_cia))
- (portRef B1 (instanceRef r_ctr_cia))
- (portRef A1 (instanceRef r_ctr_cia))))
+ (portRef Q (instanceRef FF_7))))
(net ircount_0
(joined
(portRef NC0 (instanceRef r_ctr_0))
- (portRef D (instanceRef FF_5))))
+ (portRef D (instanceRef FF_6))))
(net ircount_1
(joined
(portRef NC1 (instanceRef r_ctr_0))
- (portRef D (instanceRef FF_4))))
+ (portRef D (instanceRef FF_5))))
(net r_ctr_ci
(joined
(portRef CI (instanceRef r_ctr_0))
(joined
(portRef PC0 (instanceRef r_ctr_0))
(portRef ADR5 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_5))))
+ (portRef Q (instanceRef FF_6))))
(net rcount_1
(joined
(portRef PC1 (instanceRef r_ctr_0))
(portRef ADR6 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_4))))
+ (portRef Q (instanceRef FF_5))))
(net ircount_2
(joined
(portRef NC0 (instanceRef r_ctr_1))
- (portRef D (instanceRef FF_3))))
+ (portRef D (instanceRef FF_4))))
(net ircount_3
(joined
(portRef NC1 (instanceRef r_ctr_1))
- (portRef D (instanceRef FF_2))))
+ (portRef D (instanceRef FF_3))))
(net co0_4
(joined
(portRef CI (instanceRef r_ctr_1))
(joined
(portRef PC0 (instanceRef r_ctr_1))
(portRef ADR7 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_3))))
+ (portRef Q (instanceRef FF_4))))
(net rcount_3
(joined
(portRef PC1 (instanceRef r_ctr_1))
(portRef ADR8 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_2))))
+ (portRef Q (instanceRef FF_3))))
(net ircount_4
(joined
(portRef NC0 (instanceRef r_ctr_2))
- (portRef D (instanceRef FF_1))))
+ (portRef D (instanceRef FF_2))))
(net ircount_5
(joined
(portRef NC1 (instanceRef r_ctr_2))
- (portRef D (instanceRef FF_0))))
+ (portRef D (instanceRef FF_1))))
(net co2_2
(joined
(portRef CO (instanceRef r_ctr_2))))
(joined
(portRef PC0 (instanceRef r_ctr_2))
(portRef ADR9 (instanceRef pdp_ram_0_0_0))
- (portRef Q (instanceRef FF_1))))
+ (portRef Q (instanceRef FF_2))))
(net rcount_5
(joined
(portRef PC1 (instanceRef r_ctr_2))
+ (portRef Q (instanceRef FF_1))))
+ (net cmp_ci_2
+ (joined
+ (portRef CI (instanceRef af_cmp_0))
+ (portRef COUT (instanceRef af_cmp_ci_a))))
+ (net fcnt_en_inv_inv
+ (joined
+ (portRef B0 (instanceRef af_cmp_0))
+ (portRef Z (instanceRef INV_0))))
+ (net fcount_0
+ (joined
+ (portRef A0 (instanceRef af_cmp_0))
+ (portRef Q (instanceRef FF_20))
+ (portRef PC0 (instanceRef bdcnt_bctr_0))
+ (portRef A0 (instanceRef e_cmp_0))
+ (portRef A0 (instanceRef g_cmp_0))))
+ (net fcount_1
+ (joined
+ (portRef A1 (instanceRef af_cmp_0))
+ (portRef Q (instanceRef FF_19))
+ (portRef PC1 (instanceRef bdcnt_bctr_0))
+ (portRef A1 (instanceRef e_cmp_0))
+ (portRef A1 (instanceRef g_cmp_0))))
+ (net co0_5
+ (joined
+ (portRef CI (instanceRef af_cmp_1))
+ (portRef GE (instanceRef af_cmp_0))))
+ (net cnt_con
+ (joined
+ (portRef B0 (instanceRef af_cmp_1))
+ (portRef Z (instanceRef AND2_t2))
+ (portRef A (instanceRef INV_2))
+ (portRef B1 (instanceRef bdcnt_bctr_cia))
+ (portRef A1 (instanceRef bdcnt_bctr_cia))
+ (portRef CON (instanceRef bdcnt_bctr_0))
+ (portRef CON (instanceRef bdcnt_bctr_1))
+ (portRef CON (instanceRef bdcnt_bctr_2))
+ (portRef B1 (instanceRef af_cmp_0))))
+ (net cnt_con_inv
+ (joined
+ (portRef B1 (instanceRef af_cmp_1))
+ (portRef Z (instanceRef INV_2))))
+ (net fcount_2
+ (joined
+ (portRef A0 (instanceRef af_cmp_1))
+ (portRef Q (instanceRef FF_18))
+ (portRef PC0 (instanceRef bdcnt_bctr_1))
+ (portRef A0 (instanceRef e_cmp_1))
+ (portRef A0 (instanceRef g_cmp_1))))
+ (net fcount_3
+ (joined
+ (portRef A1 (instanceRef af_cmp_1))
+ (portRef Q (instanceRef FF_17))
+ (portRef PC1 (instanceRef bdcnt_bctr_1))
+ (portRef A1 (instanceRef e_cmp_1))
+ (portRef A1 (instanceRef g_cmp_1))))
+ (net co1_5
+ (joined
+ (portRef CI (instanceRef af_cmp_2))
+ (portRef GE (instanceRef af_cmp_1))))
+ (net scuba_vhi
+ (joined
+ (portRef Z (instanceRef scuba_vhi_inst))
+ (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+ (portRef BE3 (instanceRef pdp_ram_0_0_0))
+ (portRef BE2 (instanceRef pdp_ram_0_0_0))
+ (portRef BE1 (instanceRef pdp_ram_0_0_0))
+ (portRef BE0 (instanceRef pdp_ram_0_0_0))
+ (portRef CER (instanceRef pdp_ram_0_0_0))
+ (portRef B0 (instanceRef e_cmp_ci_a))
+ (portRef B1 (instanceRef e_cmp_ci_a))
+ (portRef A0 (instanceRef e_cmp_ci_a))
+ (portRef A1 (instanceRef e_cmp_ci_a))
+ (portRef B0 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef g_cmp_ci_a))
+ (portRef A0 (instanceRef g_cmp_ci_a))
+ (portRef A1 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef w_ctr_cia))
+ (portRef A1 (instanceRef w_ctr_cia))
+ (portRef B1 (instanceRef r_ctr_cia))
+ (portRef A1 (instanceRef r_ctr_cia))
+ (portRef B0 (instanceRef af_cmp_ci_a))
+ (portRef B1 (instanceRef af_cmp_ci_a))
+ (portRef A0 (instanceRef af_cmp_ci_a))
+ (portRef A1 (instanceRef af_cmp_ci_a))
+ (portRef B0 (instanceRef af_cmp_2))))
+ (net fcount_4
+ (joined
+ (portRef A0 (instanceRef af_cmp_2))
+ (portRef Q (instanceRef FF_16))
+ (portRef PC0 (instanceRef bdcnt_bctr_2))
+ (portRef A0 (instanceRef e_cmp_2))
+ (portRef A0 (instanceRef g_cmp_2))))
+ (net fcount_5
+ (joined
+ (portRef A1 (instanceRef af_cmp_2))
+ (portRef Q (instanceRef FF_15))
+ (portRef PC1 (instanceRef bdcnt_bctr_2))
+ (portRef A1 (instanceRef e_cmp_2))
+ (portRef A1 (instanceRef g_cmp_2))))
+ (net af_d
+ (joined
+ (portRef S0 (instanceRef a2))
+ (portRef D (instanceRef FF_0))))
+ (net af_d_c
+ (joined
+ (portRef CI (instanceRef a2))
+ (portRef GE (instanceRef af_cmp_2))))
+ (net scuba_vlo
+ (joined
+ (portRef Z (instanceRef scuba_vlo_inst))
+ (portRef AD3 (instanceRef LUT4_1))
+ (portRef AD3 (instanceRef LUT4_0))
+ (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+ (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+ (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+ (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+ (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+ (portRef ADW8 (instanceRef pdp_ram_0_0_0))
+ (portRef ADW7 (instanceRef pdp_ram_0_0_0))
+ (portRef ADW6 (instanceRef pdp_ram_0_0_0))
+ (portRef ADW5 (instanceRef pdp_ram_0_0_0))
+ (portRef CI (instanceRef bdcnt_bctr_cia))
+ (portRef B0 (instanceRef bdcnt_bctr_cia))
+ (portRef A0 (instanceRef bdcnt_bctr_cia))
+ (portRef CI (instanceRef e_cmp_ci_a))
+ (portRef B1 (instanceRef e_cmp_0))
+ (portRef B0 (instanceRef e_cmp_1))
+ (portRef B1 (instanceRef e_cmp_1))
+ (portRef B0 (instanceRef e_cmp_2))
+ (portRef B1 (instanceRef e_cmp_2))
+ (portRef B0 (instanceRef a0))
+ (portRef B1 (instanceRef a0))
+ (portRef A0 (instanceRef a0))
+ (portRef A1 (instanceRef a0))
+ (portRef CI (instanceRef g_cmp_ci_a))
+ (portRef B0 (instanceRef a1))
+ (portRef B1 (instanceRef a1))
+ (portRef A0 (instanceRef a1))
+ (portRef A1 (instanceRef a1))
+ (portRef CI (instanceRef w_ctr_cia))
+ (portRef B0 (instanceRef w_ctr_cia))
+ (portRef A0 (instanceRef w_ctr_cia))
+ (portRef CI (instanceRef r_ctr_cia))
+ (portRef B0 (instanceRef r_ctr_cia))
+ (portRef A0 (instanceRef r_ctr_cia))
+ (portRef CI (instanceRef af_cmp_ci_a))
+ (portRef B1 (instanceRef af_cmp_2))
+ (portRef B0 (instanceRef a2))
+ (portRef B1 (instanceRef a2))
+ (portRef A0 (instanceRef a2))
+ (portRef A1 (instanceRef a2))))
+ (net partial_full
+ (joined
+ (portRef AlmostFull)
(portRef Q (instanceRef FF_0))))
(net Full
(joined
(portRef Full)
- (portRef Q (instanceRef FF_12))
- (portRef A (instanceRef INV_3))
+ (portRef Q (instanceRef FF_13))
+ (portRef A (instanceRef INV_8))
(portRef AD0 (instanceRef LUT4_0))))
(net Empty
(joined
(portRef Empty)
- (portRef Q (instanceRef FF_13))
- (portRef A (instanceRef INV_2))
+ (portRef Q (instanceRef FF_14))
+ (portRef A (instanceRef INV_7))
(portRef AD0 (instanceRef LUT4_1))))
(net dataout35
(joined
(joined
(portRef Reset)
(portRef RST (instanceRef pdp_ram_0_0_0))
+ (portRef CD (instanceRef FF_20))
(portRef CD (instanceRef FF_19))
(portRef CD (instanceRef FF_18))
(portRef CD (instanceRef FF_17))
(portRef CD (instanceRef FF_16))
(portRef CD (instanceRef FF_15))
- (portRef CD (instanceRef FF_14))
- (portRef PD (instanceRef FF_13))
+ (portRef PD (instanceRef FF_14))
+ (portRef CD (instanceRef FF_13))
(portRef CD (instanceRef FF_12))
(portRef CD (instanceRef FF_11))
(portRef CD (instanceRef FF_10))
(net rden
(joined
(portRef RdEn)
- (portRef A (instanceRef AND2_t2))))
+ (portRef A (instanceRef AND2_t3))))
(net wren
(joined
(portRef WrEn)
- (portRef A (instanceRef AND2_t3))))
+ (portRef A (instanceRef AND2_t4))))
(net clk
(joined
(portRef Clock)
(portRef CLKR (instanceRef pdp_ram_0_0_0))
(portRef CLKW (instanceRef pdp_ram_0_0_0))
+ (portRef CK (instanceRef FF_20))
(portRef CK (instanceRef FF_19))
(portRef CK (instanceRef FF_18))
(portRef CK (instanceRef FF_17))
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="FIFO_36x32_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 04 17 11:33:23.678" version="5.0" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="FIFO_36x32_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 09 10 16:33:20.511" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="FIFO_36x32_OutReg.lpc" type="lpc" modified="2015 04 17 11:33:22.000"/>
- <File name="FIFO_36x32_OutReg.vhd" type="top_level_vhdl" modified="2015 04 17 11:33:22.000"/>
- <File name="FIFO_36x32_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 04 17 11:33:22.000"/>
- <File name="tb_FIFO_36x32_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 04 17 11:33:22.000"/>
+ <File name="FIFO_36x32_OutReg.lpc" type="lpc" modified="2015 09 10 16:33:18.000"/>
+ <File name="FIFO_36x32_OutReg.vhd" type="top_level_vhdl" modified="2015 09 10 16:33:18.000"/>
+ <File name="FIFO_36x32_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 09 10 16:33:18.000"/>
+ <File name="tb_FIFO_36x32_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 09 10 16:33:18.000"/>
</Package>
</DiamondModule>
+MODULE FIFO_36x32_OutReg DEFIN FIFO_36x32_OutReg.vhd
+ SUBMODULE FADD2B
+ INSTANCE a2
+ SUBMODULE VLO
+ INSTANCE scuba_vlo_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_2
+ SUBMODULE VHI
+ INSTANCE scuba_vhi_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE af_cmp_ci_a
+ SUBMODULE CU2
+ INSTANCE r_ctr_2
+ SUBMODULE CU2
+ INSTANCE r_ctr_1
+ SUBMODULE CU2
+ INSTANCE r_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE r_ctr_cia
+ SUBMODULE CU2
+ INSTANCE w_ctr_2
+ SUBMODULE CU2
+ INSTANCE w_ctr_1
+ SUBMODULE CU2
+ INSTANCE w_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE w_ctr_cia
+ SUBMODULE FADD2B
+ INSTANCE a1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE g_cmp_ci_a
+ SUBMODULE FADD2B
+ INSTANCE a0
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_2
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_1
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE e_cmp_ci_a
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_2
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_1
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_0
+ SUBMODULE FADD2B
+ INSTANCE bdcnt_bctr_cia
+ SUBMODULE FD1S3DX
+ INSTANCE FF_0
+ SUBMODULE FD1P3DX
+ INSTANCE FF_1
+ SUBMODULE FD1P3DX
+ INSTANCE FF_2
+ SUBMODULE FD1P3DX
+ INSTANCE FF_3
+ SUBMODULE FD1P3DX
+ INSTANCE FF_4
+ SUBMODULE FD1P3DX
+ INSTANCE FF_5
+ SUBMODULE FD1P3DX
+ INSTANCE FF_6
+ SUBMODULE FD1P3DX
+ INSTANCE FF_7
+ SUBMODULE FD1P3DX
+ INSTANCE FF_8
+ SUBMODULE FD1P3DX
+ INSTANCE FF_9
+ SUBMODULE FD1P3DX
+ INSTANCE FF_10
+ SUBMODULE FD1P3DX
+ INSTANCE FF_11
+ SUBMODULE FD1P3DX
+ INSTANCE FF_12
+ SUBMODULE FD1S3DX
+ INSTANCE FF_13
+ SUBMODULE FD1S3BX
+ INSTANCE FF_14
+ SUBMODULE FD1P3DX
+ INSTANCE FF_15
+ SUBMODULE FD1P3DX
+ INSTANCE FF_16
+ SUBMODULE FD1P3DX
+ INSTANCE FF_17
+ SUBMODULE FD1P3DX
+ INSTANCE FF_18
+ SUBMODULE FD1P3DX
+ INSTANCE FF_19
+ SUBMODULE FD1P3DX
+ INSTANCE FF_20
+ SUBMODULE PDPW16KC
+ INSTANCE pdp_ram_0_0_0
+ SUBMODULE INV
+ INSTANCE INV_0
+ SUBMODULE INV
+ INSTANCE INV_1
+ SUBMODULE INV
+ INSTANCE INV_2
+ SUBMODULE INV
+ INSTANCE INV_3
+ SUBMODULE INV
+ INSTANCE INV_4
+ SUBMODULE AND2
+ INSTANCE AND2_t0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_1
+ SUBMODULE INV
+ INSTANCE INV_5
+ SUBMODULE INV
+ INSTANCE INV_6
+ SUBMODULE XOR2
+ INSTANCE XOR2_t1
+ SUBMODULE AND2
+ INSTANCE AND2_t2
+ SUBMODULE INV
+ INSTANCE INV_7
+ SUBMODULE AND2
+ INSTANCE AND2_t3
+ SUBMODULE INV
+ INSTANCE INV_8
+ SUBMODULE AND2
+ INSTANCE AND2_t4
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
-CoreRevision=5.0
+CoreRevision=5.1
ModuleName=FIFO_36x32_OutReg
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/17/2015
-Time=11:33:22
+Date=09/10/2015
+Time=16:33:18
[Parameters]
Verilog=0
PeMode=Static - Dual Threshold
PeAssert=10
PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=24
PfDeassert=506
RDataCount=0
EnECC=0
EnFWFT=0
[Command]
-cmd_line= -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1
+cmd_line= -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf 24
--- /dev/null
+Data[35] i
+Data[34] i
+Data[33] i
+Data[32] i
+Data[31] i
+Data[30] i
+Data[29] i
+Data[28] i
+Data[27] i
+Data[26] i
+Data[25] i
+Data[24] i
+Data[23] i
+Data[22] i
+Data[21] i
+Data[20] i
+Data[19] i
+Data[18] i
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+Clock i
+WrEn i
+RdEn i
+Reset i
+Q[35] o
+Q[34] o
+Q[33] o
+Q[32] o
+Q[31] o
+Q[30] o
+Q[29] o
+Q[28] o
+Q[27] o
+Q[26] o
+Q[25] o
+Q[24] o
+Q[23] o
+Q[22] o
+Q[21] o
+Q[20] o
+Q[19] o
+Q[18] o
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostFull o
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Apr 17 11:33:22 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:33:18 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf 24
Circuit name : FIFO_36x32_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x32_OutReg.edn
VHDL output : FIFO_36x32_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x32_OutReg.srp
Element Usage :
- AGEB2 : 3
+ AGEB2 : 6
ALEB2 : 3
- AND2 : 3
+ AND2 : 4
CU2 : 6
CB2 : 3
- FADD2B : 7
+ FADD2B : 9
FD1P3DX : 18
FD1S3BX : 1
- FD1S3DX : 1
- INV : 4
+ FD1S3DX : 2
+ INV : 9
ROM16X1A : 2
XOR2 : 1
PDPW16KC : 1
Estimated Resource Usage:
- LUT : 50
+ LUT : 61
EBR : 1
- Reg : 20
+ Reg : 21
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf -1
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+--/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 36 -depth 32 -regout -no_enable -pe -1 -pf 24
--- Fri Apr 17 11:33:22 2015
+-- Thu Sep 10 16:33:18 2015
library IEEE;
use IEEE.std_logic_1164.all;
Reset: in std_logic;
Q: out std_logic_vector(35 downto 0);
Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic;
+ AlmostFull: out std_logic);
end FIFO_36x32_OutReg;
architecture Structure of FIFO_36x32_OutReg is
-- internal signal declarations
+ signal invout_2: std_logic;
signal invout_1: std_logic;
- signal invout_0: std_logic;
signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal ifcount_4: std_logic;
signal ifcount_5: std_logic;
signal co2: std_logic;
- signal cnt_con: std_logic;
signal co1: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
signal co1_2: std_logic;
signal wren_i: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal co1_3: std_logic;
signal wcount_4: std_logic;
signal wcount_5: std_logic;
- signal scuba_vlo: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_ctr_ci: std_logic;
signal co1_4: std_logic;
signal rcount_4: std_logic;
signal rcount_5: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
-- local component declarations
component AGEB2
attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x32_OutReg.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_20 : label is "ENABLED";
attribute GSR of FF_19 : label is "ENABLED";
attribute GSR of FF_18 : label is "ENABLED";
attribute GSR of FF_17 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t3: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_3: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
- AND2_t2: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_2: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
- AND2_t1: AND2
+ AND2_t2: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t0: XOR2
+ XOR2_t1: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_1: INV
+ INV_6: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_0: INV
+ INV_5: INV
port map (A=>wren_i, Z=>wren_i_inv);
LUT4_1: ROM16X1A
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
pdp_ram_0_0_0: PDPW16KC
generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
- FF_19: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_18: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_17: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_16: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_15: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_14: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_13: FD1S3BX
+ FF_14: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_12: FD1S3DX
+ FF_13: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_11: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_10: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_9: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_8: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_7: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_6: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_5: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_4: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_3: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_2: FD1P3DX
+ FF_3: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_1: FD1P3DX
+ FF_2: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_0: FD1P3DX
+ FF_1: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
+ FF_0: FD1S3DX
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_1,
NC0=>iwcount_4, NC1=>iwcount_5);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_ctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_2,
NC0=>ircount_4, NC1=>ircount_5);
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con,
+ B1=>cnt_con_inv, CI=>co0_5, GE=>co1_5);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vlo, CI=>co1_5, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
Empty <= empty_i;
Full <= full_i;
end Structure;
Starting process:
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Apr 17 11:33:22 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:33:18 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf 24
Circuit name : FIFO_36x32_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x32_OutReg.edn
VHDL output : FIFO_36x32_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x32_OutReg.srp
Estimated Resource Usage:
- LUT : 50
+ LUT : 61
EBR : 1
- Reg : 20
+ Reg : 21
END SCUBA Module Synthesis
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
--- Fri Apr 17 11:33:22 2015
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+-- Thu Sep 10 16:33:18 2015
-- parameterized module component declaration
component FIFO_36x32_OutReg
port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic;
WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
Q: out std_logic_vector(35 downto 0); Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic; AlmostFull: out std_logic);
end component;
-- parameterized module component instance
__ : FIFO_36x32_OutReg
port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__);
+ Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostFull=>__);
(keywordMap (keywordLevel 0))
(status
(written
- (timestamp 2015 4 17 11 33 43)
- (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
- (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf -1 ")
+ (timestamp 2015 9 10 16 32 54)
+ (program "SCUBA" (version "Diamond (64-bit) 3.5.0.102"))))
+ (comment "/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf 56 ")
(library ORCLIB
(edifLevel 0)
(technology
(port Empty
(direction OUTPUT))
(port Full
+ (direction OUTPUT))
+ (port AlmostFull
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
- (instance AND2_t3
+ (instance AND2_t4
(viewRef view1
(cellRef AND2)))
- (instance INV_3
+ (instance INV_8
(viewRef view1
(cellRef INV)))
- (instance AND2_t2
+ (instance AND2_t3
(viewRef view1
(cellRef AND2)))
- (instance INV_2
+ (instance INV_7
(viewRef view1
(cellRef INV)))
- (instance AND2_t1
+ (instance AND2_t2
(viewRef view1
(cellRef AND2)))
- (instance XOR2_t0
+ (instance XOR2_t1
(viewRef view1
(cellRef XOR2)))
- (instance INV_1
+ (instance INV_6
(viewRef view1
(cellRef INV)))
- (instance INV_0
+ (instance INV_5
(viewRef view1
(cellRef INV)))
(instance LUT4_1
(cellRef ROM16X1A))
(property initval
(string "0x3232")))
+ (instance AND2_t0
+ (viewRef view1
+ (cellRef AND2)))
+ (instance INV_4
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_3
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_2
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_1
+ (viewRef view1
+ (cellRef INV)))
+ (instance INV_0
+ (viewRef view1
+ (cellRef INV)))
(instance pdp_ram_0_0_0
(viewRef view1
(cellRef PDPW16KC))
(string "36"))
(property DATA_WIDTH_W
(string "36")))
+ (instance FF_23
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
(instance FF_22
(viewRef view1
(cellRef FD1P3DX))
(string "ENABLED")))
(instance FF_16
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3BX))
(property GSR
(string "ENABLED")))
(instance FF_15
(viewRef view1
- (cellRef FD1S3BX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance FF_14
(viewRef view1
- (cellRef FD1S3DX))
+ (cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_13
(string "ENABLED")))
(instance FF_0
(viewRef view1
- (cellRef FD1P3DX))
+ (cellRef FD1S3DX))
(property GSR
(string "ENABLED")))
(instance bdcnt_bctr_cia
(instance w_ctr_3
(viewRef view1
(cellRef CU2)))
- (instance scuba_vhi_inst
- (viewRef view1
- (cellRef VHI)))
(instance r_ctr_cia
(viewRef view1
(cellRef FADD2B)))
(instance r_ctr_3
(viewRef view1
(cellRef CU2)))
+ (instance af_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance af_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance scuba_vhi_inst
+ (viewRef view1
+ (cellRef VHI)))
+ (instance af_cmp_2
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance af_cmp_3
+ (viewRef view1
+ (cellRef AGEB2)))
(instance scuba_vlo_inst
(viewRef view1
(cellRef VLO)))
+ (instance a2
+ (viewRef view1
+ (cellRef FADD2B)))
+ (net invout_2
+ (joined
+ (portRef Z (instanceRef INV_8))
+ (portRef B (instanceRef AND2_t4))))
(net invout_1
(joined
- (portRef Z (instanceRef INV_3))
+ (portRef Z (instanceRef INV_7))
(portRef B (instanceRef AND2_t3))))
- (net invout_0
+ (net rden_i_inv
(joined
- (portRef Z (instanceRef INV_2))
+ (portRef Z (instanceRef INV_6))
(portRef B (instanceRef AND2_t2))))
- (net rden_i_inv
+ (net invout_0
(joined
- (portRef Z (instanceRef INV_1))
- (portRef B (instanceRef AND2_t1))))
+ (portRef Z (instanceRef INV_4))
+ (portRef B (instanceRef AND2_t0))))
+ (net r_nw_inv
+ (joined
+ (portRef Z (instanceRef INV_1))))
+ (net r_nw
+ (joined
+ (portRef A (instanceRef INV_1))
+ (portRef Z (instanceRef AND2_t0))))
+ (net fcnt_en_inv
+ (joined
+ (portRef A (instanceRef INV_0))
+ (portRef Z (instanceRef INV_3))))
(net fcnt_en
(joined
- (portRef SP (instanceRef FF_16))
- (portRef Z (instanceRef XOR2_t0))
+ (portRef SP (instanceRef FF_17))
+ (portRef Z (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_3))
+ (portRef SP (instanceRef FF_23))
(portRef SP (instanceRef FF_22))
(portRef SP (instanceRef FF_21))
(portRef SP (instanceRef FF_20))
(portRef SP (instanceRef FF_19))
- (portRef SP (instanceRef FF_18))
- (portRef SP (instanceRef FF_17))))
+ (portRef SP (instanceRef FF_18))))
(net empty_d
(joined
- (portRef D (instanceRef FF_15))
+ (portRef D (instanceRef FF_16))
(portRef DO0 (instanceRef LUT4_1))))
(net full_d
(joined
- (portRef D (instanceRef FF_14))
+ (portRef D (instanceRef FF_15))
(portRef DO0 (instanceRef LUT4_0))))
(net ifcount_0
(joined
(portRef NC0 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_22))))
+ (portRef D (instanceRef FF_23))))
(net ifcount_1
(joined
(portRef NC1 (instanceRef bdcnt_bctr_0))
- (portRef D (instanceRef FF_21))))
+ (portRef D (instanceRef FF_22))))
(net bdcnt_bctr_ci
(joined
(portRef CI (instanceRef bdcnt_bctr_0))
(net ifcount_2
(joined
(portRef NC0 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_20))))
+ (portRef D (instanceRef FF_21))))
(net ifcount_3
(joined
(portRef NC1 (instanceRef bdcnt_bctr_1))
- (portRef D (instanceRef FF_19))))
+ (portRef D (instanceRef FF_20))))
(net co0
(joined
(portRef CI (instanceRef bdcnt_bctr_1))
(net ifcount_4
(joined
(portRef NC0 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_18))))
+ (portRef D (instanceRef FF_19))))
(net ifcount_5
(joined
(portRef NC1 (instanceRef bdcnt_bctr_2))
- (portRef D (instanceRef FF_17))))
+ (portRef D (instanceRef FF_18))))
(net co1
(joined
(portRef CI (instanceRef bdcnt_bctr_2))
(net ifcount_6
(joined
(portRef NC0 (instanceRef bdcnt_bctr_3))
- (portRef D (instanceRef FF_16))))
+ (portRef D (instanceRef FF_17))))
(net co3
(joined
(portRef CO (instanceRef bdcnt_bctr_3))))
- (net cnt_con
- (joined
- (portRef CON (instanceRef bdcnt_bctr_3))
- (portRef Z (instanceRef AND2_t1))
- (portRef B1 (instanceRef bdcnt_bctr_cia))
- (portRef A1 (instanceRef bdcnt_bctr_cia))
- (portRef CON (instanceRef bdcnt_bctr_0))
- (portRef CON (instanceRef bdcnt_bctr_1))
- (portRef CON (instanceRef bdcnt_bctr_2))))
(net co2
(joined
(portRef CI (instanceRef bdcnt_bctr_3))
(net rden_i
(joined
(portRef B0 (instanceRef e_cmp_0))
- (portRef Z (instanceRef AND2_t2))
- (portRef B (instanceRef XOR2_t0))
- (portRef A (instanceRef INV_1))
+ (portRef Z (instanceRef AND2_t3))
+ (portRef B (instanceRef XOR2_t1))
+ (portRef A (instanceRef INV_6))
(portRef AD1 (instanceRef LUT4_0))
+ (portRef A (instanceRef AND2_t0))
(portRef CSR0 (instanceRef pdp_ram_0_0_0))
+ (portRef SP (instanceRef FF_7))
(portRef SP (instanceRef FF_6))
(portRef SP (instanceRef FF_5))
(portRef SP (instanceRef FF_4))
(portRef SP (instanceRef FF_3))
(portRef SP (instanceRef FF_2))
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- (portRef SP (instanceRef FF_0))))
+ (portRef SP (instanceRef FF_1))))
(net co0_1
(joined
(portRef CI (instanceRef e_cmp_1))
(joined
(portRef CI (instanceRef g_cmp_0))
(portRef COUT (instanceRef g_cmp_ci_a))))
- (net fcount_0
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- (portRef A0 (instanceRef g_cmp_0))
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(portRef CI (instanceRef g_cmp_1))
(portRef GE (instanceRef g_cmp_0))))
- (net fcount_2
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- (portRef A0 (instanceRef g_cmp_1))
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(portRef CI (instanceRef g_cmp_2))
(net wren_i
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(portRef B1 (instanceRef g_cmp_2))
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- (portRef A (instanceRef AND2_t1))
- (portRef A (instanceRef XOR2_t0))
- (portRef A (instanceRef INV_0))
+ (portRef Z (instanceRef AND2_t4))
+ (portRef A (instanceRef AND2_t2))
+ (portRef A (instanceRef XOR2_t1))
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(portRef AD1 (instanceRef LUT4_1))
+ (portRef A (instanceRef INV_4))
(portRef CEW (instanceRef pdp_ram_0_0_0))
+ (portRef SP (instanceRef FF_14))
(portRef SP (instanceRef FF_13))
(portRef SP (instanceRef FF_12))
(portRef SP (instanceRef FF_11))
(portRef SP (instanceRef FF_10))
(portRef SP (instanceRef FF_9))
(portRef SP (instanceRef FF_8))
- (portRef SP (instanceRef FF_7))
(portRef B0 (instanceRef g_cmp_0))
(portRef B1 (instanceRef g_cmp_0))
(portRef B0 (instanceRef g_cmp_1))
(portRef B1 (instanceRef g_cmp_1))
(portRef B0 (instanceRef g_cmp_2))))
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- (portRef A0 (instanceRef g_cmp_2))
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(portRef CI (instanceRef g_cmp_3))
(net wren_i_inv
(joined
(portRef B0 (instanceRef g_cmp_3))
- (portRef Z (instanceRef INV_0))))
- (net fcount_6
- (joined
- (portRef A0 (instanceRef g_cmp_3))
- (portRef Q (instanceRef FF_16))
- (portRef PC0 (instanceRef bdcnt_bctr_3))
- (portRef A0 (instanceRef e_cmp_3))))
+ (portRef Z (instanceRef INV_5))))
(net cmp_ge_d1
(joined
(portRef S0 (instanceRef a1))
(net iwcount_0
(joined
(portRef NC0 (instanceRef w_ctr_0))
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(net iwcount_1
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(portRef NC1 (instanceRef w_ctr_0))
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+ (portRef D (instanceRef FF_13))))
(net w_ctr_ci
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(portRef CI (instanceRef w_ctr_0))
(joined
(portRef PC0 (instanceRef w_ctr_0))
(portRef ADW0 (instanceRef pdp_ram_0_0_0))
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(portRef ADW1 (instanceRef pdp_ram_0_0_0))
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(net iwcount_2
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(portRef NC0 (instanceRef w_ctr_1))
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+ (portRef D (instanceRef FF_12))))
(net iwcount_3
(joined
(portRef NC1 (instanceRef w_ctr_1))
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+ (portRef D (instanceRef FF_11))))
(net co0_3
(joined
(portRef CI (instanceRef w_ctr_1))
(joined
(portRef PC0 (instanceRef w_ctr_1))
(portRef ADW2 (instanceRef pdp_ram_0_0_0))
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(net wcount_3
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(portRef PC1 (instanceRef w_ctr_1))
(portRef ADW3 (instanceRef pdp_ram_0_0_0))
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(net iwcount_4
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(portRef NC0 (instanceRef w_ctr_2))
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+ (portRef D (instanceRef FF_10))))
(net iwcount_5
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(portRef NC1 (instanceRef w_ctr_2))
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(net co1_3
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(portRef CI (instanceRef w_ctr_2))
(joined
(portRef PC0 (instanceRef w_ctr_2))
(portRef ADW4 (instanceRef pdp_ram_0_0_0))
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(portRef PC1 (instanceRef w_ctr_2))
(portRef ADW5 (instanceRef pdp_ram_0_0_0))
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(net iwcount_6
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(portRef NC0 (instanceRef w_ctr_3))
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+ (portRef D (instanceRef FF_8))))
(net co3_1
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(portRef CO (instanceRef w_ctr_3))))
(net wcount_6
(joined
(portRef PC0 (instanceRef w_ctr_3))
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- (net scuba_vhi
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- (portRef Z (instanceRef scuba_vhi_inst))
- (portRef CSW0 (instanceRef pdp_ram_0_0_0))
- (portRef BE3 (instanceRef pdp_ram_0_0_0))
- (portRef BE2 (instanceRef pdp_ram_0_0_0))
- (portRef BE1 (instanceRef pdp_ram_0_0_0))
- (portRef BE0 (instanceRef pdp_ram_0_0_0))
- (portRef CER (instanceRef pdp_ram_0_0_0))
- (portRef B0 (instanceRef e_cmp_ci_a))
- (portRef B1 (instanceRef e_cmp_ci_a))
- (portRef A0 (instanceRef e_cmp_ci_a))
- (portRef A1 (instanceRef e_cmp_ci_a))
- (portRef B0 (instanceRef g_cmp_ci_a))
- (portRef B1 (instanceRef g_cmp_ci_a))
- (portRef A0 (instanceRef g_cmp_ci_a))
- (portRef A1 (instanceRef g_cmp_ci_a))
- (portRef B1 (instanceRef w_ctr_cia))
- (portRef A1 (instanceRef w_ctr_cia))
- (portRef B1 (instanceRef r_ctr_cia))
- (portRef A1 (instanceRef r_ctr_cia))))
+ (portRef Q (instanceRef FF_8))))
(net ircount_0
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(portRef NC0 (instanceRef r_ctr_0))
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+ (portRef D (instanceRef FF_7))))
(net ircount_1
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(portRef NC1 (instanceRef r_ctr_0))
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+ (portRef D (instanceRef FF_6))))
(net r_ctr_ci
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(portRef CI (instanceRef r_ctr_0))
(joined
(portRef PC0 (instanceRef r_ctr_0))
(portRef ADR5 (instanceRef pdp_ram_0_0_0))
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(net rcount_1
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(portRef ADR6 (instanceRef pdp_ram_0_0_0))
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(portRef NC0 (instanceRef r_ctr_1))
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(net ircount_3
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(portRef NC1 (instanceRef r_ctr_1))
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(net co0_4
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(portRef CI (instanceRef r_ctr_1))
(joined
(portRef PC0 (instanceRef r_ctr_1))
(portRef ADR7 (instanceRef pdp_ram_0_0_0))
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(portRef ADR8 (instanceRef pdp_ram_0_0_0))
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(net ircount_4
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(portRef NC0 (instanceRef r_ctr_2))
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+ (portRef D (instanceRef FF_3))))
(net ircount_5
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(portRef NC1 (instanceRef r_ctr_2))
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+ (portRef D (instanceRef FF_2))))
(net co1_4
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(portRef CI (instanceRef r_ctr_2))
(joined
(portRef PC0 (instanceRef r_ctr_2))
(portRef ADR9 (instanceRef pdp_ram_0_0_0))
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(net rcount_5
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(portRef PC1 (instanceRef r_ctr_2))
(portRef ADR10 (instanceRef pdp_ram_0_0_0))
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(net ircount_6
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(portRef NC0 (instanceRef r_ctr_3))
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(net co3_2
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(portRef CO (instanceRef r_ctr_3))))
(net rcount_6
(joined
(portRef PC0 (instanceRef r_ctr_3))
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+ (portRef CI (instanceRef af_cmp_0))
+ (portRef COUT (instanceRef af_cmp_ci_a))))
+ (net fcnt_en_inv_inv
+ (joined
+ (portRef B0 (instanceRef af_cmp_0))
+ (portRef Z (instanceRef INV_0))))
+ (net fcount_0
+ (joined
+ (portRef A0 (instanceRef af_cmp_0))
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+ (portRef PC0 (instanceRef bdcnt_bctr_0))
+ (portRef A0 (instanceRef e_cmp_0))
+ (portRef A0 (instanceRef g_cmp_0))))
+ (net fcount_1
+ (joined
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+ (portRef A1 (instanceRef g_cmp_0))))
+ (net co0_5
+ (joined
+ (portRef CI (instanceRef af_cmp_1))
+ (portRef GE (instanceRef af_cmp_0))))
+ (net cnt_con
+ (joined
+ (portRef B0 (instanceRef af_cmp_1))
+ (portRef Z (instanceRef AND2_t2))
+ (portRef A (instanceRef INV_2))
+ (portRef B1 (instanceRef bdcnt_bctr_cia))
+ (portRef A1 (instanceRef bdcnt_bctr_cia))
+ (portRef CON (instanceRef bdcnt_bctr_0))
+ (portRef CON (instanceRef bdcnt_bctr_1))
+ (portRef CON (instanceRef bdcnt_bctr_2))
+ (portRef CON (instanceRef bdcnt_bctr_3))
+ (portRef B1 (instanceRef af_cmp_0))))
+ (net cnt_con_inv
+ (joined
+ (portRef B1 (instanceRef af_cmp_1))
+ (portRef Z (instanceRef INV_2))))
+ (net fcount_2
+ (joined
+ (portRef A0 (instanceRef af_cmp_1))
+ (portRef Q (instanceRef FF_21))
+ (portRef PC0 (instanceRef bdcnt_bctr_1))
+ (portRef A0 (instanceRef e_cmp_1))
+ (portRef A0 (instanceRef g_cmp_1))))
+ (net fcount_3
+ (joined
+ (portRef A1 (instanceRef af_cmp_1))
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+ (portRef A1 (instanceRef e_cmp_1))
+ (portRef A1 (instanceRef g_cmp_1))))
+ (net co1_5
+ (joined
+ (portRef CI (instanceRef af_cmp_2))
+ (portRef GE (instanceRef af_cmp_1))))
+ (net scuba_vhi
+ (joined
+ (portRef Z (instanceRef scuba_vhi_inst))
+ (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+ (portRef BE3 (instanceRef pdp_ram_0_0_0))
+ (portRef BE2 (instanceRef pdp_ram_0_0_0))
+ (portRef BE1 (instanceRef pdp_ram_0_0_0))
+ (portRef BE0 (instanceRef pdp_ram_0_0_0))
+ (portRef CER (instanceRef pdp_ram_0_0_0))
+ (portRef B0 (instanceRef e_cmp_ci_a))
+ (portRef B1 (instanceRef e_cmp_ci_a))
+ (portRef A0 (instanceRef e_cmp_ci_a))
+ (portRef A1 (instanceRef e_cmp_ci_a))
+ (portRef B0 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef g_cmp_ci_a))
+ (portRef A0 (instanceRef g_cmp_ci_a))
+ (portRef A1 (instanceRef g_cmp_ci_a))
+ (portRef B1 (instanceRef w_ctr_cia))
+ (portRef A1 (instanceRef w_ctr_cia))
+ (portRef B1 (instanceRef r_ctr_cia))
+ (portRef A1 (instanceRef r_ctr_cia))
+ (portRef B0 (instanceRef af_cmp_ci_a))
+ (portRef B1 (instanceRef af_cmp_ci_a))
+ (portRef A0 (instanceRef af_cmp_ci_a))
+ (portRef A1 (instanceRef af_cmp_ci_a))
+ (portRef B0 (instanceRef af_cmp_2))
+ (portRef B1 (instanceRef af_cmp_2))))
+ (net fcount_4
+ (joined
+ (portRef A0 (instanceRef af_cmp_2))
+ (portRef Q (instanceRef FF_19))
+ (portRef PC0 (instanceRef bdcnt_bctr_2))
+ (portRef A0 (instanceRef e_cmp_2))
+ (portRef A0 (instanceRef g_cmp_2))))
+ (net fcount_5
+ (joined
+ (portRef A1 (instanceRef af_cmp_2))
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+ (portRef PC1 (instanceRef bdcnt_bctr_2))
+ (portRef A1 (instanceRef e_cmp_2))
+ (portRef A1 (instanceRef g_cmp_2))))
+ (net co2_5
+ (joined
+ (portRef CI (instanceRef af_cmp_3))
+ (portRef GE (instanceRef af_cmp_2))))
+ (net fcount_6
+ (joined
+ (portRef A0 (instanceRef af_cmp_3))
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+ (portRef PC0 (instanceRef bdcnt_bctr_3))
+ (portRef A0 (instanceRef e_cmp_3))
+ (portRef A0 (instanceRef g_cmp_3))))
+ (net af_d
+ (joined
+ (portRef S0 (instanceRef a2))
+ (portRef D (instanceRef FF_0))))
+ (net af_d_c
+ (joined
+ (portRef CI (instanceRef a2))
+ (portRef GE (instanceRef af_cmp_3))))
(net scuba_vlo
(joined
(portRef Z (instanceRef scuba_vlo_inst))
(portRef CI (instanceRef r_ctr_cia))
(portRef B0 (instanceRef r_ctr_cia))
(portRef A0 (instanceRef r_ctr_cia))
- (portRef PC1 (instanceRef r_ctr_3))))
+ (portRef PC1 (instanceRef r_ctr_3))
+ (portRef CI (instanceRef af_cmp_ci_a))
+ (portRef B0 (instanceRef af_cmp_3))
+ (portRef B1 (instanceRef af_cmp_3))
+ (portRef A1 (instanceRef af_cmp_3))
+ (portRef B0 (instanceRef a2))
+ (portRef B1 (instanceRef a2))
+ (portRef A0 (instanceRef a2))
+ (portRef A1 (instanceRef a2))))
+ (net partial_full
+ (joined
+ (portRef AlmostFull)
+ (portRef Q (instanceRef FF_0))))
(net Full
(joined
(portRef Full)
- (portRef Q (instanceRef FF_14))
- (portRef A (instanceRef INV_3))
+ (portRef Q (instanceRef FF_15))
+ (portRef A (instanceRef INV_8))
(portRef AD0 (instanceRef LUT4_0))))
(net Empty
(joined
(portRef Empty)
- (portRef Q (instanceRef FF_15))
- (portRef A (instanceRef INV_2))
+ (portRef Q (instanceRef FF_16))
+ (portRef A (instanceRef INV_7))
(portRef AD0 (instanceRef LUT4_1))))
(net dataout35
(joined
(joined
(portRef Reset)
(portRef RST (instanceRef pdp_ram_0_0_0))
+ (portRef CD (instanceRef FF_23))
(portRef CD (instanceRef FF_22))
(portRef CD (instanceRef FF_21))
(portRef CD (instanceRef FF_20))
(portRef CD (instanceRef FF_19))
(portRef CD (instanceRef FF_18))
(portRef CD (instanceRef FF_17))
- (portRef CD (instanceRef FF_16))
- (portRef PD (instanceRef FF_15))
+ (portRef PD (instanceRef FF_16))
+ (portRef CD (instanceRef FF_15))
(portRef CD (instanceRef FF_14))
(portRef CD (instanceRef FF_13))
(portRef CD (instanceRef FF_12))
(net rden
(joined
(portRef RdEn)
- (portRef A (instanceRef AND2_t2))))
+ (portRef A (instanceRef AND2_t3))))
(net wren
(joined
(portRef WrEn)
- (portRef A (instanceRef AND2_t3))))
+ (portRef A (instanceRef AND2_t4))))
(net clk
(joined
(portRef Clock)
(portRef CLKR (instanceRef pdp_ram_0_0_0))
(portRef CLKW (instanceRef pdp_ram_0_0_0))
+ (portRef CK (instanceRef FF_23))
(portRef CK (instanceRef FF_22))
(portRef CK (instanceRef FF_21))
(portRef CK (instanceRef FF_20))
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="FIFO_36x64_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 04 17 11:33:44.222" version="5.0" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="FIFO_36x64_OutReg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 09 10 16:32:55.698" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="FIFO_36x64_OutReg.lpc" type="lpc" modified="2015 04 17 11:33:43.000"/>
- <File name="FIFO_36x64_OutReg.vhd" type="top_level_vhdl" modified="2015 04 17 11:33:43.000"/>
- <File name="FIFO_36x64_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 04 17 11:33:43.000"/>
- <File name="tb_FIFO_36x64_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 04 17 11:33:43.000"/>
+ <File name="FIFO_36x64_OutReg.lpc" type="lpc" modified="2015 09 10 16:32:54.000"/>
+ <File name="FIFO_36x64_OutReg.vhd" type="top_level_vhdl" modified="2015 09 10 16:32:54.000"/>
+ <File name="FIFO_36x64_OutReg_tmpl.vhd" type="template_vhdl" modified="2015 09 10 16:32:54.000"/>
+ <File name="tb_FIFO_36x64_OutReg_tmpl.vhd" type="testbench_vhdl" modified="2015 09 10 16:32:54.000"/>
</Package>
</DiamondModule>
+MODULE FIFO_36x64_OutReg DEFIN FIFO_36x64_OutReg.vhd
+ SUBMODULE FADD2B
+ INSTANCE a2
+ SUBMODULE VLO
+ INSTANCE scuba_vlo_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_3
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_2
+ SUBMODULE VHI
+ INSTANCE scuba_vhi_inst
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE af_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE af_cmp_ci_a
+ SUBMODULE CU2
+ INSTANCE r_ctr_3
+ SUBMODULE CU2
+ INSTANCE r_ctr_2
+ SUBMODULE CU2
+ INSTANCE r_ctr_1
+ SUBMODULE CU2
+ INSTANCE r_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE r_ctr_cia
+ SUBMODULE CU2
+ INSTANCE w_ctr_3
+ SUBMODULE CU2
+ INSTANCE w_ctr_2
+ SUBMODULE CU2
+ INSTANCE w_ctr_1
+ SUBMODULE CU2
+ INSTANCE w_ctr_0
+ SUBMODULE FADD2B
+ INSTANCE w_ctr_cia
+ SUBMODULE FADD2B
+ INSTANCE a1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_3
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_2
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_1
+ SUBMODULE AGEB2
+ INSTANCE g_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE g_cmp_ci_a
+ SUBMODULE FADD2B
+ INSTANCE a0
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_3
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_2
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_1
+ SUBMODULE ALEB2
+ INSTANCE e_cmp_0
+ SUBMODULE FADD2B
+ INSTANCE e_cmp_ci_a
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_3
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_2
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_1
+ SUBMODULE CB2
+ INSTANCE bdcnt_bctr_0
+ SUBMODULE FADD2B
+ INSTANCE bdcnt_bctr_cia
+ SUBMODULE FD1S3DX
+ INSTANCE FF_0
+ SUBMODULE FD1P3DX
+ INSTANCE FF_1
+ SUBMODULE FD1P3DX
+ INSTANCE FF_2
+ SUBMODULE FD1P3DX
+ INSTANCE FF_3
+ SUBMODULE FD1P3DX
+ INSTANCE FF_4
+ SUBMODULE FD1P3DX
+ INSTANCE FF_5
+ SUBMODULE FD1P3DX
+ INSTANCE FF_6
+ SUBMODULE FD1P3DX
+ INSTANCE FF_7
+ SUBMODULE FD1P3DX
+ INSTANCE FF_8
+ SUBMODULE FD1P3DX
+ INSTANCE FF_9
+ SUBMODULE FD1P3DX
+ INSTANCE FF_10
+ SUBMODULE FD1P3DX
+ INSTANCE FF_11
+ SUBMODULE FD1P3DX
+ INSTANCE FF_12
+ SUBMODULE FD1P3DX
+ INSTANCE FF_13
+ SUBMODULE FD1P3DX
+ INSTANCE FF_14
+ SUBMODULE FD1S3DX
+ INSTANCE FF_15
+ SUBMODULE FD1S3BX
+ INSTANCE FF_16
+ SUBMODULE FD1P3DX
+ INSTANCE FF_17
+ SUBMODULE FD1P3DX
+ INSTANCE FF_18
+ SUBMODULE FD1P3DX
+ INSTANCE FF_19
+ SUBMODULE FD1P3DX
+ INSTANCE FF_20
+ SUBMODULE FD1P3DX
+ INSTANCE FF_21
+ SUBMODULE FD1P3DX
+ INSTANCE FF_22
+ SUBMODULE FD1P3DX
+ INSTANCE FF_23
+ SUBMODULE PDPW16KC
+ INSTANCE pdp_ram_0_0_0
+ SUBMODULE INV
+ INSTANCE INV_0
+ SUBMODULE INV
+ INSTANCE INV_1
+ SUBMODULE INV
+ INSTANCE INV_2
+ SUBMODULE INV
+ INSTANCE INV_3
+ SUBMODULE INV
+ INSTANCE INV_4
+ SUBMODULE AND2
+ INSTANCE AND2_t0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_0
+ SUBMODULE ROM16X1A
+ INSTANCE LUT4_1
+ SUBMODULE INV
+ INSTANCE INV_5
+ SUBMODULE INV
+ INSTANCE INV_6
+ SUBMODULE XOR2
+ INSTANCE XOR2_t1
+ SUBMODULE AND2
+ INSTANCE AND2_t2
+ SUBMODULE INV
+ INSTANCE INV_7
+ SUBMODULE AND2
+ INSTANCE AND2_t3
+ SUBMODULE INV
+ INSTANCE INV_8
+ SUBMODULE AND2
+ INSTANCE AND2_t4
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
-CoreRevision=5.0
+CoreRevision=5.1
ModuleName=FIFO_36x64_OutReg
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/17/2015
-Time=11:33:43
+Date=09/10/2015
+Time=16:32:54
[Parameters]
Verilog=0
PeMode=Static - Dual Threshold
PeAssert=10
PeDeassert=12
-FullFlg=0
-PfMode=Static - Dual Threshold
-PfAssert=508
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=56
PfDeassert=506
RDataCount=0
EnECC=0
EnFWFT=0
[Command]
-cmd_line= -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1
+cmd_line= -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf 56
--- /dev/null
+Data[35] i
+Data[34] i
+Data[33] i
+Data[32] i
+Data[31] i
+Data[30] i
+Data[29] i
+Data[28] i
+Data[27] i
+Data[26] i
+Data[25] i
+Data[24] i
+Data[23] i
+Data[22] i
+Data[21] i
+Data[20] i
+Data[19] i
+Data[18] i
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+Clock i
+WrEn i
+RdEn i
+Reset i
+Q[35] o
+Q[34] o
+Q[33] o
+Q[32] o
+Q[31] o
+Q[30] o
+Q[29] o
+Q[28] o
+Q[27] o
+Q[26] o
+Q[25] o
+Q[24] o
+Q[23] o
+Q[22] o
+Q[21] o
+Q[20] o
+Q[19] o
+Q[18] o
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostFull o
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Apr 17 11:33:43 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:32:54 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf 56
Circuit name : FIFO_36x64_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x64_OutReg.edn
VHDL output : FIFO_36x64_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x64_OutReg.srp
Element Usage :
- AGEB2 : 4
+ AGEB2 : 8
ALEB2 : 4
- AND2 : 3
+ AND2 : 4
CU2 : 8
CB2 : 4
- FADD2B : 7
+ FADD2B : 9
FD1P3DX : 21
FD1S3BX : 1
- FD1S3DX : 1
- INV : 4
+ FD1S3DX : 2
+ INV : 9
ROM16X1A : 2
XOR2 : 1
PDPW16KC : 1
Estimated Resource Usage:
- LUT : 60
+ LUT : 73
EBR : 1
- Reg : 23
+ Reg : 24
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf -1
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+--/opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -regout -no_enable -pe -1 -pf 56
--- Fri Apr 17 11:33:43 2015
+-- Thu Sep 10 16:32:54 2015
library IEEE;
use IEEE.std_logic_1164.all;
Reset: in std_logic;
Q: out std_logic_vector(35 downto 0);
Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic;
+ AlmostFull: out std_logic);
end FIFO_36x64_OutReg;
architecture Structure of FIFO_36x64_OutReg is
-- internal signal declarations
+ signal invout_2: std_logic;
signal invout_1: std_logic;
- signal invout_0: std_logic;
signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal co1: std_logic;
signal ifcount_6: std_logic;
signal co3: std_logic;
- signal cnt_con: std_logic;
signal co2: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
signal co1_2: std_logic;
signal wren_i: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
signal co2_2: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_6: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal co3_1: std_logic;
signal co2_3: std_logic;
signal wcount_6: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_ctr_ci: std_logic;
signal co3_2: std_logic;
signal co2_4: std_logic;
signal rcount_6: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal fcount_6: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x64_OutReg.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_23 : label is "ENABLED";
attribute GSR of FF_22 : label is "ENABLED";
attribute GSR of FF_21 : label is "ENABLED";
attribute GSR of FF_20 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t3: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_3: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
- AND2_t2: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_2: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
- AND2_t1: AND2
+ AND2_t2: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t0: XOR2
+ XOR2_t1: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_1: INV
+ INV_6: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_0: INV
+ INV_5: INV
port map (A=>wren_i, Z=>wren_i_inv);
LUT4_1: ROM16X1A
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
pdp_ram_0_0_0: PDPW16KC
generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
- FF_22: FD1P3DX
+ FF_23: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_21: FD1P3DX
+ FF_22: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_20: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_19: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_18: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_17: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_16: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_15: FD1S3BX
+ FF_16: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_14: FD1S3DX
+ FF_15: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_13: FD1P3DX
+ FF_14: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_12: FD1P3DX
+ FF_13: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_11: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_10: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_9: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_8: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_7: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_6: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_5: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_4: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_3: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_2: FD1P3DX
+ FF_3: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_1: FD1P3DX
+ FF_2: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_0: FD1P3DX
+ FF_1: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
+ FF_0: FD1S3DX
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
port map (CI=>co2_3, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3_1,
NC0=>iwcount_6, NC1=>open);
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_ctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
port map (CI=>co2_4, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_2,
NC0=>ircount_6, NC1=>open);
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con,
+ B1=>cnt_con_inv, CI=>co0_5, GE=>co1_5);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_5, GE=>co2_5);
+
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_5, GE=>af_d_c);
+
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
Empty <= empty_i;
Full <= full_i;
end Structure;
Starting process:
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Apr 17 11:33:43 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:32:54 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf 56
Circuit name : FIFO_36x64_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
EDIF output : FIFO_36x64_OutReg.edn
VHDL output : FIFO_36x64_OutReg.vhd
Bus notation : big endian
Report output : FIFO_36x64_OutReg.srp
Estimated Resource Usage:
- LUT : 60
+ LUT : 73
EBR : 1
- Reg : 23
+ Reg : 24
END SCUBA Module Synthesis
--- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.0
--- Fri Apr 17 11:33:43 2015
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.1
+-- Thu Sep 10 16:32:54 2015
-- parameterized module component declaration
component FIFO_36x64_OutReg
port (Data: in std_logic_vector(35 downto 0); Clock: in std_logic;
WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
Q: out std_logic_vector(35 downto 0); Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic; AlmostFull: out std_logic);
end component;
-- parameterized module component instance
__ : FIFO_36x64_OutReg
port map (Data(35 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
- Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__);
+ Reset=>__, Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostFull=>__);
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
set scuba "$Para(FPGAPath)/scuba"
-set modulename "FIFO_36x64_OutReg"
+set modulename "FIFO_36x32_OutReg"
set lang "vhdl"
set lpcfile "$Para(sbp_path)/$modulename.lpc"
set arch "ep5c00"
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
-set Para(ModuleName) "FIFO_36x64_OutReg"
+set Para(ModuleName) "FIFO_36x32_OutReg"
set Para(Module) "FIFO"
set Para(libname) latticeecp3
set Para(arch_name) ep5c00
-SCUBA, Version Diamond (64-bit) 3.4.0.80
-Fri Apr 17 11:33:43 2015
+SCUBA, Version Diamond (64-bit) 3.5.0.102
+Thu Sep 10 16:33:18 2015
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
-Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
+Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
- Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -outdata REGISTERED -no_enable -pe -1 -pf -1
- Circuit name : FIFO_36x64_OutReg
+ Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x32_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 5 -data_width 36 -num_words 32 -outdata REGISTERED -no_enable -pe -1 -pf 24
+ Circuit name : FIFO_36x32_OutReg
Module type : fifoblk
- Module Version : 5.0
+ Module Version : 5.1
Ports :
Inputs : Data[35:0], Clock, WrEn, RdEn, Reset
- Outputs : Q[35:0], Empty, Full
+ Outputs : Q[35:0], Empty, Full, AlmostFull
I/O buffer : not inserted
- EDIF output : FIFO_36x64_OutReg.edn
- VHDL output : FIFO_36x64_OutReg.vhd
- VHDL template : FIFO_36x64_OutReg_tmpl.vhd
- VHDL testbench : tb_FIFO_36x64_OutReg_tmpl.vhd
+ EDIF output : FIFO_36x32_OutReg.edn
+ VHDL output : FIFO_36x32_OutReg.vhd
+ VHDL template : FIFO_36x32_OutReg_tmpl.vhd
+ VHDL testbench : tb_FIFO_36x32_OutReg_tmpl.vhd
VHDL purpose : for synthesis and simulation
Bus notation : big endian
- Report output : FIFO_36x64_OutReg.srp
+ Report output : FIFO_36x32_OutReg.srp
Estimated Resource Usage:
- LUT : 60
+ LUT : 61
EBR : 1
- Reg : 23
+ Reg : 21
END SCUBA Module Synthesis
--- /dev/null
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.5.0.102
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component FIFO_36x128_DynThr_OutReg
+ port (Data : in std_logic_vector(35 downto 0);
+ Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(35 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostFull: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(35 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal AmFullThresh : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(35 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+ signal AlmostFull: std_logic;
+begin
+ u1 : FIFO_36x128_DynThr_OutReg
+ port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
+ Reset => Reset, AmFullThresh => AmFullThresh, Q => Q, Empty => Empty,
+ Full => Full, AlmostFull => AlmostFull
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ for i in 0 to 132 loop
+ wait until Clock'event and Clock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 132 loop
+ wait until Clock'event and Clock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 130 loop
+ wait until Clock'event and Clock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.5.0.102
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
port (Data : in std_logic_vector(35 downto 0);
Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
Reset: in std_logic; Q : out std_logic_vector(35 downto 0);
- Empty: out std_logic; Full: out std_logic
+ Empty: out std_logic; Full: out std_logic;
+ AlmostFull: out std_logic
);
end component;
signal Q : std_logic_vector(35 downto 0);
signal Empty: std_logic;
signal Full: std_logic;
+ signal AlmostFull: std_logic;
begin
u1 : FIFO_36x128_OutReg
port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
- Reset => Reset, Q => Q, Empty => Empty, Full => Full
+ Reset => Reset, Q => Q, Empty => Empty, Full => Full,
+ AlmostFull => AlmostFull
);
process
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.5.0.102
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
port (Data : in std_logic_vector(35 downto 0);
Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
Reset: in std_logic; Q : out std_logic_vector(35 downto 0);
- Empty: out std_logic; Full: out std_logic
+ Empty: out std_logic; Full: out std_logic;
+ AlmostFull: out std_logic
);
end component;
signal Q : std_logic_vector(35 downto 0);
signal Empty: std_logic;
signal Full: std_logic;
+ signal AlmostFull: std_logic;
begin
u1 : FIFO_36x32_OutReg
port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
- Reset => Reset, Q => Q, Empty => Empty, Full => Full
+ Reset => Reset, Q => Q, Empty => Empty, Full => Full,
+ AlmostFull => AlmostFull
);
process
--- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.5.0.102
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
port (Data : in std_logic_vector(35 downto 0);
Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic;
Reset: in std_logic; Q : out std_logic_vector(35 downto 0);
- Empty: out std_logic; Full: out std_logic
+ Empty: out std_logic; Full: out std_logic;
+ AlmostFull: out std_logic
);
end component;
signal Q : std_logic_vector(35 downto 0);
signal Empty: std_logic;
signal Full: std_logic;
+ signal AlmostFull: std_logic;
begin
u1 : FIFO_36x64_OutReg
port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn,
- Reset => Reset, Q => Q, Empty => Empty, Full => Full
+ Reset => Reset, Q => Q, Empty => Empty, Full => Full,
+ AlmostFull => AlmostFull
);
process
jspc29 / tdc.git / commitdiff