--- /dev/null
+\section{BLR Configuration}
+Setting of LVL1 triggers (PT1-PT3) made of an analog multiplicity signal
+from TOF+RPC in the CTS BLR board.
+The analog multiplicity signal is a negative signal with amlitude
+proportional to number of hits in the TOF and RPC detectors, so
+consequently proportional to number of detected charged particles.
+Selection of events with a certain minimum multiplicity allows to
+select events with specified region of centrality of the reaction.
+This is done in the discriminator, which gives a signal on output
+only for events with multiplicity signal larger than the selected
+threshold.
+Three different thresholds for cut on analog multiplicity signal from
+RPC+TOF can be set for three physics triggers PT1,PT2,PT3 on
+the cts trigger board ("baseline restorer board No.7").
+The thresholds are set via setting of first three channels of DAC
+Nr.0 on the board.
+The threshold values are set in the ascii file in hex form:
+\begin{verbatim}
+MAMBOnr DACnr address command value
+0 0 0 3 0x0A00 #thr. for PT1
+0 0 1 3 0x0B00 #thr. for PT2
+0 0 2 3 0x0C00 #thr. for PT3
+0 0 3 3 0x9200
+0 0 4 3 0x0000
+0 0 5 3 0x0000
+0 0 6 3 0x0000
+0 0 7 3 0x0000
+
+\end{verbatim}
+
+Only the first 12 bits of the input of the DAC (value in the previous example)
+take care, therefore 0x0A00 is 0x0A0 = 160 in decimal.
+Threshold value for the multiplicity outputs is set as: Vth = 4.5V*DAC/4096.
+The range of the DAC is 0 - 4096 i.e. 0 - FFF (12 bits), so the range
+of threshold Vth is 0 - 4500 mV.
+
+The threshold is connected to multiplicity cut in a following way:
+One particle in RPC or TOF produces amlitude of about 35 mV (averaged
+number, varies a little from various RPC sectors, also there is some
+difference for TOF and RPC).
+So e.g. M2 has amplitude about 70mV, and we set threshold 65 mV.
+For M30 we set 1V, etc.
+The saturation of the analog multiplicity signal is at about 3V,
+so the board allows to set threshold up to multiplicity 90.
+Table for threshold setting (from measurement up to NOV2010):
+
+\begin{verbatim}
+ multiplicity threshold DAC (hex) DAC (dec)
+ >=2 65mV 0x03c 60
+ >=3 100mV 0x05b 91
+ >=4 130mV 0x076 118
+ >=10 330mV 0x12c 300
+ >=15 500mV 0x1c7 455
+ >=30 1000mV 0x38d 909
+ >=60 2000mV 0x71c 1820
+\end{verbatim}
+Setting of thresholds:
+Now there is symbolic file used in the daq startup script:
+/var/diskless/etrax\_fs/cts/mult\_thresholds/ctsblr\_thresholds
+(on lxhadesdaq), and requested file with threshold setting
+(which is in the same directory) is linked to it:
+lrwxrwxrwx 1 hadaq hades 24 2010-11-12 17:23 ctsblr\_thresholds
+-> thresholds\_M2M3M60\_nov10
+All files with the board setting since SEP10 are in lxhadesdaq,
+directory /var/diskless/etrax\_fs/cts/mult\_thresholds
+for example thresholds\_M2M3M60\_nov10.
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--- /dev/null
+\section{Eventbuilder}
+\label{sec:instructionseb}
+\paragraph*{EB doesn't run, shared memory error in logfile}
+\begin{itemize}
+ \item Log in to the corresponding lxhadeb machine
+ \item goto /dev/shm
+ \item remove all netqueue* and daq* files
+ \item restart EB
+\end{itemize}
\paragraph*{If CTS monitor in Epics does not work}
\begin{verbatim}
ssh to scs@lxhadesdaq
-password is epics
+password is ??? (ask Burkhard)
-test for prrocesses:
+test for processes:
ps U scs
- PID TTY STAT TIME COMMAND
- 7728 pts/83 R+ 0:00 ps U scs
+ PID TTY STAT TIME COMMAND
+7728 pts/83 R+ 0:00 ps U scs
24174 ? S 0:00 sshd: scs@pts/83
25656 pts/83 Ss 0:00 -bash
30793 ? S 0:00 procServ 4813 ../../bin/linux-x86/trb st.cmd
30847 pts/88 S+ 0:00 caRepeater
-if only the procServ process is running but not its subprocess tribe
+if only the procServ process is running but not its subprocess trb
then telnet to procServ
-then ^R will restart the tribe IOC
-then quit the telnet session.
+then <CTRL>R will restart the trb IOC
+then <CTRL>]
+quit
+the telnet session.
to start from scratch:
cd EPICS/apps/trb/iocBoot/ioclxhadesdaq/
procServ 4813 ../../bin/linux-x86/trb st.cmd
-to check:
+to check (only on lxhadesdaq):
telnet localhost 4813
<CR> ==> you should see epics> prompt.
dbl ==> gives you list of PVs.
-^] to get back to the telnet prompt
+<CTRL>] to get back to the telnet prompt
then
quit
-test for prrocesses:
-ps U scs
- PID TTY STAT TIME COMMAND
- 7728 pts/83 R+ 0:00 ps U scs
-24174 ? S 0:00 sshd: scs@pts/83
-25656 pts/83 Ss 0:00 -bash
-30793 ? S 0:00 procServ 4813 ../../bin/linux-x86/trb st.cmd
-30800 pts/88 Ssl+ 0:02 ../../bin/linux-x86/trb st.cmd
-30847 pts/88 S+ 0:00 caRepeater
-
-if only the procServ process is running but not its subprocess trb:
-
-telnet to procServ
-^R will restart the tribe IOC
-^]
-quit
- the telnet session.
\end{verbatim}
-\section{Messages in Logger Window}
\ No newline at end of file
+\section{Messages in Logger Window}
+\subsection{Eventbuilder}
+\paragraph*{NETMEM-? <E> netmem.c, 685: ShmTrans\_open: failed to open shmem segment...}~\\
+There is a problem with shared memories between netmem and eventbuilder. See~\ref{sec:instructionseb}.
+
+\paragraph*{NETMEM-? <E> queue fill level exceeded 95\%}~\\
+A data buffer is full. Restart EB. If problem still exists: one data source is missing (Check with scan\_ports.pl)
+
+\paragraph*{EVTBLD-? <W> discarded events: 12}~\\
+The eventbuilder discarded some events. If rate is low (< 10 per second): ignore. Otherwise: Check if server is
+busy with some other task or restart EB.
+
+\paragraph*{daq\_netmem<W>[N]: UDP receive buffer length smaller than requested buffer length}~\\
+The system sets a maximum fo UDP buffer sizes lower than our usual sizes. This should be corrected automatically by default.
+Run \\\verb!sysctl -w net.core.rmem_max=10485760! and restart eventbuilders.
+
+\subsection{StatWatch}
+logerrors.pl is started within the daq start-up script. It should not give messages during DAQ start-up and shortly after.
+If there are any: ignore them. Messages are sent every 30 seconds and should give a summary of the last 30 seconds.
+
+\paragraph*{StatWatch <N> \$n board complain: timing trigger input error: \$addr\\
+ StatWatch <E> N boards complain: timing trigger missing / spike / multiple}~\\
+The named board saw a problem on the reference time input. May happen from time to time. If a boards constantly complains:
+Trigger cable to board has to be checked.
+
+\paragraph*{StatWatch <N> \$n board complain: frontend error}~\\
+A front-end failed. MDC: token not return from motherboard. If a board complains constantly: reconfigure / reboot. If nothing
+helps: exchange board.
+
+\paragraph*{StatWatch <E> N boards complain: missing CMS}~\\
+The common stop signal for MDC showed a problem. One-time message: ignore. Repeated every 30 seconds: restart DAQ, check CMS cables.
+
+\paragraph*{StatWatch <E> N boards complain: spike on CMS}~\\
+The common stop signal for MDC showed a short spike. One-time message: ignore. Repeated every 30 seconds: restart DAQ, check CMS cables, correlate to HV.
+
+\paragraph*{StatWatch <E> N boards complain: frontend error}~\\
+A front-end module failed. In most cases this is corrected automatically. If message is repeated, restart DAQ, make power cycle, check hardware.
+
+\paragraph*{StatWatch <E> N boards complain: frontend not configured}~\\
+A front-end module is not configured correctly. If a board from RICH complains (address 0x3000 - 0x3054), run RichInitADCM from DAQ Expert Tools.
+In all other cases or if RICH still has errors: restart DAQ.
+
+
+\paragraph*{StatWatch <E> N boards complain: Event not found~\\
+ StatWatch <E> N boards complain: LVL1 counter mismatch~\\
+ StatWatch <E> N boards complain: IPU counter mismatch~\\
+ StatWatch <E> N boards complain: Severe data buffer problem}~\\
+Serious problem in data buffers. Restart DAQ.
+
+\paragraph*{StatWatch <E> N boards complain: Data missing~\\
+ StatWatch <E> N boards complain: broken event}~\\
+A front-end experienced a problem with a data buffer. If message is repeated, restart DAQ.
+
\input{mdcinstructions}
\input{showerinstructions}
\input{richinstructions}
+\input{blrconfig}
\input{epics}
+\input{ebinstructions}
\clearpage
\bibliography{biblio}
D100 - D13F & SPI Data Mem. & see section SPI Flash \\
D200 & Flash select & select Flash ROM image \\
E000 & TDC Readback Fifo & Fifo for readback values from TDC \\
+E401 - E403 & I/O Debug & Registers to read / set I/O to MBO \\
\hline
\end{tabularx}
\caption{Memory map for MDC OEP}
\item[0x9008: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
\end{description}
-% STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_fifo_almost_full(addr));
-% STATISTICS_READY_OUT <= '1';
-% STATISTICS_UNKNOWN_OUT <= '0';
-% elsif addr >= 16 and addr <= 21 then
-% case addr is
-% when 16 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_almost_full);
-% when 17 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_idle);
-% when 18 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_lvl1_working);
-% when 19 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_idle);
-% when 20 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_working);
-% when 21 => STATISTICS_DATA_OUT <= x"00" & std_logic_vector(timer_ipu_waiting);
-% end case;
+\subsubsection{MDC OEP I/O Control Register}
+\begin{description}
+ \item[0xE401: Override Control] Control register to select between normal, internal control of the I/O lines to the MBO or external control via slow-control.
+ \begin{description}
+ \item[Bit 0] Enable control of JTAG lines (currently not implemented)
+ \item[Bit 1] Enable control of Mode lines to the MBO]
+ \item[Bit 2] Enable control of data/address bus including DST and AOD line
+ \end{description}
+ \item[0xE402] Control and read-back of mode and JTAG lines. Bits 3 -- 1 are copied to the corresponding outputs if 0xE401 Bit 0 is set. Bits 21 -- 16 are connected to the mode lines of the MBO if Bit 1 of 0xE401 is set. A read always shows the current status of the signals.
+ \begin{description}
+ \item[Bit 0] JTAG TDO
+ \item[Bit 1] JTAG TDI
+ \item[Bit 2] JTAG TMS
+ \item[Bit 3] JTAG TCK
+ \item[Bit 16] GDE
+ \item[Bit 17] MOD
+ \item[Bit 18] RDM
+ \item[Bit 19] RES
+ \item[Bit 20] TOK
+ \item[Bit 21] WRM
+ \end{description}
+
+ \item[0xE403] Control and read-back of data/address bus. Bits 16 -- 0 are copied to the data bus if Bit 20 of this register and 0xE401 Bit 2 are set. If Bit 20 is not set, outputs are tri-stated.
+ \begin{description}
+ \item[Bit 8 -- 0] ADD lines
+ \item[Bit 12] AOD
+ \item[Bit 16] DST
+ \item[Bit 20] override enable / tri-state off
+ \item[Bit 24] output enable (from internal logic)
+ \item[Bit 28] RESERVE input
+ \end{description}
+\end{description}
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{l|X|X}
+\hline
+\textbf{Name} & \textbf{short MBO} & \textbf{long MBO}\\
+\hline
+\hline
+TDC Reg. 0 (Mode 0) & $A001 + 2 \times \textrm{TDC}$ & $A061 + 2 \times \textrm{TDC}$ \\
+TDC Reg. 1 (Mode 1) & $A011 + 2 \times \textrm{TDC}$ & $A079 + 2 \times \textrm{TDC}$ \\
+TDC Reg. 2 (Cal. Mask) & $A021 + 2 \times \textrm{TDC}$ & $A091 + 2 \times \textrm{TDC}$ \\
+TDC Reg. 3 (Inp. Mask) & $A031 + 2 \times \textrm{TDC}$ & $A0A9 + 2 \times \textrm{TDC}$ \\
+Thresholds & $A049 + 2 \times \textrm{DBO}$ & $A0CD + 2 \times \textrm{DBO}$ \\
+\hline
+\end{tabularx}
+\caption[MDC MBO Configuration]{The MDC Motherboards can be configured by several registers in each TDC and the on-board DAC. The position in the internal memory depends on the type of motherboard (short or long). The variables DBO and TDC have to be replaced with the corresponding DBO or TDC number, respectively. Note that both are counted from 0. Addresses in the range above 0xA000 not listed must not be written since they contain essential control information.}
+\label{tab:MdcMboConfiguration}
+\end{center}
+\end{table}
+\clearpage
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Hardware}
\label{fig:mdcpowercycle}
\end{figure}
-Afterwards, the correct FPGA design needs to be loaded to the OEP. This is done with the commands
-\\\verb!daqop set flash 1 oep; daqop reboot oep!
-\\After 10 seconds all OEP are rebooted and DAQ might be started again. If rebooting of the OEP fails,
-first run a DAQ start-up until the script complains ``OEP design too old''. Answer with ``No'' and start again
-with the command above.
\ No newline at end of file
+Afterwards, the correct FPGA design needs to be loaded to the OEP. Click the ``MdcRebootOEP'' button available in the ``DAQ Expert Tools''
+After 10 seconds all OEP are rebooted and DAQ can be started again. If rebooting of the OEP fails,
+first run a DAQ start-up until the script complains ``OEP design too old''. Close the window and try rebooting OEP again.
+
+When beam is in the cave the procedure can fail\footnote{Beam causes heavy noise in the cave. The OEP code loaded after power-cycle is not able to correct data transmission errors - only after reboot the network can operator without problems.}. In this case, switch off beam in the cave until OEP are rebooted. There is a switch in the counting room to remove beam for a short while - no need to call operators.
\ No newline at end of file
8200 & Start/Veto TRB & -- \\
8300 & RPC TRB & -- \\
8800 & Other TRB & -- \\
+9000 & TRB3 central FPGA & 0xFE40 \\
+9100 & TRB3 peripheral FPGA (all) & 0xFE45\\
+9101 & TRB3 peripheral FPGA 1& 0xFE41\\
+9102 & TRB3 peripheral FPGA 2& 0xFE42\\
+9103 & TRB3 peripheral FPGA 3& 0xFE43\\
+9104 & TRB3 peripheral FPGA 4& 0xFE44\\
\hline
\end{tabularx}
\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value
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