The physics trigger seems to be working now. All data from frame generator is read

diff --git a/mupix/sources/EventBuffer.vhd b/mupix/sources/EventBuffer.vhd
index 5bc51ffa17ae55104d9d7841a261bbe8e26b2d8a..99d766625156804a6a003db755c63384564091da 100644 (file)
--- a/mupix/sources/EventBuffer.vhd
+++ b/mupix/sources/EventBuffer.vhd
@@ -77,25 +77,40 @@ architecture behavioral of eventbuffer is
   signal fifo_read_f_fsm : fifo_read_f_states := idle;
   signal fifo_read_f : std_logic := '0';
   signal fifo_read_busy_f : std_logic := '0';
-  signal fifo_read_done_f : std_logic := '0';
-  
+
+  component fifo is
+    generic (
+      addr_wd : integer;
+      word_wd : integer);
+    port (
+      Din     : in  std_logic_vector (word_wd - 1 downto 0);
+      Wr      : in  std_logic;
+      Dout    : out std_logic_vector (word_wd - 1 downto 0);
+      Rd      : in  std_logic;
+      Empty   : out std_logic;
+      Full    : out std_logic;
+      WrCnt_o : out std_logic_vector(addr_wd - 1 downto 0);
+      Reset   : in  std_logic;
+      CLK     : in  std_logic);
+  end component fifo;
 
 begin  -- behavioral
 
-  -- send data to fifo 
-  fifo_32_data_1 : fifo_32_data
+  fifo_1: entity work.fifo
+    generic map (
+      addr_wd => 11,
+      word_wd => 32)
     port map (
-      data  => fifo_data_in,            --data in
-      clock => clk,
-      wren  => fifo_write,
-      rden  => fifo_read_enable,
-      reset => fifo_reset,
-      q     => fifo_data_out,           --data out
-      wcnt  => fifo_write_ctr,
-      empty => fifo_empty,
-      full  => fifo_full
-      );
-
+      Din     => fifo_data_in,
+      Wr      => fifo_write,
+      Dout    => fifo_data_out,
+      Rd      => fifo_read_enable,
+      Empty   => fifo_empty,
+      Full    => fifo_full,
+      WrCnt_o => fifo_write_ctr,
+      Reset   => fifo_reset,
+      CLK     => clk);
+  
   fifo_read_enable <= fifo_read_s or fifo_read_f;
   fifo_reset <= clear_buffer_in;
 
@@ -119,7 +134,6 @@ begin  -- behavioral
     wait until rising_edge(clk);
     fifo_read_f <= '0';
     fifo_read_busy_f <= '0';
-    fifo_read_done_f <= '0';
     fee_data_int <= (others => '0');
     fee_data_write_int <= '0';
     fee_data_finished_int <= '0';

diff --git a/mupix/sources/TriggerHandler.vhd b/mupix/sources/TriggerHandler.vhd
index 8d76532c8d8815e114ae5cbf44a0b645158adb1d..7fd873387be137a22c67ed1583875428a76b05e8 100644 (file)
--- a/mupix/sources/TriggerHandler.vhd
+++ b/mupix/sources/TriggerHandler.vhd
@@ -128,6 +128,9 @@ architecture behavioral of TriggerHandler is
 
   signal trigger_handler_fsm : trigger_handler_type := idle;
   signal trigger_type        : trigger_type_type    := t_unknown;
+  signal wr_header_int : std_logic := '0';
+  signal wr_data_int : std_logic := '0';
+  signal wr_status_int : std_logic := '0';
   
 begin
   
@@ -151,7 +154,6 @@ begin
     timing_trigger_int      <= '0';
     status_trigger_int      <= '0';
     flush_buffer_int        <= '0';
-    fee_data_write_int      <= '0';
     fee_data_finished_int   <= '0';
     fee_trg_release_int     <= '0';
     fee_trg_statusbit_int   <= (others => '0');
@@ -159,6 +161,9 @@ begin
     trigger_busy_int        <= '1';
     fast_clear_int          <= '0';
     fee_trg_release_int     <= '0';
+    wr_header_int           <= '0';
+    wr_data_int             <= '0';
+    wr_status_int           <= '0';
     if LVL1_INVALID_TRG_IN = '1' or reset_trigger_state_edge = "01" then
       fast_clear_int      <= '1';
       fee_trg_release_int <= '1';
@@ -169,9 +174,11 @@ begin
           trigger_busy_int        <= '0';
           trigger_handler_state <= x"01";
           if LVL1_VALID_TIMING_TRG_IN = '1' then
+              wr_header_int <= '1';
               trigger_type <= t_timing;
               trigger_handler_fsm <= timing_trigger;
           elsif(LVL1_VALID_NOTIMING_TRG_IN = '1') then
+            wr_header_int <= '1';
             trigger_handler_fsm <= check_trigger_type;
           end if;
           
@@ -215,8 +222,7 @@ begin
 
         when status_trigger => --dummy implementation
           trigger_handler_state <= x"06";
-          fee_data_int <= x"deadbeef";
-          fee_data_write_int <= '1';
+          wr_status_int <= '1';
           trigger_handler_fsm <= wait_trigger_data_valid_b;
           
         when write_data_to_eventbuffer =>
@@ -230,11 +236,11 @@ begin
 
         when write_data_to_ipu =>
           trigger_handler_state <= x"0A";
+          wr_data_int <= '1';
           if fifo_readout_end_int = "10" then
+            wr_data_int <= '0';
             trigger_handler_fsm <= wait_trigger_data_valid_a;
           else
-            fee_data_int       <= FEE_DATA_0_IN;
-            fee_data_write_int <= FEE_DATA_WRITE_0_IN;
             trigger_handler_fsm <= write_data_to_ipu;
           end if;
 
@@ -268,6 +274,29 @@ begin
     end if;
   end process trigger_handler_proc;
 
+  ------------------------------------------------------------
+  --Data Output Mux
+  ------------------------------------------------------------
+  Data_Out_Mux: process (clk_in) is
+  begin  -- process Data_Out_Mux
+    if rising_edge(clk_in) then
+      if wr_header_int = '1' then
+        fee_data_write_int <= '1';--header see Hades DAQ user guide
+        fee_data_int <= "001" & "0" & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN;
+      elsif wr_data_int = '1' then
+        fee_data_write_int <= FEE_DATA_WRITE_0_IN;
+        fee_data_int <= FEE_DATA_0_IN;
+      elsif wr_status_int = '1' then
+         fee_data_int <= x"deadbeef";
+         fee_data_write_int <= '1';
+      else
+        fee_data_write_int <= '0';
+        fee_data_int <= (others => '1');
+      end if;
+    end if;
+  end process Data_Out_Mux;
+
+  
   ------------------------------------------------------------
   --Trigger statistics
   ------------------------------------------------------------