-\subsubsection{Hardware Information}
+\subsection{Hardware Information}
\begin{itemize*}
\item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/trbv3_SCHEMATIC_michael.pdf}{trbv3\_SCHEMATIC\_michael.pdf}
\item Pin-out file for the peripheral FPGAs \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph.lpf}{cvsroot/trb3/base/trb3\_periph.lpf}
-\subsubsection{Board Identification}
+\subsection{Board Identification}
\label{Trb3BoardID}
The TRB3 boards are equipped with 5 temperature sensors, one for each FPGA. They contain a unique ID that is used to identify each FPGA. Additionally, the peripheral FPGAs have to bits identification (endpoint ID) corresponding to their position on the board.
This information can be read out after the first initial programming of the FPGAs.
The first three digits of the SID is the serial number as written on the board, the fourth digit is an identifier for the FPGA number as printed on the PCB (central FPGA is FPGA 5, the others are numbered 1 to 4, but mapped to 0 to 3 in the file). Based on this file, a second file \filename{addresses.db} can be written for each individual set-up to assign each board the necessary network addresses.
-\subsubsection{Flash Programming}
+\subsection{Flash Programming}
Typically only the first programming of a board is done with a JTAG cable, all later upgrades can be done directly via TrbNet to the Flash ROMs. The advantage is the increased speed (about a factor 10) and that no physical access to the board is necessary. The software needs some settings in the FPGA code to function properly:
First, the name of the design has to contain a certain sub-string:
Second, the upper 16 Bit of the Hardware Version register as described below is checked.
-\subsubsection{Design Identification}
+\subsection{Design Identification}
The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules: The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and have to contain one of the following values:
\begin{description*}
\item[9000] design is for the central FPGA
Software versions can be stored in the generic \signal{Regio\_Compile\_Version} (register 0x41).
-\subsubsection{Network Addresses}
+\subsection{Network Addresses}
All boards of a given type are accessible by a broadcast address at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint:
\begin{itemize*}
\item 0x40 for the central FPGA
\subsection{FPGA I/O Performance}
\clearpage
\section{TRB3 Platform}
- \subsection{General Remarks}
- \input{Trb3GeneralRemarks}
\subsection{Known Bugs and Limitations}
\input{Trb3KnownBugs}
\subsection{Clock and Trigger Distribution}
\cleardoublepage
\part{Design Components}
- \input{DesignComponents}
+ \section{General Remarks}
+ \input{Trb3GeneralRemarks}
\clearpage
\section{TDC}
\subsection{Building Blocks}
\cleardoublepage
\part{Synchronous TrbNet}
- \section{Clock Measurements}
\section{Media Interfaces}
\input{SyncMediaInterface}
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-\part{Quick Start}
+\part{Software Quick Start}
\lstset{
% basicstyle=\small
morecomment=[l][\ttfamily]{\#!},
}
-\begin{abstract}
-This Quick Start manual describes way how to quickly run your TRB3. Is written
-in easy way that every, even not advanced in Linux systems users should be
-able to run his own TRB3. After successful passing this manual we recommend your
-to read man documentation for TRB3 which is much more detailed.
-\end{abstract}
+This section is supposed to give a quick overview of the steps to take to get a running TRB3 set-up. It includes installing software and configuring your PC with all necessary settings.
+
+Note that most set-ups use a openSUSE 64 Bit installation - on other distributions things are likely to differ in more or less subtle ways...
\input{trb3qs_suse}
\input{trb3qs_software}