Minor simulation changes

diff --git a/ADC/sim/adcprocessor_cfd.mpf b/ADC/sim/adcprocessor_cfd.mpf
index 91f8fc66485b60982f05a2d997ccb845d959ed3b..8da2da468df4c1fb33d4d0f998c883d57ea3499c 100644 (file)
--- a/ADC/sim/adcprocessor_cfd.mpf
+++ b/ADC/sim/adcprocessor_cfd.mpf
@@ -1793,7 +1793,7 @@ Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_24 = ../source/adc_package.vhd
 Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1429549883 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_25 = /home/aneiser/trb3/ADC/sim/tb_adcprocessor_cfd.vhd
-Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1429624870 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1429626290 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

diff --git a/ADC/sim/tb_adcprocessor_cfd.vhd b/ADC/sim/tb_adcprocessor_cfd.vhd
index 582a371160da5c7e1a24546f52b418b70b5fdd82..80914fa2c9ded6fea45af7c3d2d28c6a2c4a149b 100644 (file)
--- a/ADC/sim/tb_adcprocessor_cfd.vhd
+++ b/ADC/sim/tb_adcprocessor_cfd.vhd
@@ -34,14 +34,14 @@ begin
   config.BaselineAlwaysOn <= '1', '0' after 20 us;
 
   config.InputThreshold  <= to_unsigned(32, 10);
-  config.BaselineAverage <= to_unsigned(4, 5);
+  config.BaselineAverage <= to_unsigned(6, 5);
   config.PolarityInvert  <= '1';
 
-  config.CFDDelay <= to_unsigned(0, 5);
+  config.CFDDelay <= to_unsigned(2, 5);
   config.CFDMult <= to_unsigned(2, 4);
   config.CFDMultDly <= to_unsigned(3, 4);
 
-  config.IntegrateWindow <= to_unsigned(64, 8);
+  config.IntegrateWindow <= to_unsigned(128, 8);
    
   config.CheckWord1       <= (others => '0');
   config.CheckWord2       <= (others => '0');
@@ -69,7 +69,7 @@ begin
   begin
     readout_rx.data_valid       <= '0';
     readout_rx.valid_timing_trg <= '0';
-    wait for 13740 ns;
+    wait for 40740 ns;
     wait until rising_edge(clock100);
     wait for 0.5 ns;
     readout_rx.valid_timing_trg <= '1';