add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test_random.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rng_trivium.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
DEBUG_OUT => debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
);
- THE_FWD_TEST: entity fwd_test
+ THE_FWD_TEST: entity fwd_test_random
port map(
CLK => clk_sys,
RESET => reset_i,
--
FWD_ENABLE_IN => additional_reg(31),
FWD_DELAY_IN => control_reg(31 downto 16),
- FWD_SIZE_IN => control_reg(15 downto 0),
+-- FWD_SIZE_IN => control_reg(15 downto 0),
FWD_START_IN => tick_int,
FWD_BUSY_OUT => fwd_busy_int, --open
--