--- /dev/null
+*~
+*.tcl
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+workdir
+workdir_*
+*.bit
+*.kate-swp*
+*.kate-swap*
+.run_manager.ini
+reportview.xml
+.kateproject.d
+*/project/
+*/project2/
+modelsim.ini
+*.mti
+*.bak
+work
+*.wlf
+*stacktrace.txt
+*edn
+licbug.txt
+old
+config_compile.pl
+._Real_._Math_.vhd
+diamond
--- /dev/null
+{
+ "name": "LogicBox"
+, "files": [ { "git": 1 } ]
+}
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+Familyname => 'MachXO3LF',
+Devicename => 'LCMXO3LF-2100E',
+Package => 'WLCSP49',
+Speedgrade => '5',
+
+TOPNAME => "logicbox",
+lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
+synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="LogicBox" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="LogicBox">
+ <Options/>
+ <Implementation title="LogicBox" dir="LogicBox" description="LogicBox" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="logicbox"/>
+ <Source name="logicbox.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="logicbox"/>
+ </Source>
+ <Source name="LogicBox.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="LogicBox1.sty"/>
+</BaliProject>
--- /dev/null
+#-- Synopsys, Inc.
+#-- Version J-2015.03L-SP1
+#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt
+
+#project files
+
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../padiwa/source/uart_sctrl.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "logicbox.vhd"
+
+
+
+#implementation: "LogicBox"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+
+#device options
+set_option -technology MACHXO3LF
+set_option -part LCMXO3LF_2100E
+set_option -package UWG49CTR
+set_option -speed_grade -5
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "logicbox"
+
+# mapper_options
+set_option -frequency 1
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/logicbox.edf"
+
+#set log file
+set_option log_file "workdir/logicbox.srf"
+impl -active "workdir"
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library machxo3lf;\r
+use machxo3lf.all;\r
+\r
+\r
+entity logicbox is\r
+ port(\r
+ CLK : in std_logic;\r
+ \r
+ INPUT : in std_logic_vector(3 downto 0);\r
+ OUTPUT : out std_logic_vector(3 downto 0);\r
+ \r
+ LED : inout std_logic_vector(3 downto 0);\r
+ \r
+ STATUSI : in std_logic;\r
+ STATUSO : in std_logic;\r
+ CONTROLI : out std_logic;\r
+ CONTROLO : out std_logic;\r
+ \r
+ RX_OUT : out std_logic;\r
+ TX_IN : in std_logic;\r
+ CBUS : in std_logic\r
+ );\r
+end entity;\r
+\r
+architecture arch of logicbox is\r
+ signal clk_i, clk_osc : std_logic;\r
+ signal led_i : std_logic_vector(3 downto 0);\r
+ signal timer_i : unsigned(23 downto 0) := (others => '0');\r
+ signal config : std_logic_vector(3 downto 0);\r
+ \r
+ signal uart_rx_data : std_logic_vector(31 downto 0);\r
+ signal uart_tx_data : std_logic_vector(31 downto 0);\r
+ signal uart_addr : std_logic_vector(7 downto 0);\r
+ signal bus_read : std_logic := '0';\r
+ signal bus_write : std_logic := '0';\r
+ signal bus_ready : std_logic; \r
+ \r
+ component OSCH\r
+ generic (NOM_FREQ: string := "133.00");\r
+ port (\r
+ STDBY :IN std_logic;\r
+ OSC :OUT std_logic;\r
+ SEDSTDBY :OUT std_logic\r
+ );\r
+ end component; \r
+ \r
+begin\r
+\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- I don't care what you do, as long as you do it!\r
+---------------------------------------------------------------------------\r
+\r
+-- RX_OUT <= TX_IN when rising_edge(clk_i);\r
+OUTPUT <= INPUT xor (STATUSI & STATUSO & CBUS & CBUS);\r
+led_i <= INPUT when rising_edge(clk_i);\r
+\r
+bus_ready <= bus_read or bus_write; \r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock\r
+---------------------------------------------------------------------------\r
+clk_source: OSCH\r
+ generic map ( NOM_FREQ => "33.25" )\r
+ port map (\r
+ STDBY => '0',\r
+ OSC => clk_osc,\r
+ SEDSTDBY => open\r
+ );\r
+clk_i <= clk_osc;\r
+\r
+timer_i <= timer_i + 1 when rising_edge(clk_i);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Read configuration switch\r
+---------------------------------------------------------------------------\r
+process begin\r
+ wait until rising_edge(clk_i);\r
+ if timer_i(23 downto 4) = 0 then\r
+ if timer_i(3 downto 0) = x"0" then\r
+ LED <= (others => 'Z');\r
+ elsif timer_i(3 downto 0) = x"8" then\r
+ config <= LED;\r
+ end if;\r
+ else\r
+ LED <= led_i;\r
+ end if;\r
+end process; \r
+\r
+---------------------------------------------------------------------------\r
+-- UART\r
+---------------------------------------------------------------------------\r
+THE_UART : entity work.uart_sctrl\r
+ generic map(\r
+ CLOCK_SPEED => 33250000\r
+ )\r
+ port map(\r
+ CLK => clk_i,\r
+ RESET => '0',\r
+ UART_RX => TX_IN,\r
+ UART_TX => RX_OUT,\r
+ \r
+ DATA_OUT => uart_rx_data,\r
+ DATA_IN => uart_tx_data,\r
+ ADDR_OUT => uart_addr, \r
+ WRITE_OUT => bus_write,\r
+ READ_OUT => bus_read,\r
+ READY_IN => bus_ready,\r
+ \r
+ DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- UART\r
+---------------------------------------------------------------------------\r
+\r
+\r
+end architecture;\r
+\r
+ \r
+
\ No newline at end of file
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 24
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+SYSCONFIG MCCLK_FREQ=33.25 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE ;
+LOCATE COMP "OUTPUT[2]" SITE "A6" ;
+LOCATE COMP "OUTPUT[3]" SITE "C5" ;
+LOCATE COMP "OUTPUT[0]" SITE "B4" ;
+LOCATE COMP "OUTPUT[1]" SITE "B5" ;
+LOCATE COMP "CONTROLI" SITE "B1" ;
+LOCATE COMP "CONTROLO" SITE "A1" ;
+LOCATE COMP "LED[0]" SITE "A7" ;
+LOCATE COMP "LED[1]" SITE "E5" ;
+LOCATE COMP "LED[2]" SITE "C1" ;
+LOCATE COMP "LED[3]" SITE "D2" ;
+LOCATE COMP "INPUT[0]" SITE "F7" ;
+LOCATE COMP "INPUT[2]" SITE "G7" ;
+LOCATE COMP "INPUT[3]" SITE "F4" ;
+LOCATE COMP "INPUT[1]" SITE "F3" ;
+LOCATE COMP "RX_OUT" SITE "F1" ;
+LOCATE COMP "TX_IN" SITE "C4" ;
+LOCATE COMP "CBUS" SITE "C3" ;
+LOCATE COMP "CLK" SITE "G4" ;
+LOCATE COMP "STATUSO" SITE "G2" ;
+LOCATE COMP "STATUSI" SITE "G1" ;
+IOBUF PORT "INPUT[0]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[1]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[2]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[3]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "CONTROLI" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CONTROLO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED[0]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[1]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[2]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[3]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "OUTPUT[0]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[1]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[2]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "OUTPUT[3]" IO_TYPE=LVTTL33 SLEWRATE=FAST DRIVE=16 ;
+IOBUF PORT "RX_OUT" IO_TYPE=LVTTL33 ;
+IOBUF PORT "TX_IN" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CLK" IO_TYPE=LVDS25 ;
+IOBUF PORT "STATUSO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 ;
+BANK 0 VCCIO 3.3 V;
+BANK 5 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+
+
+FREQUENCY PORT CLK 100 MHz;
+FREQUENCY NET clk_osc 33.25 MHz;
\ No newline at end of file
jspc29 / logicbox.git / commitdiff