debugging the link state

diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj
index dafb69d176825bcc2b1a2235031b54e9c6641e5c..154d721c335433d447de13eb0db1ae69d8746363 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.prj
+++ b/gbe_hub/trb3sc_gbe_hub.prj
@@ -190,6 +190,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_inserter.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_remover.vhd"
 
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/parser.vhd"
+
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd"

diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd
index 94a9900237563c037851da3cbc12e6d2722a4706..99ee3b4866fcd7185407a69d12c08128be8833dd 100644 (file)
--- a/gbe_hub/trb3sc_gbe_hub.vhd
+++ b/gbe_hub/trb3sc_gbe_hub.vhd
@@ -184,7 +184,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
   signal pcs_an_ready               : std_logic;
   signal link_active                : std_logic;
   
-  signal debug                      : std_logic_vector(31 downto 0);
+  signal debug                      : std_logic_vector(127 downto 0);
 
   signal sniffer_data               : std_logic_vector(7 downto 0); -- SCTRL endpoint
   signal sniffer_wr                 : std_logic;
@@ -207,8 +207,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is
 
   signal dlm_tag_ctr                : unsigned(7 downto 0);
   signal inc_dlm_tag                : std_logic;
-  
-
+    
 begin
 
 -- SerDes usage: 
@@ -253,6 +252,17 @@ begin
     LED_GREEN_OUT     => LED_RJ_GREEN(1)
   );
 
+  HDR_IO(1)  <= clear_n_i;
+  HDR_IO(2)  <= reset_n_i;
+  HDR_IO(3)  <= tx_pll_lol_d_i;
+  HDR_IO(4)  <= link_tx_ready_i;
+  HDR_IO(5)  <= '0';
+  HDR_IO(6)  <= '0';
+  HDR_IO(7)  <= '0';
+  HDR_IO(8)  <= '0';
+  HDR_IO(9)  <= '0';  
+  HDR_IO(10) <= clk_sys;
+  
 ---------------------------------------------------------------------------
 -- DLM timing generator
 ---------------------------------------------------------------------------
@@ -285,7 +295,7 @@ begin
 
   dlm_inject_int  <= rst_dlm_ctr;
   dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr);
-  
+    
 ---------------------------------------------------------------------------
 -- FiFo controller
 ---------------------------------------------------------------------------
@@ -361,20 +371,24 @@ begin
   -- 8 : fifo_eof
   -- 7..0: data
   
-  DBG(3 downto 0)   <= dl_rx_port_mux;
-  DBG(11 downto 4)  <= ul_rx_data(7 downto 0);
-  DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0);
-  DBG(20)           <= ul_rx_frame_avail;
-  DBG(21)           <= ul_rx_frame_req;
-  DBG(22)           <= ul_rx_frame_ack;
-  DBG(23)           <= dl_rx_data(0)(9);
-  DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0);
-  DBG(28)           <= ul_rx_data(8);
-  DBG(29)           <= ul_rx_data(9);
-  DBG(30)           <= ul_rx_data(10);
-  DBG(31)           <= ul_rx_fifofull;
-  DBG(32)           <= dl_rx_data(0)(8);
+  DBG(31 downto 0)  <= debug(31 downto 0);
+  DBG(32)           <= '0';
   DBG(33)           <= clk_sys;
+  
+--  DBG(3 downto 0)   <= dl_rx_port_mux;
+--  DBG(11 downto 4)  <= ul_rx_data(7 downto 0);
+--  DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0);
+--  DBG(20)           <= ul_rx_frame_avail;
+--  DBG(21)           <= ul_rx_frame_req;
+--  DBG(22)           <= ul_rx_frame_ack;
+--  DBG(23)           <= dl_rx_data(0)(9);
+--  DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0);
+--  DBG(28)           <= ul_rx_data(8);
+--  DBG(29)           <= ul_rx_data(9);
+--  DBG(30)           <= ul_rx_data(10);
+--  DBG(31)           <= ul_rx_fifofull;
+--  DBG(32)           <= dl_rx_data(0)(8);
+--  DBG(33)           <= clk_sys;
 
 ---------------------------------------------------------------------------
 -- GbE wrapper without med interface
@@ -425,10 +439,9 @@ begin
       GSC_BUSY_IN              => gsc_busy,            
       -- reset
       MAKE_RESET_OUT           => reset_via_gbe,
-      -- debug  signal aux_reg                    : std_logic_vector(31 downto 0);
-
+      -- debug
       STATUS_OUT               => status,
-      DEBUG_OUT                => debug
+      DEBUG_OUT                => open
     );
   
 -------------------------------------------------------------------------------
@@ -604,8 +617,8 @@ begin
     LINK_ACTIVE_OUT(0)          => open, -- for internal SCTRL
     TICK_MS_IN                  => tick_ms_int,
     -- DLM
-    DLM_INJECT_IN               => (others => '0'),
-    DLM_DATA_IN                 => (others => '0'),
+    DLM_INJECT_IN(0)            => dlm_inject_int,
+    DLM_DATA_IN(7 downto 0)     => dlm_tx_data_int,
     DLM_FOUND_OUT               => open,
     DLM_DATA_OUT                => open,
     DLM_CLK_OUT                 => open,
@@ -703,8 +716,14 @@ begin
     TX_LINK_READY_IN            => link_tx_ready_i,
     TICK_MS_IN                  => tick_ms_int,
     -- DLM
-    DLM_INJECT_IN               => (others => '0'),
-    DLM_DATA_IN                 => (others => '0'),
+    DLM_INJECT_IN(0)            => dlm_inject_int,
+    DLM_INJECT_IN(1)            => dlm_inject_int,
+    DLM_INJECT_IN(2)            => dlm_inject_int,
+    DLM_INJECT_IN(3)            => dlm_inject_int,
+    DLM_DATA_IN(7 downto 0)     => dlm_tx_data_int,
+    DLM_DATA_IN(15 downto 8)    => dlm_tx_data_int,
+    DLM_DATA_IN(23 downto 16)   => dlm_tx_data_int,
+    DLM_DATA_IN(31 downto 24)   => dlm_tx_data_int,
     DLM_FOUND_OUT               => open,
     DLM_DATA_OUT                => open,
     DLM_CLK_OUT                 => open,
@@ -802,8 +821,14 @@ begin
     TX_LINK_READY_IN            => link_tx_ready_i,
     TICK_MS_IN                  => tick_ms_int,
     -- DLM
-    DLM_INJECT_IN               => (others => '0'),
-    DLM_DATA_IN                 => (others => '0'),
+    DLM_INJECT_IN(0)            => dlm_inject_int,
+    DLM_INJECT_IN(1)            => dlm_inject_int,
+    DLM_INJECT_IN(2)            => dlm_inject_int,
+    DLM_INJECT_IN(3)            => dlm_inject_int,
+    DLM_DATA_IN(7 downto 0)     => dlm_tx_data_int,
+    DLM_DATA_IN(15 downto 8)    => dlm_tx_data_int,
+    DLM_DATA_IN(23 downto 16)   => dlm_tx_data_int,
+    DLM_DATA_IN(31 downto 24)   => dlm_tx_data_int,
     DLM_FOUND_OUT               => open,
     DLM_DATA_OUT                => open,
     DLM_CLK_OUT                 => open,
@@ -884,7 +909,7 @@ begin
     DLM_CLK_OUT                 => open,
     -- Debug                   
     STATUS_OUT                  => status_raw(4 * 32 - 1 downto 3 * 32),
-    DEBUG_OUT                   => open
+    DEBUG_OUT                   => debug --open
   );
 
 ---------------------------------------------------------------------------