bidirectional uart, IF

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index bfe059bf2623bd53bffabd48f71b39a6553050ac..1229532543e32993731e41c8ace4f5a5fc972ad1 100644 (file)
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -15,17 +15,17 @@ entity logicbox is
     INPUT  : in  std_logic_vector(3 downto 0);\r
     OUTPUT : out std_logic_vector(3 downto 0);\r
        \r
-       LED    : inout std_logic_vector(3 downto 0);\r
-       \r
-       STATUSI  : in  std_logic;\r
-       STATUSO  : in  std_logic;\r
-       CONTROLI : out std_logic;\r
-       CONTROLO : out std_logic;\r
-       \r
-       RX_OUT : out std_logic;\r
-       TX_IN  : in  std_logic;\r
-       CBUS   : in  std_logic\r
-       );\r
+    LED    : inout std_logic_vector(3 downto 0);\r
+    \r
+    STATUSI  : in  std_logic;\r
+    STATUSO  : in  std_logic;\r
+    CONTROLI : out std_logic;\r
+    CONTROLO : out std_logic;\r
+    \r
+    RX_OUT : out std_logic;\r
+    TX_IN  : in  std_logic;\r
+    CBUS   : in  std_logic\r
+    );\r
 end entity;\r
 \r
 architecture arch of logicbox is\r
@@ -47,6 +47,7 @@ architecture arch of logicbox is
   signal uart_read_out  : std_logic := '0';\r
   signal uart_write_out : std_logic := '0';\r
   signal uart_ready_in  : std_logic;\r
+  signal uart_busy_out  : std_logic;\r
   \r
   signal uart_rx_data : std_logic_vector(31 downto 0);\r
   signal uart_tx_data : std_logic_vector(31 downto 0);\r
@@ -54,6 +55,7 @@ architecture arch of logicbox is
   signal bus_read     : std_logic := '0';\r
   signal bus_write    : std_logic := '0';\r
   signal bus_ready    : std_logic; \r
+  signal bus_busy     : std_logic;\r
   \r
   signal input_i         : std_logic_vector(3 downto 0);\r
   signal input_selected  : std_logic_vector(3 downto 0); \r
@@ -67,7 +69,9 @@ architecture arch of logicbox is
   signal sed_error : std_logic;\r
   signal sed_debug : std_logic_vector(31 downto 0);\r
   signal controlsed_i : std_logic_vector(3 downto 0);\r
-\r
+  signal testreg1, testreg2 : std_logic_vector(31 downto 0);\r
+  \r
+  \r
   --PULSER\r
   -------------------------------------  \r
   signal pulser       : std_logic;\r
@@ -281,7 +285,7 @@ THE_UART : entity work.uart_sctrl
     WRITE_OUT => uart_write_out,\r
     READ_OUT  => uart_read_out,\r
     READY_IN  => uart_ready_in,\r
-    --READY_IN  => '1',\r
+    BUSY_OUT  => uart_busy_out,\r
     \r
     DEBUG     => open\r
     );\r
@@ -323,13 +327,15 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     SPI_WRITE_IN  => uart_write_out,\r
     SPI_READ_IN   => uart_read_out,\r
     SPI_READY_OUT => uart_ready_in,\r
+    SPI_BUSY_IN   => uart_busy_out,\r
 \r
     LOC_DATA_OUT  => uart_rx_data,\r
     LOC_DATA_IN   => uart_tx_data,\r
     LOC_ADDR_OUT  => uart_addr,\r
     LOC_WRITE_OUT => bus_write,\r
     LOC_READ_OUT  => bus_read,\r
-    LOC_READY_IN  => bus_ready\r
+    LOC_READY_IN  => bus_ready,\r
+    LOC_BUSY_OUT  => bus_busy\r
 \r
   );\r
 \r
@@ -355,7 +361,10 @@ PROC_REGS : process begin
       \r
       when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);\r
       when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);\r
-      \r
+\r
+      when x"ff" => uart_tx_data <= testreg1;              \r
+      when x"fe" => uart_tx_data <= testreg2;                    \r
+                    \r
       when others =>null;\r
     end case;\r
     \r
@@ -383,7 +392,10 @@ PROC_REGS : process begin
       when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);\r
       \r
       when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
-      \r
+\r
+      when x"ff" => testreg1 <= uart_rx_data(31 downto 0);\r
+      when x"fe" => testreg2 <= uart_rx_data(31 downto 0);\r
+                    \r
       when others => null;\r
     end case;\r
   end if;\r